WSdev Wiki

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  <siteinfo>
    <sitename>WSdev Wiki</sitename>
    <dbname>nesdev_db</dbname>
    <base>https://ws.nesdev.org/wiki/WSdev_Wiki</base>
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<page arvcontinue="">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>1</id>
    <timestamp>2022-04-12T23:50:02Z</timestamp>
    <contributor>
      <username>MediaWiki default</username>
      <id>2</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="755" xml:space="preserve">&lt;strong&gt;MediaWiki has been installed.&lt;/strong&gt;

Consult the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide] for information on using the wiki software.

== Getting started ==
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:Configuration_settings Configuration settings list]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [https://lists.wikimedia.org/postorius/lists/mediawiki-announce.lists.wikimedia.org/ MediaWiki release mailing list]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Localisation#Translation_resources Localise MediaWiki for your language]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:Combating_spam Learn how to combat spam on your wiki]</text>
    <sha1>11cef88175cf81168a86e7c0327a5b2d7a1920f5</sha1>
  </revision>
  <revision>
    <id>3</id>
    <parentid>1</parentid>
    <timestamp>2023-08-15T01:36:31Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Main page skeleton so there's something.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="50" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==</text>
    <sha1>29ed002989d0e68a0b9780b30f247a56f77f5095</sha1>
  </revision>
  <revision>
    <id>8</id>
    <parentid>3</parentid>
    <timestamp>2023-08-15T05:16:32Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Initial landing page.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="935" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)

=== Components ===

* [[Display]]
* [[Sound]]
* [[Timers]]
* [[Interrupts]]
* [[Serial port]]
* [[DMA]] (WonderSwan Color only)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>2be56d670a847fadb6e86249497f4d5c60b2a7bf</sha1>
  </revision>
  <revision>
    <id>10</id>
    <parentid>8</parentid>
    <timestamp>2023-08-15T06:09:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add start of WonderWitch section</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1026" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)

=== Components ===

* [[Display]]
* [[Sound]]
* [[Timers]]
* [[Interrupts]]
* [[Serial port]]
* [[DMA]] (WonderSwan Color only)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS interrupt list]]
* [[WonderWitch .fx files|.fx files]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>cc84191a68583bb8d956cfc9ec99083af96db825</sha1>
  </revision>
  <revision>
    <id>17</id>
    <parentid>10</parentid>
    <timestamp>2023-08-15T13:10:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add timing sub-page</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1039" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Components ===

* [[Display]]
* [[Sound]]
* [[Timers]]
* [[Interrupts]]
* [[Serial port]]
* [[DMA]] (WonderSwan Color only)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS interrupt list]]
* [[WonderWitch .fx files|.fx files]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>cdc2c7b75ad93df4070b5f7905a6ff9fbfb61621</sha1>
  </revision>
  <revision>
    <id>19</id>
    <parentid>17</parentid>
    <timestamp>2023-08-15T13:19:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add EEPROM, Mapper URLs</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1065" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Components ===

* [[Display]]
* [[Sound]]
* [[Timers]]
* [[Interrupts]]
* [[Serial port]]
* [[EEPROM]]
* [[DMA]] (WonderSwan Color only)
* [[Mapper]]

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS interrupt list]]
* [[WonderWitch .fx files|.fx files]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>137a5a03b3a9f8fa17239723c251aed67ae14f83</sha1>
  </revision>
  <revision>
    <id>20</id>
    <parentid>19</parentid>
    <timestamp>2023-08-15T13:21:27Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add more URLs</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1100" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Components ===

* [[Display]]
* [[Sound]]
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[Serial port]]
* [[EEPROM]]
* [[DMA]] (WonderSwan Color only)
* [[Mapper]]
  * [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>8ef262ac35e2ecb78b138dd02bef4a2fc5761bc7</sha1>
  </revision>
  <revision>
    <id>21</id>
    <parentid>20</parentid>
    <timestamp>2023-08-15T13:21:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1099" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Components ===

* [[Display]]
* [[Sound]]
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[Serial port]]
* [[EEPROM]]
* [[DMA]] (WonderSwan Color only)
* [[Mapper]]
** [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>cc4488eea5ac82239ba85446753b7df8a73ccac4</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>MediaWiki:Common.css</title>
  <ns>8</ns>
  <id>2</id>
  <revision>
    <id>2</id>
    <timestamp>2023-08-15T01:13:55Z</timestamp>
    <contributor>
      <username>Brizzo</username>
      <id>1</id>
    </contributor>
    <comment>Created page with "/* CSS placed here will be applied to all skins */  /* If a table is actually a table, you can add attractive borders    and dark gray TH by changing the first line to    {| class="tabular"  */ table.tabular {   margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px solid #aaa; border-collapse: collapse } table.tabular th, table.tabular td {   border: 1px solid #aaaaaa; padding: 0.2em } table.tabular th {   background: #f2f2f2; text-align: center } table.tabular caption..."</comment>
    <model>css</model>
    <format>text/css</format>
    <text bytes="18057" xml:space="preserve">/* CSS placed here will be applied to all skins */

/* If a table is actually a table, you can add attractive borders
   and dark gray TH by changing the first line to
   {| class="tabular"
 */
table.tabular {
  margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px solid #aaa; border-collapse: collapse
}
table.tabular th, table.tabular td {
  border: 1px solid #aaaaaa; padding: 0.2em
}
table.tabular th {
  background: #f2f2f2; text-align: center
}
table.tabular caption {
  margin-left: inherit; margin-right: inherit
}

table.oddf0 tr:nth-of-type(odd) {
  background: #F0F0F0;
}

table.evenf0 tr:nth-of-type(even) {
  background: #F0F0F0;
}

/*
 * Below taken directly from:
 * http://www.mediawiki.org/wiki/MediaWiki:Common.css
 */

/*
This is the CSS for all skins (for all users) on MediaWiki.org. 

SECTIONS:
1. Indication of namespaces
2. Color classes for content
3. Special pages
4. Main page styling
5. Sidebar external links
6. Extension:Matrix stuff
7. Wikitables, infobox templates, warnings, and other such stylings
8. Some other small things
*/

/** 1. INDICATION OF NAMESPACES **/

/* Pseudo NS Special (light grey) */
.ns--2 #content { background-color: #f4f4f4; }
.ns--2 div.thumb { border-color: #f4f4f4; } 

/* NS Project + Project_talk (light sky blue) */
.ns-4 #content, .ns-5 #content { background-color: #f8fcff; }
.ns-4 div.thumb, .ns-5 div.thumb { border-color: #f8fcff; } 

/* NS MediaWiki + MediaWiki_talk (light grey) */
.ns-8 #content, .ns-9 #content { background-color: #f4f4f4; }
.ns-8 div.thumb, .ns-9 div.thumb { border-color: #f4f4f4; } 

/* NS Manual + Manual_talk (light bluish violet) */
.ns-100 #content, .ns-101 #content { background-color: #f3f3ff; }
.ns-100 div.thumb, .ns-101 div.thumb { border-color: #f3f3ff; } 

/* NS Help (but NOT Help_talk) (blue border and Public Domain icon) */
.ns-12 #content {
	border: 2px solid #0000cc;
	border-right: none;
	background-image: url(http://upload.wikimedia.org/wikipedia/mediawiki/b/b8/PD-banner.png);
	background-repeat: no-repeat;
	background-position: right top;
}
.ns-12 #bodyContent {
	background-image: url(http://upload.wikimedia.org/wikipedia/mediawiki/6/67/PD-icon-faded.png);
	background-repeat: no-repeat;
	background-position: right 5em;
}

/***** 2. COLOR CLASSES FOR CONTENT  *****/
 
/* Border colors */
.borderc1 { border-color: #e9e9e9; border-width: thin; }
.borderc2 { border-color: #aaaaaa; border-width: thin; }
.borderc3 { border-color: #777777; border-width: thin; }
.borderc4 { border-color: #000000; border-width: thin; }
.borderc5 { border-color: #c00000; border-width: thin; }
.borderc6 { border-color: #025e9d; border-width: thin; }
.borderc7 { border-color: #008040; border-width: thin; }
.borderc8 { border-color: #ffcc00; border-width: thin; } /* Used by: [[Template:Welcome]]. */
 
/* Background colors */
.backgroundc1 { background-color: #ffffff; } /* Used by: [[Template:Welcome]]. */
.backgroundc2 { background-color: #f9f9f9; }
.backgroundc3 { background-color: #eeeeee; }
.backgroundc4 { background-color: #e0e0e0; }
.backgroundc5 { background-color: #d2d2d2; }
.backgroundc6 { background-color: #b7b7b7; }
.backgroundc7 { background-color: #a3a3a3; }
.backgroundc8 { background-color: #444455; }

/** 3. SPECIAL PAGES **/

/* Consistent special page navigation */
.SpecialPageInfo {
	background-color: #f9f9f9;
	background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/8/89/Exquisite-khelpcenter.png/35px-Exquisite-khelpcenter.png);
	background-position: 0.8em 0.5em;
	background-repeat: no-repeat;
	padding: 0.3em 0.5em 0.3em 5.0em;
	border-color: #025e9d; 
	border-width: 1px; 
	border-style: solid;
	border-bottom-width: medium;
	margin-bottom: 1em;
}

.mw-viewprevnext {
	display: block;
	border: 1px solid #cccccc;
	background-color: #f9f9f2;
	padding: 0.2em 0.4em;
}

/** 4. MAIN PAGE STYLING **/

#mainpage_topbox {
	background: #f9f9f9;
	padding: 0px;
	border: 1px solid #aaaaaa;
	margin: 0.2em 10px 10px;
}
.mainpage_boxtitle, .mainpage_hubtitle, #mainpage_pagetitle {
	font-size: 105%;
	padding: 0.4em;
	background-color: #eeeeee;
	border-bottom: 1px solid #aaaaaa;
}
.mainpage_boxtitle {
	line-height: 120%;
}
#mainpage_pagetitle {
	color: #cf7606;
	font-size: 200% !important;
}
#mainpage_sitelinks {
	padding: 0.2em;
	text-align: center;
	background-color: white;
}
.mainpage_hubtitle {
	text-align: center;
}
.mainpage_boxcontents, .mainpage_boxcontents_small {
	background: #ffffff;
	padding: 0.2em 0.4em;
}
.mainpage_boxcontents_small {
	font-size: 95%;
}
.mainpage_hubbox, #mainpage_newscell, #mainpage_downloadcell {
	padding: 0;
	border: 1px solid #aaaaaa;
}
.mainpage_hubbox {
	margin-bottom: 0;
}
#mainpage_newscell {
	margin-bottom: 15px;
	margin-top: 0 !important;
}
#mainpage_newscell .mainpage_boxtitle {
	background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/8/89/Exquisite-khelpcenter.png/20px-Exquisite-khelpcenter.png);
	background-repeat: no-repeat;
	background-position: 99% 0.3em;
	padding-right: 25px;
}
#mainpage_downloadcell {
	width: 17em;
	margin-bottom: 5px;
}
#mainpage_downloadcell .mainpage_boxtitle {
	background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/5/5d/Crystal_Clear_action_build.png/18px-Crystal_Clear_action_build.png);
	background-repeat: no-repeat;
	background-position: 96% 0.33em;
	padding-right: 25px;
}
#mainpage_mwtitle { color: #005288; } /* The words 'MediaWiki.org' in the title. */

/* The "mainpage" class is added to the body with JavaScript for the main page in all */
/* languages, so we can style things that apppear on the main page and also elsewhere. */
.mainpage #lastmod, 
.mainpage #siteSub, 
.mainpage h1.firstHeading {
	display: none !important;
} 
.mainpage #content {
	padding-top: 1em;
}

/** 5. SIDEBAR EXTERNAL LINKS **/

#n-blog-text a, #n-browse-svn a, #n-Statistics-for-SVN a, #n-phpdoc a, #n-svn-statistics a {
	background: url(/skins-1.5/monobook/external.png) center right no-repeat;
	padding-right: 13px;
	color: #3366bb;
}

/** 7. WIKITABLES, INFOBOX TEMPLATES, WARNINGS AND OTHER SUCH STYLINGS **/

/* Give wikitables blue headings */
.wikitable th, .wikitable td.hl3, .wikitable th.hl3 {
	background: #8da7d6;
}
.wikitable td.hl1, .wikitable th.hl1 {
	background: #c5d8fc;
}
.wikitable td.hl2, .wikitable th.hl2 {
	background: #a7c1f2;
}

/**
 * Make entire table valign=top,
 * To replace the |valign=top| on every cell.
 */
.vatop tr, tr.vatop, .vatop td, .vatop th {
	vertical-align: top;
}

/* General purpose "pretty (data) tables" */
table.datatable {
	background-color: transparent;
}

table.datatable th, table.datatable td {
	padding: 4px;
}

table.datatable th {
	text-align: left;
	background-color: #999999;
}

table.datatable tr {
	background-color: #cccccc;
}

table.datatable tr:hover {
	background-color: #ffffcc;
}

/* SideBox styling */
div.sideBox {
	position: relative;
	float: right;
	background: white;
	margin-left: 1em;
	border: 1px solid gray;
	padding: 0.3em;
	width: 200px;
	overflow: hidden; 
	clear: right;
}
div.sideBox dl {
	padding: 0;
	margin: 0 0 0.3em 0;
	font-size: 96%;
}
div.sideBox dl dt {
	background: none;
	margin: 0.4em 0 0 0;
}
div.sideBox dl dd {
	margin: 0.1em 0 0 1.1em;
	background-color: #f3f3f3;
}

/* Extension infobox styling */
.ext-infobox {
	border: 2px solid #aaaaaa;
	width: 272px;
	float: right;
	margin: 0 0 0.5em 0.5em;
	border-collapse: collapse;
	background-color: white;
}
.ext-infobox td {
	border: 2px none #aaaaaa;
	padding: 0.2em 0.5em;
	border-bottom: 1px solid #f0f0f0 !important;
}
.ext-header {
	background-color: #aaaaaa;
	color: white;
	text-align: left;
}
.ext-header td { padding-top: 0.5em; }
.ext-header img { padding: 0 0.2em 0 0.5em; }
.ext-status-unstable, .ext-status-unstable td { border-color: #990000; }
.ext-status-unstable .ext-header { background-color: #990000; color: #ffff00; }
.ext-status-experimental, .ext-status-experimental td { border-color: #ff4500; }
.ext-status-experimental .ext-header { background-color: #ff4500; }
.ext-status-beta, .ext-status-beta td { border-color: #ffba01; }
.ext-status-beta .ext-header { background-color: #ffba01; }
.ext-status-stable, .ext-status-stable td { border-color: #32cd32; }
.ext-status-stable .ext-header { background-color: #32cd32; }

/* Version box on [[Manual:Downloading MediaWiki]] */
#DownloadVersionBox {
	border: 2px solid black;
	border-collapse: collapse; 
	margin: auto;
	width: 50%;
	color: black;
}
#DownloadVersionBox td {
	border: 2px solid black;
	padding: 20px;
}

/* Major warning - used on the main page template to warn against editing carelessly, but can be used elsewhere as well */
.majorwarning {
	background: yellow; 
	padding: 0.3em; 
	text-align: center; 
	font-size: 125%; 
	border: 2px solid red;
}

/* Page headings used throughout the wiki (though not very much at the time of writing…) */ 
.page-notice, .page-warning {
	border-width: 1px; 
	border-style: solid;
	padding: 0.3em 0.5em;
	margin-bottom: 1em;
	width: 95%; 
	margin-left: auto; 
	margin-right: auto; 
	text-align: center;
}

/* Informative notices at the top of pages (blue) */
.page-notice {
	background-color: #f9f9f9;
	border-color: #025e9d; 
	text-align: left;
}

/* Warning information at the top of pages (red) */
.page-warning {
	background-color: #ffffff;
	border-color: #c51919;
	border-width: 2px;
}
.pw-head {
	color: #c51919;
	font-weight: bold;
}

/* Used in Template:Notice */
.block-note {
	background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/6/60/Bulbgraph.png/18px-Bulbgraph.png);
	background-position: top left;
	background-repeat: no-repeat;
}
/*
   Using block-contents in the hope that it can apply to all block-level warning templates, 
   with different images applied as backgrounds to the wrapping DIV.
*/
.block-contents {
	display: block;
	padding-left: 20px;
}

/* Template documentation ([[Template:Documentation]]) */
.template-documentation {
	clear: both;
	margin: 1em 0 0 0;
	border: 1px solid #aaa; 
	background-color: #ecfcf4; 
	padding: 5px;
}

/** 8. SOME OTHER SMALL THINGS **/

/* Give a bit of space to the TOC */
#toc { margin: 1em 0; }

/* Allow limiting of which header levels are shown in a TOC;
   &lt;div class="toclimit-3"&gt;, for instance, will limit to
   showing ==headings== and ===headings=== but no further.
   Used in [[Template:TOCright]]
 */
.toclimit-2 .toclevel-1 ul,
.toclimit-3 .toclevel-2 ul,
.toclimit-4 .toclevel-3 ul,
.toclimit-5 .toclevel-4 ul,
.toclimit-6 .toclevel-5 ul,
.toclimit-7 .toclevel-6 ul {
	display: none;
}

/* make the list of references look smaller and highlight clicked reference in blue */
ol.references { font-size: 100%; }
.references-small { font-size: 90%; }
ol.references &gt; li:target { background-color: #ddeeff; }
sup.reference:target { background-color: #ddeeff; }

/* extra buttons for edit dialog (from commons:MediaWiki:Common.css) */
.my-buttons {
	padding: .5em;
}
.my-buttons a {
	color: black;
	background-color: #cde !important;
	font-weight: bold;
	font-size: .9em;
	text-decoration: none;
	border: thin #069 outset;
	padding: 0 .1em .1em;
}
.my-buttons a:hover, .my-buttons a:active {
	background-color: #bcd;
	border-style: inset;
}

/* from [[User:Splarka/Help:Linked images]] */
.imagelink_wikilogo a {
	width: 135px;
	height: 135px;
	display: block;
	text-decoration: none;
	background-image: url("http://upload.wikimedia.org/wikipedia/mediawiki/b/bc/Wiki.png");
}

/** reduced subset of the mbox styles from enwiki, mainly for the nice boxflow **/
table.mbox {
	margin: 4px 10%;
	border-collapse: collapse;
	border: 1px solid #aaa; /* Default "notice" gray */
	background: #f9f9f9;
}
table.mbox-wide {
	margin: 4px 0;
}

th.mbox-text, td.mbox-text {     /* The message body cell(s) */
	border: none;
	padding: 0.25em 0.9em;       /* 0.9em left/right */
	width: 100%;    /* Make all mboxes the same width regardless of text length */
}
td.mbox-image {                  /* The left image cell */
	border: none;
	padding: 2px 0 2px 0.9em;    /* 0.9em left, 0px right */
	text-align: center;
}
td.mbox-imageright {             /* The right image cell */
	border: none;
	padding: 2px 0.9em 2px 0;    /* 0px left, 0.9em right */
	text-align: center;
}
td.mbox-empty-cell {         /* An empty narrow cell */
	border: none;
	padding: 0px;
	width: 1px;
}

/* These mbox-small classes must be placed after all other 
   ambox/tmbox/ombox etc classes. "body.mediawiki" is so 
   they override "table.ambox + table.ambox" above. */
body.mediawiki table.mbox-small {   /* For the "small=yes" option. */
	clear: right;
	float: right;
	margin: 4px 0 4px 1em;
	width: 238px;
	font-size: 88%;
	line-height: 1.25em;
}
body.mediawiki table.mbox-small-left {   /* For the "small=left" option. */
	margin: 4px 1em 4px 0;
	width: 238px;
	border-collapse: collapse;
	font-size: 88%;
	line-height: 1.25em;
}

/* These are the same colours as the enwiki
   'cmbox' styles; just with different names. */
table.mbox-critical {
	border: 4px solid #b22222;    /* Red */
	background: #FFDBDB;          /* Pink */
}
table.mbox-important {
	background: #FFDBDB;    /* Red */
}
table.mbox-warning {
	background: #FFE7CE;    /* Orange */
}
table.mbox-caution {
	background: #FFF9DB;    /* Yellow */
}
table.mbox-notice {
	background: #D8E8FF;    /* Blue */
}
table.mbox-move {
	background: #E4D8FF;    /* Purple */
}
table.mbox-protection {
	background: #EFEFE1;    /* Gray-gold */
}

/**
 * Infoboxes
 */
.infobox {
	float: right;
	clear: right;
	margin-bottom: 0.5em;
	margin-left: 1em;
	padding: 0.2em;
	border: 1px solid #AAA;
	background: #F9F9F9;
	color: black;
}
 
.infobox td,
.infobox th {
	vertical-align: top;
}
 
.infobox caption {
	margin-left: inherit;
	font-size: larger;
}
 
.infobox.bordered {
	border-collapse: collapse;
}
 
.infobox.bordered td,
.infobox.bordered th {
	border: 1px solid #AAA;
}
 
.infobox.bordered .borderless td,
.infobox.bordered .borderless th {
	border: 0;
}

/* Apparently the namespaces parameter
  for inputbox forces a checkbox.
  Let's hide it in the API sidebar */
.mw-inputbox-hideapicheck label[for=mw-inputbox-ns104],
#mw-inputbox-ns104 {
	display: none;
}

/** Testing for code review **/
div.mw-wordcloud { 
	width: 100%;
	text-align: justify;
}

.mw-wordcloud-size-1 {
	color: #222;
	font-size: 2.4em;
}
.mw-wordcloud-size-2 {
	color: #333;
	font-size:2.2em;
}
.mw-wordcloud-size-3 {
	color: #444;
	font-size: 2.0em;
}
.mw-wordcloud-size-4 {
	color: #555;
	font-size: 1.8em;
}
.mw-wordcloud-size-5 {
	color: #666;
	font-size: 1.6em;
}
.mw-wordcloud-size-6 {
	color: #777;
	font-size: 1.4em;
}
.mw-wordcloud-size-7 {
	color: #888;
	font-size: 1.2em;
}
.mw-wordcloud-size-8 {
	color: #999;
	font-size: 1em;
}
.mw-wordcloud-size-9 {
	color: #aaa;
	font-size: 0.8em;
	letter-spacing: 3px;
}
.mw-wordcloud-size-10, .mw-wordcloud-size-0 {
	color: #bbb;
	font-size: 0.8em;
}

/* Styling for related links and disambiguation links */
.rellink, .dablink {
	font-style: italic;
	margin-bottom: 0.5em;
	padding-left: 2em;
}

/* @todo FIXME: document me :) */
#signuptopbox li {
	float: left;
	list-style: none;
	font-family: sans-serif;
}
#signuptopbox li {
	color: #3ca7d4;
	background: #c2e1f9;
	line-height: 2.8em;
	margin-right: .25em;
	padding-right: .5em;
}
#signuptopbox li.pr-active, #signuptopbox li.pr-active div {
	color: #67ca36;
	background: #d4f9c2;
	border-color: #fff #fff #fff #67ca36;
}
#signuptopbox li div{
	width: 0;
	height: 0;
	border-color: #fff #fff #fff #3CA7D4;
	border-style: solid;
	border-width: 1.4em .3em 1.4em 1.4em;
	float: left;
}
#signuptopbox li span.pr-number{
	display: block;
	width: 1.8em;
	line-height: 1.8em;
	background: #3ca7d4;
	color: #c2e1f9;
	text-align: center;
	margin: .5em;
	-webkit-border-radius: 50%;
	-moz-border-radius: 50%;
	-ms-border-radius: 50%;
	-o-border-radius: 50%;
	border-radius: 50%;
	font-weight: 600;
	float: left;
}
#signuptopbox li.pr-active span.pr-number {
	background: #67ca36;
	color: #d4f9c2;
}
#signuptopbox li span {
	float: left;
}
#signuptopbox li.pr-spacer {
	padding: 0;
}

/* BREADCRUMB CODE */
 
.breadcrumb {
        list-style: none;
        overflow: hidden;
        font: 14px Helvetica, Arial, Sans-Serif;
}
.breadcrumb li {
        float: left;
        margin-bottom: 0;
}
.breadcrumb li a {
        color: white;
        text-decoration: none;
        padding: 10px 0 10px 45px;
        position: relative;
        display: block;
        float: left;
}
 
.breadcrumb li a:after {
        content: " ";
        display: block;
        width: 0;
        height: 0;
        border-top: 50px solid transparent;           /* Go big on the size, and let overflow hide */
        border-bottom: 50px solid transparent;
        position: absolute;
        top: 50%;
        margin-top: -50px;
        left: 100%;
        z-index: 2;
}
 
.breadcrumb li a:before {
        content: " ";
        display: block;
        width: 0;
        height: 0;
        border-top: 50px solid transparent;
        border-bottom: 50px solid transparent;
        border-left: 31px solid white;
        position: absolute;
        top: 50%;
        margin-top: -50px;
        margin-left: 1px;
        left: 100%;
        z-index: 1;
}
 
.breadcrumb li:first-child a {
        padding-left: 20px;
}
 
.currentcrumb a {
        background: #069;
}
 
.currentcrumb a:after {
        border-left: 30px solid #069;
}
 
.currentcrumb a:hover, .prevcrumb a:hover, .nextcrumb a:hover {
        background: #002d44;
}
 
.currentcrumb a:hover:after, .prevcrumb a:hover:after, .nextcrumb a:hover:after { border-left-color: #002d44 !important; }
 
.prevcrumb a {
        background: #396;
}
 
.prevcrumb a:after {
        border-left: 30px solid #396;
}
 
.nextcrumb a {
        background: #999;
}
 
.nextcrumb a:after {
        border-left: 30px solid #999;
}

/* bug 27375, To go in ext.codereview */
.mw-codereview-diff ins {
	background: #EDFFED;
}
.mw-codereview-diff del {
	background: #FFEDED;
}
/* bug 29307, awaiting deployment */
pre {
	line-height: 1.3em;
}

/*
 * End mediawiki.org import
 */

pre,.mw-code { white-space:pre; overflow-x: auto; }</text>
    <sha1>7b014c1d6648715d37f0e5bdbc8085bd023638be</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>MediaWiki:Loginprompt</title>
  <ns>8</ns>
  <id>3</id>
  <revision>
    <id>4</id>
    <timestamp>2023-08-15T01:46:21Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds log-in prompt explaining how to register an account.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="287" xml:space="preserve">Looking to register an account? Because of spam, accounts are currently created manually by request. Please reach out to Fiskbit or lidnariq on the [http://forums.nesdev.org/ NESdev forums] or [https://discord.gg/JSG4kuF8EK NESdev Discord server] if you'd like to contribute to the wiki.</text>
    <sha1>250f3ff9f50ef5476c10ce328ab8981594ebfd68</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>MediaWiki:Sidebar</title>
  <ns>8</ns>
  <id>4</id>
  <revision>
    <id>5</id>
    <timestamp>2023-08-15T01:55:43Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>‎Updates the sidebar.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="200" xml:space="preserve">* navigation
** mainpage|Wiki main page
** http://forums.nesdev.org/ | NESdev Forums
** https://discord.gg/JSG4kuF8EK | NESdev Discord
** recentchanges-url|recentchanges
* SEARCH
* TOOLBOX
* LANGUAGES</text>
    <sha1>d3889c8a1c188f221c689d5bb4dca061db57ed59</sha1>
  </revision>
  <revision>
    <id>6</id>
    <parentid>5</parentid>
    <timestamp>2023-08-15T02:13:47Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds WonderSwan Discord invite.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="244" xml:space="preserve">* navigation
** mainpage|Wiki main page
** http://forums.nesdev.org/ | NESdev Forums
** https://discord.gg/JSG4kuF8EK | NESdev Discord
** https://discord.gg/6hFZY5ce | WS Discord
** recentchanges-url|recentchanges
* SEARCH
* TOOLBOX
* LANGUAGES</text>
    <sha1>4a4323f9a6c0ecb3be9558fe10332aceef5d03ce</sha1>
  </revision>
  <revision>
    <id>7</id>
    <parentid>6</parentid>
    <timestamp>2023-08-15T02:29:24Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Swaps out WS Discord link for hopefully-permanent version.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="243" xml:space="preserve">* navigation
** mainpage|Wiki main page
** http://forums.nesdev.org/ | NESdev Forums
** https://discord.gg/JSG4kuF8EK | NESdev Discord
** https://discord.gg/7rmX2QJ | WS Discord
** recentchanges-url|recentchanges
* SEARCH
* TOOLBOX
* LANGUAGES</text>
    <sha1>822d68b76e3bb3a1837509e8f7956610cca52a9c</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>9</id>
    <timestamp>2023-08-15T06:04:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.  == ROM header ==  Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.  {| class="wikitable" |+ Header contents |- ! Offset !! Length !! Contents |- | '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment. |- | '''$5''' || '''1''' || '''Maintenance''' |- | $6 || 1 || Developer/Publishe..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4302" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper type
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== $5 - Maintenance ===

&lt;pre&gt;
s...0000
|   ++++- Must be zero; otherwise the console will prohibit execution.
|         Purpose unknown.
+-------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
          Bypasses the custom boot splash stored in the console's
          internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== $6 - Developer/Publisher ID ===

{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher
|-
| $01 || Bandai
|-
| $02 || Taito
|-
| $03 || ?
|-
| $04 || Koei
|-
| $05 || Data East
|-
| $06 || Asmik Ace
|-
| $07 || Media Entertainment
|-
| $08 || Nichibutsu
|-
| $0A || Coconuts Japan
|-
| $0B || Sammy
|-
| $0C || Sunsoft
|-
| $0D || ?
|-
| $0E || Banpresto
|-
| $10 || Jaleco
|-
| $11 || Imagineer
|-
| $12 || Konami
|-
| $16 || Kobunsha
|-
| $17 || Bottom Up
|-
| $18 || ?
|-
| $19 || Sunrise
|-
| $1A || Cyber Front
|-
| $1B || Megahouse
|-
| $1D || Interbec
|-
| $1E || ?
|-
| $1F || ?
|-
| $20 || Athena
|-
| $21 || KID
|-
| $22 || ?
|-
| $23 || ?
|-
| $24 || Omega Micott
|-
| $25 || ?
|-
| $26 || ?
|-
| $27 || ?
|-
| $28 || Squaresoft
|-
| $2A || ?
|-
| $2B || ?
|-
| $2D || Namco
|-
| $2E || ?
|-
| $2F || ?
|-
| $31 || ?
|-
| $32 || ?
|-
| $33 || ?
|-
| $36 || ?
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== $7 - Color ===

&lt;pre&gt;
???????c
       +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== $9 - Game version? / Safe mode ===

&lt;pre&gt;
pvvvvvvv
|+++++++- Game version?
+-------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
          This prohibits writing to the internal EEPROM for addresses
          0x60 and above (user settings, custom splash screen).
          Games are expected to enable write protection; however, the
          WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== $A - ROM size ===

Unofficial ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''&lt;ref name="2003only"&gt;Not supported by the [[Bandai 2001]] mapper, which is limited to 16 MiB. The [[Bandai 2003]] mapper is limited to 64 MiB.&lt;/ref&gt;
|-
| ''$0B'' || ''512 Mbit (64 MiB)''&lt;ref name="2003only"/&gt;
|}

=== $B - Save type/size ===

{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== $C - Flags ===

&lt;pre&gt;
?????SBv
     ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
     ||   Controls the splash screen's orientation.
     |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
     +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== $D - Mapper type ===

{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>f4cf7c069d1cce48e80e1b798b3f4746c8d3182f</sha1>
  </revision>
  <revision>
    <id>11</id>
    <parentid>9</parentid>
    <timestamp>2023-08-15T06:11:55Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds byte bit markings.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4442" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper type
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== $5 - Maintenance ===

&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== $6 - Developer/Publisher ID ===

{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher
|-
| $01 || Bandai
|-
| $02 || Taito
|-
| $03 || ?
|-
| $04 || Koei
|-
| $05 || Data East
|-
| $06 || Asmik Ace
|-
| $07 || Media Entertainment
|-
| $08 || Nichibutsu
|-
| $0A || Coconuts Japan
|-
| $0B || Sammy
|-
| $0C || Sunsoft
|-
| $0D || ?
|-
| $0E || Banpresto
|-
| $10 || Jaleco
|-
| $11 || Imagineer
|-
| $12 || Konami
|-
| $16 || Kobunsha
|-
| $17 || Bottom Up
|-
| $18 || ?
|-
| $19 || Sunrise
|-
| $1A || Cyber Front
|-
| $1B || Megahouse
|-
| $1D || Interbec
|-
| $1E || ?
|-
| $1F || ?
|-
| $20 || Athena
|-
| $21 || KID
|-
| $22 || ?
|-
| $23 || ?
|-
| $24 || Omega Micott
|-
| $25 || ?
|-
| $26 || ?
|-
| $27 || ?
|-
| $28 || Squaresoft
|-
| $2A || ?
|-
| $2B || ?
|-
| $2D || Namco
|-
| $2E || ?
|-
| $2F || ?
|-
| $31 || ?
|-
| $32 || ?
|-
| $33 || ?
|-
| $36 || ?
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== $7 - Color ===

&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== $9 - Game version? / Safe mode ===

&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== $A - ROM size ===

Unofficial ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''&lt;ref name="2003only"&gt;Not supported by the [[Bandai 2001]] mapper, which is limited to 16 MiB. The [[Bandai 2003]] mapper is limited to 64 MiB.&lt;/ref&gt;
|-
| ''$0B'' || ''512 Mbit (64 MiB)''&lt;ref name="2003only"/&gt;
|}

=== $B - Save type/size ===

{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== $C - Flags ===

&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== $D - Mapper type ===

{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>d49fc9d8b2d6d10c390e8679f09105ad969e5894</sha1>
  </revision>
  <revision>
    <id>12</id>
    <parentid>11</parentid>
    <timestamp>2023-08-15T06:14:59Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Manually adds horizontal lines to try to break up the page a bit.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4474" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper type
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== $5 - Maintenance ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== $6 - Developer/Publisher ID ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher
|-
| $01 || Bandai
|-
| $02 || Taito
|-
| $03 || ?
|-
| $04 || Koei
|-
| $05 || Data East
|-
| $06 || Asmik Ace
|-
| $07 || Media Entertainment
|-
| $08 || Nichibutsu
|-
| $0A || Coconuts Japan
|-
| $0B || Sammy
|-
| $0C || Sunsoft
|-
| $0D || ?
|-
| $0E || Banpresto
|-
| $10 || Jaleco
|-
| $11 || Imagineer
|-
| $12 || Konami
|-
| $16 || Kobunsha
|-
| $17 || Bottom Up
|-
| $18 || ?
|-
| $19 || Sunrise
|-
| $1A || Cyber Front
|-
| $1B || Megahouse
|-
| $1D || Interbec
|-
| $1E || ?
|-
| $1F || ?
|-
| $20 || Athena
|-
| $21 || KID
|-
| $22 || ?
|-
| $23 || ?
|-
| $24 || Omega Micott
|-
| $25 || ?
|-
| $26 || ?
|-
| $27 || ?
|-
| $28 || Squaresoft
|-
| $2A || ?
|-
| $2B || ?
|-
| $2D || Namco
|-
| $2E || ?
|-
| $2F || ?
|-
| $31 || ?
|-
| $32 || ?
|-
| $33 || ?
|-
| $36 || ?
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== $7 - Color ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== $9 - Game version? / Safe mode ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== $A - ROM size ===
----
Unofficial ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''&lt;ref name="2003only"&gt;Not supported by the [[Bandai 2001]] mapper, which is limited to 16 MiB. The [[Bandai 2003]] mapper is limited to 64 MiB.&lt;/ref&gt;
|-
| ''$0B'' || ''512 Mbit (64 MiB)''&lt;ref name="2003only"/&gt;
|}

=== $B - Save type/size ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== $C - Flags ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== $D - Mapper type ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>fa0f7ba0dbbbb05654a5132b6c4cae654497fa41</sha1>
  </revision>
  <revision>
    <id>14</id>
    <parentid>12</parentid>
    <timestamp>2023-08-15T06:18:21Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>remove references in ROM type section</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4436" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper type
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== $5 - Maintenance ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== $6 - Developer/Publisher ID ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher
|-
| $01 || Bandai
|-
| $02 || Taito
|-
| $03 || ?
|-
| $04 || Koei
|-
| $05 || Data East
|-
| $06 || Asmik Ace
|-
| $07 || Media Entertainment
|-
| $08 || Nichibutsu
|-
| $0A || Coconuts Japan
|-
| $0B || Sammy
|-
| $0C || Sunsoft
|-
| $0D || ?
|-
| $0E || Banpresto
|-
| $10 || Jaleco
|-
| $11 || Imagineer
|-
| $12 || Konami
|-
| $16 || Kobunsha
|-
| $17 || Bottom Up
|-
| $18 || ?
|-
| $19 || Sunrise
|-
| $1A || Cyber Front
|-
| $1B || Megahouse
|-
| $1D || Interbec
|-
| $1E || ?
|-
| $1F || ?
|-
| $20 || Athena
|-
| $21 || KID
|-
| $22 || ?
|-
| $23 || ?
|-
| $24 || Omega Micott
|-
| $25 || ?
|-
| $26 || ?
|-
| $27 || ?
|-
| $28 || Squaresoft
|-
| $2A || ?
|-
| $2B || ?
|-
| $2D || Namco
|-
| $2E || ?
|-
| $2F || ?
|-
| $31 || ?
|-
| $32 || ?
|-
| $33 || ?
|-
| $36 || ?
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== $7 - Color ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== $9 - Game version? / Safe mode ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== $A - ROM size ===
----
Unofficial ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapperr. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== $B - Save type/size ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== $C - Flags ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== $D - Mapper type ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>eb6c403dab6aaac4f237252f252f389cf14f73e6</sha1>
  </revision>
  <revision>
    <id>15</id>
    <parentid>14</parentid>
    <timestamp>2023-08-15T06:18:32Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>fix typo</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4435" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper type
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== $5 - Maintenance ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== $6 - Developer/Publisher ID ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher
|-
| $01 || Bandai
|-
| $02 || Taito
|-
| $03 || ?
|-
| $04 || Koei
|-
| $05 || Data East
|-
| $06 || Asmik Ace
|-
| $07 || Media Entertainment
|-
| $08 || Nichibutsu
|-
| $0A || Coconuts Japan
|-
| $0B || Sammy
|-
| $0C || Sunsoft
|-
| $0D || ?
|-
| $0E || Banpresto
|-
| $10 || Jaleco
|-
| $11 || Imagineer
|-
| $12 || Konami
|-
| $16 || Kobunsha
|-
| $17 || Bottom Up
|-
| $18 || ?
|-
| $19 || Sunrise
|-
| $1A || Cyber Front
|-
| $1B || Megahouse
|-
| $1D || Interbec
|-
| $1E || ?
|-
| $1F || ?
|-
| $20 || Athena
|-
| $21 || KID
|-
| $22 || ?
|-
| $23 || ?
|-
| $24 || Omega Micott
|-
| $25 || ?
|-
| $26 || ?
|-
| $27 || ?
|-
| $28 || Squaresoft
|-
| $2A || ?
|-
| $2B || ?
|-
| $2D || Namco
|-
| $2E || ?
|-
| $2F || ?
|-
| $31 || ?
|-
| $32 || ?
|-
| $33 || ?
|-
| $36 || ?
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== $7 - Color ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== $9 - Game version? / Safe mode ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== $A - ROM size ===
----
Unofficial ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== $B - Save type/size ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== $C - Flags ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== $D - Mapper type ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>d71bd563a6e4fd796717380ef1d8c461dfa31d70</sha1>
  </revision>
  <revision>
    <id>27</id>
    <parentid>15</parentid>
    <timestamp>2023-08-18T08:42:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add missing developer/publisher IDs (from up-n-atom)</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4909" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper type
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== $5 - Maintenance ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== $6 - Developer/Publisher ID ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || ?
|-
| $2F || HTR || ?
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== $7 - Color ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== $9 - Game version? / Safe mode ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== $A - ROM size ===
----
Unofficial ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== $B - Save type/size ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== $C - Flags ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== $D - Mapper type ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>e48ca0e20772b24b508358358f7db5a544b2f78f</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>WonderWitch .fx files</title>
  <ns>0</ns>
  <id>6</id>
  <revision>
    <id>13</id>
    <timestamp>2023-08-15T06:17:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "[[FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.  == Format ==  {| class="wikitable" |+ Header contents |- ! Offset..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1382" xml:space="preserve">[[FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.

== Format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;code&gt;#!ws&lt;/code&gt;
|-
| $04 || 60 || Padding; unused.
|-
| $40 || 16 || File name; zero-terminated Shift-JIS string.
|-
| $50 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| $68 || 4 || ?
|-
| $6C || 4 || Total file size, in bytes, excluding the header.
|-
| $70 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| $72 || 2 || File mode
|-
| $74 || 4 || Modification time - seconds since January 1st, 2000.
|-
| $78 || 4 || ?
|-
| $7C || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== File mode ===
----
&lt;pre&gt;

15      bit       0
---- ---- ---- ----
???? ???? ??i? ?rwx
            |   ||+- Execute
            |   |+-- Write
            |   +--- Read
            +------- Intermediate library
&lt;/pre&gt;</text>
    <sha1>4aea7eb5b6d30ce32c95c383a36adfbf5703174f</sha1>
  </revision>
  <revision>
    <id>16</id>
    <parentid>13</parentid>
    <timestamp>2023-08-15T06:19:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>clarify padding format</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1390" xml:space="preserve">[[FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.

== Format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;code&gt;#!ws&lt;/code&gt;
|-
| $04 || 60 || Padding; typically 0xFF.
|-
| $40 || 16 || File name; zero-terminated Shift-JIS string.
|-
| $50 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| $68 || 4 || ?
|-
| $6C || 4 || Total file size, in bytes, excluding the header.
|-
| $70 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| $72 || 2 || File mode
|-
| $74 || 4 || Modification time - seconds since January 1st, 2000.
|-
| $78 || 4 || ?
|-
| $7C || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== File mode ===
----
&lt;pre&gt;

15      bit       0
---- ---- ---- ----
???? ???? ??i? ?rwx
            |   ||+- Execute
            |   |+-- Write
            |   +--- Read
            +------- Intermediate library
&lt;/pre&gt;</text>
    <sha1>aadb0b65daa3b66207b9d9e69ce04a847f834fd3</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>Timing</title>
  <ns>0</ns>
  <id>7</id>
  <revision>
    <id>18</id>
    <timestamp>2023-08-15T13:17:54Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Clocks ==  The WonderSwan is clocked with a master clock of approximately 12288000 Hz (= 12.288 MHz).  This clock is split into four internal memory access quadrants, running at 3072000 Hz (= 3.072 MHz) each. Three of those are used by the console in "mono" mode: [[CPU|NEC V30MZ]], [[Display]] and [[Sound]]. On the WonderSwan Color, the fourth quadrant is used to handle color palette reads during display drawing.  Out of those, only the CPU quadrant can access the car..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="998" xml:space="preserve">== Clocks ==

The WonderSwan is clocked with a master clock of approximately 12288000 Hz (= 12.288 MHz).

This clock is split into four internal memory access quadrants, running at 3072000 Hz (= 3.072 MHz) each. Three of those are used by the console in "mono" mode: [[CPU|NEC V30MZ]], [[Display]] and [[Sound]]. On the WonderSwan Color, the fourth quadrant is used to handle color palette reads during display drawing.

Out of those, only the CPU quadrant can access the cartridge bus. It can be additionally configured to use one of two wait states:

* 1 cycle access - an effective bus speed of 3072000 Hz, same as the CPU,
* 3 cycle access - an effective bus speed of 1024000 Hz.

== Display ==

By default, a WonderSwan frame consists of 159 lines, 144 of which are visible. Each line consists of 256 clock cycles, of which 224 are used to draw a pixel at a time. This leads to a total duration of 40704 clock cycles per frame, for an effective default refresh rate of approximately 75.472 Hz.</text>
    <sha1>ef2d69d3b48f50e99434f7337ecad113a492d7d3</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>22</id>
    <timestamp>2023-08-16T22:31:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "* Superscripts are used to mark ports specific to a given mode or platform: ** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. ** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;. * If two Bits rows are provided, the second one refers to the "Color" mode. * The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).  {| class="wikitable" ! Category ! Port ! Description ! Bits ! Type ! Notes |- ! rowspan="45" | Displ..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17163" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Shade LUT|LCD Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Shade LUT|LCD Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Shade LUT|LCD Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Shade LUT|LCD Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | Timers
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! Interrupts
! $B0
| Interrupt Vector
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv v...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! UART
! $B1
| Serial Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! Interrupts
! $B2
| Interrupt Enable
|
| RW8
|
|-
! UART
! $B3
| Serial Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .rot&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Receive ready (r), Overrun (o), Transfer ready (t)
|-
! Interrupts
! $B4
| Interrupt Status
|
| RW8
|
|-
! Keypad
! $B5
| Keypad
|
| RW8
|
|-
! rowspan="2" | Interrupts
! $B6
| Interrupt Acknowledge
|
| RW8
|
|-
! $B7
| Interrupt NMI Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
|}</text>
    <sha1>b361ace8489a13c4588fc34ea6733bfe33c5b64c</sha1>
  </revision>
  <revision>
    <id>23</id>
    <parentid>22</parentid>
    <timestamp>2023-08-16T22:33:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>Mono Shade LUT</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17203" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | Timers
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! Interrupts
! $B0
| Interrupt Vector
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv v...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! UART
! $B1
| Serial Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! Interrupts
! $B2
| Interrupt Enable
|
| RW8
|
|-
! UART
! $B3
| Serial Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .rot&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Receive ready (r), Overrun (o), Transfer ready (t)
|-
! Interrupts
! $B4
| Interrupt Status
|
| RW8
|
|-
! Keypad
! $B5
| Keypad
|
| RW8
|
|-
! rowspan="2" | Interrupts
! $B6
| Interrupt Acknowledge
|
| RW8
|
|-
! $B7
| Interrupt NMI Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
|}</text>
    <sha1>1f2d621f492beead934b0c7775392bb4b83e27b0</sha1>
  </revision>
  <revision>
    <id>24</id>
    <parentid>23</parentid>
    <timestamp>2023-08-17T09:18:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>clarify keypad port</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17331" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | Timers
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! Interrupts
! $B0
| Interrupt Vector
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv v...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! UART
! $B1
| Serial Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! Interrupts
! $B2
| Interrupt Enable
|
| RW8
|
|-
! UART
! $B3
| Serial Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .rot&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Receive ready (r), Overrun (o), Transfer ready (t)
|-
! Interrupts
! $B4
| Interrupt Status
|
| RW8
|
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | Interrupts
! $B6
| Interrupt Acknowledge
|
| RW8
|
|-
! $B7
| Interrupt NMI Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
|}</text>
    <sha1>4ceb54e7c335f905aa2606f4ac2877f1b09282e5</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>Keypad</title>
  <ns>0</ns>
  <id>9</id>
  <revision>
    <id>25</id>
    <timestamp>2023-08-17T09:28:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan SoC features a 4 by 3 keypad matrix.  == Scanning ==  Scanning is done via writing to and reading from port $B5.  &lt;pre&gt; 7  bit  0 ---- ---- .iii oooo  ||| ++++- Output rows (0-3)  +++------ Input rows  (4-6) &lt;/pre&gt;  The standard procedure is to read rows 4, 5 and 6 in order, shifting their values into one twelve-bit mask like so:  &lt;pre&gt; 15      bit       0 ---- ---- ---- ---- .... 4444 5555 6666 &lt;/pre&gt;  Typical keypad scanning implementations introduce a d..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2746" xml:space="preserve">The WonderSwan SoC features a 4 by 3 keypad matrix.

== Scanning ==

Scanning is done via writing to and reading from port $B5.

&lt;pre&gt;
7  bit  0
---- ----
.iii oooo
 ||| ++++- Output rows (0-3)
 +++------ Input rows  (4-6)
&lt;/pre&gt;

The standard procedure is to read rows 4, 5 and 6 in order, shifting their values into one twelve-bit mask like so:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... 4444 5555 6666
&lt;/pre&gt;

Typical keypad scanning implementations introduce a delay between writing to and reading from the matrix, allowing the scanned values to stabilize. For example, one can use the DAA opcode for doing so.

== Startup override ==

On startup, the [[boot ROM]] checks whether or not certain output rows are forced high when all input rows are disabled. This triggers a startup override:

* Input row 0 - jump to 4000:0000,
* Input row 1 - jump to 4000:0010.

As this override is done before boot ROM lockout, it can be used to dump the boot ROM.

== Keypad arrangement ==

=== WonderSwan ===

==== Layout ====

&lt;pre&gt;
    Y1
 Y4    Y2
    Y3


    X1
 X4    X2                              A
    X3       Sound Start Power      B
                    (St)
&lt;/pre&gt;

Sound and Power buttons are not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Y4 - Y3 - Y2 - Y1 -
      |    |    |    |
5--- X4 - X3 - X2 - X1 -
      |    |    |    |
6---  B -  A - St ---+--
      |    |    |    |

&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... yyyy xxxx bas.
     |||| |||| ||+- Start
     |||| |||| |+-- A
     |||| |||| +--- B
     |||| ++++----- X4, X3, X2, X1
     ++++---------- Y4, Y3, Y2, Y1      
&lt;/pre&gt;

=== Pocket Challenge V2 ===

==== Layout ====

&lt;pre&gt;
  Power


     Esc
                                 View
   Up                                  Clear
                                       (Clr)
 Lft Rgh                           Circle
                                    (Crc)
   Dwn                           Pass
                                (Pas)
&lt;/pre&gt;

The Power switch is not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Pas  Crc --+-- Clr -
      |    |    |    |
5--- Rgh  Esc --+- View -
      |    |    |    |
6--- Up - Dwn --+-- Lft -
      |    |    |    |
               [1]
&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... pc1C re1v ud1l
     || | || | || +- Left
     || | || | |+--- Down
     || | || | +---- Up
     || | || +------ View
     || | |+-------- Esc
     || | +--------- Right
     || +----------- Clear
     |+------------- Circle
     +-------------- Pass
&lt;/pre&gt;</text>
    <sha1>fe46d407e6eb1e22394371c3de7eeaf27b823ac2</sha1>
  </revision>
  <revision>
    <id>26</id>
    <parentid>25</parentid>
    <timestamp>2023-08-17T09:29:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2769" xml:space="preserve">The WonderSwan SoC features a 4 by 3 keypad matrix.

== Scanning ==

Scanning is done via writing to and reading from port $B5.

&lt;pre&gt;
7  bit  0
---- ----
.iii oooo
 ||| ++++- Output rows (0-3)
 +++------ Input rows  (4-6)
&lt;/pre&gt;

The standard procedure is to read rows 4, 5 and 6 in order, shifting their values into one twelve-bit mask like so:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... 4444 5555 6666
&lt;/pre&gt;

Typical keypad scanning implementations introduce a delay between writing to and reading from the matrix, allowing the scanned values to stabilize. For example, one can use the DAA opcode for doing so.

== Startup override ==

On startup, the [[boot ROM]] checks whether or not certain output rows are forced high when all input rows are disabled. This triggers a startup override prior to the boot logo:

* Input row 0 - jump to 4000:0000,
* Input row 1 - jump to 4000:0010.

As this override is done before boot ROM lockout, it can be used to dump the boot ROM.

== Keypad arrangement ==

=== WonderSwan ===

==== Layout ====

&lt;pre&gt;
    Y1
 Y4    Y2
    Y3


    X1
 X4    X2                              A
    X3       Sound Start Power      B
                    (St)
&lt;/pre&gt;

Sound and Power buttons are not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Y4 - Y3 - Y2 - Y1 -
      |    |    |    |
5--- X4 - X3 - X2 - X1 -
      |    |    |    |
6---  B -  A - St ---+--
      |    |    |    |

&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... yyyy xxxx bas.
     |||| |||| ||+- Start
     |||| |||| |+-- A
     |||| |||| +--- B
     |||| ++++----- X4, X3, X2, X1
     ++++---------- Y4, Y3, Y2, Y1      
&lt;/pre&gt;

=== Pocket Challenge V2 ===

==== Layout ====

&lt;pre&gt;
  Power


     Esc
                                 View
   Up                                  Clear
                                       (Clr)
 Lft Rgh                           Circle
                                    (Crc)
   Dwn                           Pass
                                (Pas)
&lt;/pre&gt;

The Power switch is not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Pas  Crc --+-- Clr -
      |    |    |    |
5--- Rgh  Esc --+- View -
      |    |    |    |
6--- Up - Dwn --+-- Lft -
      |    |    |    |
               [1]
&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... pc1C re1v ud1l
     || | || | || +- Left
     || | || | |+--- Down
     || | || | +---- Up
     || | || +------ View
     || | |+-------- Esc
     || | +--------- Right
     || +----------- Clear
     |+------------- Circle
     +-------------- Pass
&lt;/pre&gt;</text>
    <sha1>3a184f11a68c50935f97eb559a5bf7242c178e94</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>2001 Mapper pinout</title>
  <ns>0</ns>
  <id>10</id>
  <revision>
    <id>28</id>
    <timestamp>2023-08-18T21:56:26Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>from my notes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1403" xml:space="preserve">2001: 48-pin 0.6mm pitch TQFP

                 D4 &lt;&gt; /01 o 25\ ?? Gnd                  
                D3 &lt;&gt; /02     26\ ?? Gnd                 
               D2 &lt;&gt; /03       27\ ?? Gnd                
              D1 &lt;&gt; /04         28\ ?? Gnd               
             D0 &lt;&gt; /05           29\ -&gt; Microwire SK     
           Gnd -- /06             30\ -- Vcc             
           A0 -&gt; /07          /|   31\ &lt;- Microwire DO   
          A1 -&gt; /08          / |/   32\ -&gt; Microwire DI  
        Vcc -- /09             /     33\ -&gt; Microwire CS 
        A2 -&gt; /10          /\      \  34\ -- nc          
       A3 -&gt; /11           \/      L\  35\ -&gt; ROM A22    
 CPU A19 -&gt; /12          /\      \  L\  36\ -&gt; ROM A17   
 CPU A18 -&gt; \13          \/     \/\     37/ -&gt; ROM A16   
  CPU A17 -&gt; \14       \       \ \/    38/ -&gt; ROM A20    
   CPU A16 -&gt; \15       \     \_\     39/ -&gt; ROM A21     
        Vcc -- \16          |\ \     40/ -- Gnd          
      /Reset ?&gt; \17         |_\     41/ -&gt; ROM A19       
         /MBC &lt;- \18      \        42/ -&gt; ROM A18        
          M/IO -&gt; \19    \/\      43/ -&gt; ROM /CS         
            /RD -&gt; \20  \ \/     44/ -- Vcc              
             /WR -&gt; \21  \      45/ -&gt; SRAM /CS          
             /SEL -&gt; \22       46/ &lt;&gt; D7                 
               CLK -&gt; \23     47/ &lt;&gt; D6                  
                Gnd -- \24 O 48/ &lt;&gt; D5</text>
    <sha1>466e4ce751f28bd07775962feeb86b2ade301a64</sha1>
  </revision>
  <revision>
    <id>29</id>
    <parentid>28</parentid>
    <timestamp>2023-08-18T21:57:01Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>orientation</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1514" xml:space="preserve">2001: 48-pin 0.6mm pitch TQFP

                 D4 &lt;&gt; /01 o 25\ ?? Gnd                  
                D3 &lt;&gt; /02     26\ ?? Gnd                 
               D2 &lt;&gt; /03       27\ ?? Gnd                
              D1 &lt;&gt; /04         28\ ?? Gnd               
             D0 &lt;&gt; /05           29\ -&gt; Microwire SK     
           Gnd -- /06             30\ -- Vcc             
           A0 -&gt; /07          /|   31\ &lt;- Microwire DO   
          A1 -&gt; /08          / |/   32\ -&gt; Microwire DI  
        Vcc -- /09             /     33\ -&gt; Microwire CS 
        A2 -&gt; /10          /\      \  34\ -- nc          
       A3 -&gt; /11           \/      L\  35\ -&gt; ROM A22    
 CPU A19 -&gt; /12          /\      \  L\  36\ -&gt; ROM A17   
 CPU A18 -&gt; \13          \/     \/\     37/ -&gt; ROM A16   
  CPU A17 -&gt; \14       \       \ \/    38/ -&gt; ROM A20    
   CPU A16 -&gt; \15       \     \_\     39/ -&gt; ROM A21     
        Vcc -- \16          |\ \     40/ -- Gnd          
      /Reset ?&gt; \17         |_\     41/ -&gt; ROM A19       
         /MBC &lt;- \18      \        42/ -&gt; ROM A18        
          M/IO -&gt; \19    \/\      43/ -&gt; ROM /CS         
            /RD -&gt; \20  \ \/     44/ -- Vcc              
             /WR -&gt; \21  \      45/ -&gt; SRAM /CS          
             /SEL -&gt; \22       46/ &lt;&gt; D7                 
               CLK -&gt; \23     47/ &lt;&gt; D6                  
                Gnd -- \24 O 48/ &lt;&gt; D5

Note the orientation of the text: "Bandai 2001" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>c4d7e94ab6b8f532e2962e6ab46ff05abc2aa272</sha1>
  </revision>
  <revision>
    <id>34</id>
    <parentid>29</parentid>
    <timestamp>2023-08-19T06:08:59Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>pitch</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1514" xml:space="preserve">2001: 48-pin 0.5mm pitch TQFP

                 D4 &lt;&gt; /01 o 25\ ?? Gnd                  
                D3 &lt;&gt; /02     26\ ?? Gnd                 
               D2 &lt;&gt; /03       27\ ?? Gnd                
              D1 &lt;&gt; /04         28\ ?? Gnd               
             D0 &lt;&gt; /05           29\ -&gt; Microwire SK     
           Gnd -- /06             30\ -- Vcc             
           A0 -&gt; /07          /|   31\ &lt;- Microwire DO   
          A1 -&gt; /08          / |/   32\ -&gt; Microwire DI  
        Vcc -- /09             /     33\ -&gt; Microwire CS 
        A2 -&gt; /10          /\      \  34\ -- nc          
       A3 -&gt; /11           \/      L\  35\ -&gt; ROM A22    
 CPU A19 -&gt; /12          /\      \  L\  36\ -&gt; ROM A17   
 CPU A18 -&gt; \13          \/     \/\     37/ -&gt; ROM A16   
  CPU A17 -&gt; \14       \       \ \/    38/ -&gt; ROM A20    
   CPU A16 -&gt; \15       \     \_\     39/ -&gt; ROM A21     
        Vcc -- \16          |\ \     40/ -- Gnd          
      /Reset ?&gt; \17         |_\     41/ -&gt; ROM A19       
         /MBC &lt;- \18      \        42/ -&gt; ROM A18        
          M/IO -&gt; \19    \/\      43/ -&gt; ROM /CS         
            /RD -&gt; \20  \ \/     44/ -- Vcc              
             /WR -&gt; \21  \      45/ -&gt; SRAM /CS          
             /SEL -&gt; \22       46/ &lt;&gt; D7                 
               CLK -&gt; \23     47/ &lt;&gt; D6                  
                Gnd -- \24 O 48/ &lt;&gt; D5

Note the orientation of the text: "Bandai 2001" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>a47ab56b418801050d72bf1fdfe8c396c284674e</sha1>
  </revision>
  <revision>
    <id>50</id>
    <parentid>34</parentid>
    <timestamp>2023-08-20T07:12:54Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>had the entire right half upside-down</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1533" xml:space="preserve">2001: 48-pin 0.5mm pitch TQFP

                 D4 &lt;&gt; /01 o 48\ &lt;&gt; D5                   
                D3 &lt;&gt; /02     47\ &lt;&gt; D6                  
               D2 &lt;&gt; /03       46\ &lt;&gt; D7                 
              D1 &lt;&gt; /04         45\ -&gt; SRAM /CS          
             D0 &lt;&gt; /05           44\ -- Vcc              
           Gnd -- /06             43\ -&gt; ROM /CS         
           A0 -&gt; /07               42\ -&gt; ROM A18        
          A1 -&gt; /08                 41\ -&gt; ROM A19       
        Vcc -- /09                   40\ -- Gnd          
        A2 -&gt; /10                     39\ -&gt; ROM A21     
       A3 -&gt; /11                       38\ -&gt; ROM A20    
 CPU A19 -&gt; /12         BANDAI          37\ -&gt; ROM A16   
 CPU A18 -&gt; \13          2001           36/ -&gt; ROM A17   
  CPU A17 -&gt; \14                       35/ -&gt; ROM A22    
   CPU A16 -&gt; \15                     34/ -- nc          
        Vcc -- \16                   33/ -&gt; Microwire CS 
      /Reset ?&gt; \17                 32/ -&gt; Microwire DI  
         /MBC &lt;- \18               31/ &lt;- Microwire DO   
          M/IO -&gt; \19             30/ -- Vcc             
            /RD -&gt; \20           29/ -&gt; Microwire SK     
             /WR -&gt; \21         28/ ?? Gnd               
             /SEL -&gt; \22       27/ ?? Gnd                
               CLK -&gt; \23     26/ ?? Gnd                 
                Gnd -- \24 O 25/ ?? Gnd                  

Note the orientation of the text: "Bandai 2001" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>4045cda402aecefd24c395a675eab6cd7ae894d7</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>2003 Mapper pinout</title>
  <ns>0</ns>
  <id>11</id>
  <revision>
    <id>30</id>
    <timestamp>2023-08-18T22:10:22Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>create from my notes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1484" xml:space="preserve">2003: 48-pin 0.6mm pitch TQFP

                Gnd -- /01 o 25\ &lt;&gt; D7                 
             GPO 3 &lt;? /02     26\ &lt;&gt; D6               
            GPO 2 &lt;? /03       27\ &lt;&gt; D5                
           GPO 1 &lt;? /04         28\ &lt;&gt; D4             
          GPO 0 &lt;? /05           29\ &lt;&gt; D3              
           Gnd -- /06             30\ -- Vcc            
      RTC SIO &lt;&gt; /07          /|   31\ &lt;&gt; D2            
     RTC SCK &lt;- /08          / |/   32\ &lt;&gt; D1         
     RTC CS &lt;- /09             /     33\ &lt;&gt; D0          
   ROM A25 &lt;- /10          /\      \  34\ &lt;- A0       
  ROM A24 &lt;- /11           \/      L\  35\ &lt;- A1        
 ROM A23 &lt;- /12          /\      \  L\  36\ &lt;- A2     
 ROM A22 &lt;- \13       /  \/     \/\     37/ &lt;- A3     
  ROM A17 &lt;- \14      \/       \ \/    38/ &lt;- CPU A19 
   ROM A16 &lt;- \15      \/     \_\     39/ &lt;- CPU A18    
        Gnd -- \16          |\ \     40/ &lt;- CPU A17   
     ROM A20 &lt;- \17         |_\     41/ &lt;- CPU A16      
      ROM A21 &lt;- \18      \        42/ &lt;- /Reset        
       ROM A19 &lt;- \19    \/\      43/ -&gt; /MBC         
        ROM A18 &lt;- \20  \ \/     44/ &lt;- M/IO            
        SRAM /CS &lt;- \21  \      45/ &lt;- /RD              
          ROM /CS &lt;- \22       46/ &lt;- /WR             
         ROM /BYTE &lt;- \23     47/ &lt;- /SEL             
          D15 (A-1) &lt;Z \24 O 48/ &lt;- CLK               

Note the orientation of the text: "Bandai 2003" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>b743a842d081cbc33ada662e56b0936ba673a07a</sha1>
  </revision>
  <revision>
    <id>35</id>
    <parentid>30</parentid>
    <timestamp>2023-08-19T06:09:06Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>pitch</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1484" xml:space="preserve">2003: 48-pin 0.5mm pitch TQFP

                Gnd -- /01 o 25\ &lt;&gt; D7                 
             GPO 3 &lt;? /02     26\ &lt;&gt; D6               
            GPO 2 &lt;? /03       27\ &lt;&gt; D5                
           GPO 1 &lt;? /04         28\ &lt;&gt; D4             
          GPO 0 &lt;? /05           29\ &lt;&gt; D3              
           Gnd -- /06             30\ -- Vcc            
      RTC SIO &lt;&gt; /07          /|   31\ &lt;&gt; D2            
     RTC SCK &lt;- /08          / |/   32\ &lt;&gt; D1         
     RTC CS &lt;- /09             /     33\ &lt;&gt; D0          
   ROM A25 &lt;- /10          /\      \  34\ &lt;- A0       
  ROM A24 &lt;- /11           \/      L\  35\ &lt;- A1        
 ROM A23 &lt;- /12          /\      \  L\  36\ &lt;- A2     
 ROM A22 &lt;- \13       /  \/     \/\     37/ &lt;- A3     
  ROM A17 &lt;- \14      \/       \ \/    38/ &lt;- CPU A19 
   ROM A16 &lt;- \15      \/     \_\     39/ &lt;- CPU A18    
        Gnd -- \16          |\ \     40/ &lt;- CPU A17   
     ROM A20 &lt;- \17         |_\     41/ &lt;- CPU A16      
      ROM A21 &lt;- \18      \        42/ &lt;- /Reset        
       ROM A19 &lt;- \19    \/\      43/ -&gt; /MBC         
        ROM A18 &lt;- \20  \ \/     44/ &lt;- M/IO            
        SRAM /CS &lt;- \21  \      45/ &lt;- /RD              
          ROM /CS &lt;- \22       46/ &lt;- /WR             
         ROM /BYTE &lt;- \23     47/ &lt;- /SEL             
          D15 (A-1) &lt;Z \24 O 48/ &lt;- CLK               

Note the orientation of the text: "Bandai 2003" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>a624b0f87dd8bda88995e50a79b467adc904a670</sha1>
  </revision>
  <revision>
    <id>49</id>
    <parentid>35</parentid>
    <timestamp>2023-08-20T07:11:14Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>had the entire right half upside-down</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1477" xml:space="preserve">2003: 48-pin 0.5mm pitch TQFP

                Gnd -- /01 o 48\ &lt;- CLK								 
             GPO 3 &lt;? /02     47\ &lt;- /SEL             
            GPO 2 &lt;? /03       46\ &lt;- /WR               
           GPO 1 &lt;? /04         45\ &lt;- /RD            
          GPO 0 &lt;? /05           44\ &lt;- M/IO            
           Gnd -- /06             43\ -&gt; /MBC           
      RTC SIO &lt;&gt; /07               42\ &lt;- /Reset        
     RTC SCK &lt;- /08                 41\ &lt;- CPU A16    
     RTC CS &lt;- /09                   40\ &lt;- CPU A17     
   ROM A25 &lt;- /10                     39\ &lt;- CPU A18  
  ROM A24 &lt;- /11        BANDAI         38\ &lt;- CPU A19   
 ROM A23 &lt;- /12          2003           37\ &lt;- A3     
 ROM A22 &lt;- \13                         36/ &lt;- A2     
  ROM A17 &lt;- \14                       35/ &lt;- A1      
   ROM A16 &lt;- \15                     34/ &lt;- A0         
        Gnd -- \16                   33/ &lt;&gt; D0        
     ROM A20 &lt;- \17                 32/ &lt;&gt; D1           
      ROM A21 &lt;- \18               31/ &lt;&gt; D2            
       ROM A19 &lt;- \19             30/ -- Vcc          
        ROM A18 &lt;- \20           29/ &lt;&gt; D3              
        SRAM /CS &lt;- \21         28/ &lt;&gt; D4               
          ROM /CS &lt;- \22       27/ &lt;&gt; D5              
         ROM /BYTE &lt;- \23     26/ &lt;&gt; D6               
          D15 (A-1) &lt;Z \24 O 25/ &lt;&gt; D7                

Note the orientation of the text: "Bandai 2003" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>cede91ff05d5bb0d5de1e5b60bfe1613be2ac9d9</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>31</id>
    <timestamp>2023-08-18T22:30:22Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>create from my notes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1682" xml:space="preserve">In addition to the normal [[Cartridge]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;
or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! $C8
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... ACWR ....&lt;/tt&gt;
| W8
| Abort (A), Command (C), Write (W), Read (R)
|-
! $C8
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... .... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

The specific meaning of the "Command" register depends on the model of EEPROM on the PCB. Only three Microwire EEPROMs have been seen used (equivalent to 93C46, 93C76, and 93C86)

On the 2001, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

If more than ACWR bit is set at the same time, the 2001 ignores it.

The CWR bits specify how many data bits are sent/received. C: No data bits. W: Send Data register after command register. R: Receive data register after sending command register.

If the A bit is set, the transaction immediately stops.

(Upload logic analyzer traces here)</text>
    <sha1>f633ef5d0eac455579d0a1c950a2b10d87cf9bb1</sha1>
  </revision>
  <revision>
    <id>32</id>
    <parentid>31</parentid>
    <timestamp>2023-08-18T22:32:18Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>if I say $C8 is byte-wide, only talk about 8 bits</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1662" xml:space="preserve">In addition to the normal [[Cartridge]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;
or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! $C8
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ACWR ....&lt;/tt&gt;
| W8
| Abort (A), Command (C), Write (W), Read (R)
|-
! $C8
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

The specific meaning of the "Command" register depends on the model of EEPROM on the PCB. Only three Microwire EEPROMs have been seen used (equivalent to 93C46, 93C76, and 93C86)

On the 2001, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

If more than ACWR bit is set at the same time, the 2001 ignores it.

The CWR bits specify how many data bits are sent/received. C: No data bits. W: Send Data register after command register. R: Receive data register after sending command register.

If the A bit is set, the transaction immediately stops.

(Upload logic analyzer traces here)</text>
    <sha1>7995fe2b17b0c07c5f1aa4d429c2df59860bd312</sha1>
  </revision>
  <revision>
    <id>48</id>
    <parentid>32</parentid>
    <timestamp>2023-08-19T21:49:57Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>merge cells</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1666" xml:space="preserve">In addition to the normal [[Cartridge]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;
or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ACWR ....&lt;/tt&gt;
| W8
| Abort (A), Command (C), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

The specific meaning of the "Command" register depends on the model of EEPROM on the PCB. Only three Microwire EEPROMs have been seen used (equivalent to 93C46, 93C76, and 93C86)

On the 2001, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

If more than ACWR bit is set at the same time, the 2001 ignores it.

The CWR bits specify how many data bits are sent/received. C: No data bits. W: Send Data register after command register. R: Receive data register after sending command register.

If the A bit is set, the transaction immediately stops.

(Upload logic analyzer traces here)</text>
    <sha1>84182607bf0a4e666fd85f9158905f274e36cc39</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>Bandai 2003</title>
  <ns>0</ns>
  <id>13</id>
  <revision>
    <id>33</id>
    <timestamp>2023-08-18T22:46:29Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>create from my notes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2222" xml:space="preserve">In addition to the normal [[Cartridge]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
! $CA
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D..B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| Data direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-flashing
! $CE
| Enable
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROMEX bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| ROM0 bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM1 bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM2 bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.</text>
    <sha1>e4866d7241b2c3b60bbfe40ee27583630f862288</sha1>
  </revision>
  <revision>
    <id>39</id>
    <parentid>33</parentid>
    <timestamp>2023-08-19T13:11:28Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>make it clearer that RTC Command and Status are the same port, unify capitalization</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2258" xml:space="preserve">In addition to the normal [[Cartridge]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D..B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.</text>
    <sha1>d5e8e9e637f1a84d7dfc4e85241bd039db829a2c</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>WonderGate</title>
  <ns>0</ns>
  <id>14</id>
  <revision>
    <id>36</id>
    <timestamp>2023-08-19T11:07:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== WonderGate ==  TODO  === Servers ===   {| class="wikitable" |+ WonderGate servers |- ! Hostname !! Software |- | [[WonderGate/bplXX.mopera.ne.jp|bplXX.mopera.ne.jp]] || MobileWonderGate (browser) |}"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="201" xml:space="preserve">== WonderGate ==

TODO

=== Servers ===


{| class="wikitable"
|+ WonderGate servers
|-
! Hostname !! Software
|-
| [[WonderGate/bplXX.mopera.ne.jp|bplXX.mopera.ne.jp]] || MobileWonderGate (browser)
|}</text>
    <sha1>91ae80b6f5add0dd4ac9501c54f137855bdea885</sha1>
  </revision>
  <revision>
    <id>46</id>
    <parentid>36</parentid>
    <timestamp>2023-08-19T18:09:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="362" xml:space="preserve">== WonderGate ==

TODO

=== Servers ===


{| class="wikitable"
|+ WonderGate servers
|-
! Software !! Hostname
|-
| rowspan="2" | MobileWonderGate (web browser)
| [[WonderGate/bplXX.mopera.ne.jp|bpl01.mopera.ne.jp]]
|-
| [[WonderGate/bplXX.mopera.ne.jp|bpl02.mopera.ne.jp]]
|-
| Terrors 2
| [[WonderGate/terrors2.wgg.channel.or.jp|terrors2.wgg.channel.or.jp]]
|}</text>
    <sha1>a543b6a77463a6450d62c5dc9fa1d7701f503fd7</sha1>
  </revision>
  <revision>
    <id>47</id>
    <parentid>46</parentid>
    <timestamp>2023-08-19T18:12:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="458" xml:space="preserve">== WonderGate ==

TODO

=== Servers ===


{| class="wikitable"
|+ WonderGate servers
|-
! Software !! Hostname
|-
| rowspan="2" | MobileWonderGate (web browser)
| [[WonderGate/bplXX.mopera.ne.jp|bpl01.mopera.ne.jp]]
|-
| [[WonderGate/bplXX.mopera.ne.jp|bpl02.mopera.ne.jp]]
|-
| Pocket Fighter
|
|-
| Rainbow Islands - Putty's Party
|
|-
| Star Hearts
|
|-
| Terrors 2
| [[WonderGate/terrors2.wgg.channel.or.jp|terrors2.wgg.channel.or.jp]]
|-
| Wizardry
|
|}</text>
    <sha1>c370c3e1d26dcd0809c48cbf03c6a8f0d60413fd</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>WonderGate/bplXX.mopera.ne.jp</title>
  <ns>0</ns>
  <id>15</id>
  <revision>
    <id>37</id>
    <timestamp>2023-08-19T11:17:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:  * &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt; * &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;  == Packet format ==  Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.  The client expects one block in response from the server.  === Header ===  {| class="wikitable" ! Offset ! Leng..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1467" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

The client expects one block in response from the server.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| 0x02 || 2 || Response type:
* 0x0000 - not a response
* 0x0010 - allow
* 0x0012 - deny
* 0x0021 - require ID/password
* 0x0023 - unknown (too large?)
|-
| 0x04 || 4 || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}</text>
    <sha1>ce2cb671662916111e93d683380c9e2a4023f79f</sha1>
  </revision>
  <revision>
    <id>38</id>
    <parentid>37</parentid>
    <timestamp>2023-08-19T12:05:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1595" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

The client expects one block in response from the server.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| 0x02 || 2 || Response type:
* 0x0000 - not a response
* 0x0010 - allow
* 0x0012 - deny
* 0x0021 - require ID/password
* 0x0023 - unknown (too large?)
|-
| 0x04 || 4 || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}</text>
    <sha1>b8bda6949d5f4a87b8e2e2c23d39f3325936e041</sha1>
  </revision>
  <revision>
    <id>40</id>
    <parentid>38</parentid>
    <timestamp>2023-08-19T13:57:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1578" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| 0x02 || 2 || Response type:
* 0x0000 - not a response
* 0x0010 - allow + 0 blocks
* 0x0012 - deny + 1 block
* 0x0021 - require ID/password + 1 block
* 0x0023 - unknown (too large?) + 0 blocks
|-
| 0x04 || 4 || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}</text>
    <sha1>2a1734f699502726c1cf339076a893fdd2ee450b</sha1>
  </revision>
  <revision>
    <id>41</id>
    <parentid>40</parentid>
    <timestamp>2023-08-19T15:04:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1640" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| 0x02 || 2 || Message type:
* 0x0000 - request: GET
* 0x0002 - request: POST
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4 || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}</text>
    <sha1>2eb5a3dbd6cbab0b8aa6a6f79b219d7649c6f91e</sha1>
  </revision>
  <revision>
    <id>42</id>
    <parentid>41</parentid>
    <timestamp>2023-08-19T15:15:09Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1942" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4 || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}</text>
    <sha1>21023a54ea4b1d4a16c6e4a28f43f1a62ea15e76</sha1>
  </revision>
  <revision>
    <id>43</id>
    <parentid>42</parentid>
    <timestamp>2023-08-19T15:44:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1950" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}</text>
    <sha1>2b46fdf698d2af8f51b63ca3eea0a7fe625b327c</sha1>
  </revision>
  <revision>
    <id>44</id>
    <parentid>43</parentid>
    <timestamp>2023-08-19T15:47:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2074" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

== TODO ==

* Why does the browser not send POST queries despite using an "allow" command? Is there a related Mopera flag?</text>
    <sha1>3e920b927a6fd521c15a2573f96507b48b193c3f</sha1>
  </revision>
</page>
<page arvcontinue="">
  <title>WonderWave</title>
  <ns>0</ns>
  <id>16</id>
  <revision>
    <id>45</id>
    <timestamp>2023-08-19T18:07:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderWave is an infrared adapter for the WonderSwan. It is implemented as a bi-directional 9600 bps converter between IrDA and the WonderSwan's UART &lt;ref&gt;[http://www.wonderwitch.com/neta/waza035/index.html 技その35「WonderWaveでファイル転送」]&lt;/ref&gt;.  == Notes == &lt;references /&gt;"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="295" xml:space="preserve">The WonderWave is an infrared adapter for the WonderSwan. It is implemented as a bi-directional 9600 bps converter between IrDA and the WonderSwan's UART &lt;ref&gt;[http://www.wonderwitch.com/neta/waza035/index.html 技その35「WonderWaveでファイル転送」]&lt;/ref&gt;.

== Notes ==
&lt;references /&gt;</text>
    <sha1>62706590fab7fbf72310df0dd5904cf24b8221fc</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>51</id>
    <parentid>48</parentid>
    <timestamp>2023-08-20T18:35:26Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>better target</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1663" xml:space="preserve">In addition to the normal [[Mapper]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;
or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ACWR ....&lt;/tt&gt;
| W8
| Abort (A), Command (C), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

The specific meaning of the "Command" register depends on the model of EEPROM on the PCB. Only three Microwire EEPROMs have been seen used (equivalent to 93C46, 93C76, and 93C86)

On the 2001, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

If more than ACWR bit is set at the same time, the 2001 ignores it.

The CWR bits specify how many data bits are sent/received. C: No data bits. W: Send Data register after command register. R: Receive data register after sending command register.

If the A bit is set, the transaction immediately stops.

(Upload logic analyzer traces here)</text>
    <sha1>249e0c1e131629cfd316417728016df85da170fa</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Bandai 2003</title>
  <ns>0</ns>
  <id>13</id>
  <revision>
    <id>52</id>
    <parentid>39</parentid>
    <timestamp>2023-08-20T18:42:06Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>better link target</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2255" xml:space="preserve">In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D..B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.</text>
    <sha1>ad71476be4c8352f9668b164f527fc78ad5f9dc2</sha1>
  </revision>
  <revision>
    <id>73</id>
    <parentid>52</parentid>
    <timestamp>2023-08-21T21:06:27Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4009" xml:space="preserve">In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.

== 2003 RTC interface ==
The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written. 

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

(Put logic analyzer traces here)

Values are as follows:

=== $00-$0F, $1C-$1F ===
Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

=== $10, $11 ===
Send command byte ($60 or $61 respectively) and stop.

=== $12 ===
Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

=== $13 ===
Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

=== $14 ===
Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the ''first'' byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

=== $15 ===
Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

=== $16 ===
Send command byte ($66), then send three bytes of payload, then stop.bit.

=== $17 ===
Send command byte ($67), then receive three bytes of payload, then stop.

=== $18, $1A ===
Send command byte ($68 or $6A), then send two bytes of payload, then stop.needed" bit.

=== $19, $1B ===
Send command byte ($69 or $6B), then receive two bytes of payload, then stop.</text>
    <sha1>fb1ba04fb3953f48783693db09e76e88284eff8b</sha1>
  </revision>
  <revision>
    <id>74</id>
    <parentid>73</parentid>
    <timestamp>2023-08-21T21:09:28Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>/* 2003 RTC interface */ floating SIO pin is pulled high</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4113" xml:space="preserve">In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.

== 2003 RTC interface ==
The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

(Put logic analyzer traces here)

Values are as follows:

=== $00-$0F, $1C-$1F ===
Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

=== $10, $11 ===
Send command byte ($60 or $61 respectively) and stop.

=== $12 ===
Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

=== $13 ===
Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

=== $14 ===
Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the ''first'' byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

=== $15 ===
Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

=== $16 ===
Send command byte ($66), then send three bytes of payload, then stop.bit.

=== $17 ===
Send command byte ($67), then receive three bytes of payload, then stop.

=== $18, $1A ===
Send command byte ($68 or $6A), then send two bytes of payload, then stop.needed" bit.

=== $19, $1B ===
Send command byte ($69 or $6B), then receive two bytes of payload, then stop.</text>
    <sha1>281ed534df91aac3977ad77a4b71c3ae4f232d79</sha1>
  </revision>
  <revision>
    <id>75</id>
    <parentid>74</parentid>
    <timestamp>2023-08-21T21:09:58Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>/* 2003 RTC interface */ edito</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4097" xml:space="preserve">In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.

== 2003 RTC interface ==
The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

(Put logic analyzer traces here)

Values are as follows:

=== $00-$0F, $1C-$1F ===
Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

=== $10, $11 ===
Send command byte ($60 or $61 respectively) and stop.

=== $12 ===
Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

=== $13 ===
Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

=== $14 ===
Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the ''first'' byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

=== $15 ===
Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

=== $16 ===
Send command byte ($66), then send three bytes of payload, then stop.

=== $17 ===
Send command byte ($67), then receive three bytes of payload, then stop.

=== $18, $1A ===
Send command byte ($68 or $6A), then send two bytes of payload, then stop.

=== $19, $1B ===
Send command byte ($69 or $6B), then receive two bytes of payload, then stop.</text>
    <sha1>0556efe6c59febe6d9a6a500ad049dde51d24379</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Mapper</title>
  <ns>0</ns>
  <id>17</id>
  <revision>
    <id>53</id>
    <timestamp>2023-08-20T18:54:40Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>create from my notes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1154" xml:space="preserve">There are three documented memory-mapping chips used on the WonderSwan and Pocket Challenge V2:

* [[Bandai 2001]]
* [[Bandai 2003]]
* [[KARNAK]]

All three provide this same common subset for memory banking:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | Extended bankswitching
! $C0
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00BB bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000.
|-
! $C1
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb&lt;/tt&gt;
| RW8
| Selects a 64KiB bank accessed via segment 0x1000.
|-
! $C2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb&lt;/tt&gt;
| RW8
| Selects a 64KiB bank accessed via segment 0x2000.
|-
! $C3
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb&lt;/tt&gt;
| RW8
| Selects a 64KiB bank accessed via segment 0x3000.
|}

Note that the number of bits in the Linear bank register depends on the mapper.

The black-and-white WonderSwan expects that the register at $C3 will power up holding $FF.</text>
    <sha1>fc3aa2bbf24508dc738f7674eebf184579312756</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>2003 Mapper pinout</title>
  <ns>0</ns>
  <id>11</id>
  <revision>
    <id>54</id>
    <parentid>49</parentid>
    <timestamp>2023-08-20T19:07:42Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>link to corresponding mapper description</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1488" xml:space="preserve">[[Bandai 2003]]: 48-pin 0.5mm pitch TQFP

                Gnd -- /01 o 48\ &lt;- CLK								 
             GPO 3 &lt;? /02     47\ &lt;- /SEL             
            GPO 2 &lt;? /03       46\ &lt;- /WR               
           GPO 1 &lt;? /04         45\ &lt;- /RD            
          GPO 0 &lt;? /05           44\ &lt;- M/IO            
           Gnd -- /06             43\ -&gt; /MBC           
      RTC SIO &lt;&gt; /07               42\ &lt;- /Reset        
     RTC SCK &lt;- /08                 41\ &lt;- CPU A16    
     RTC CS &lt;- /09                   40\ &lt;- CPU A17     
   ROM A25 &lt;- /10                     39\ &lt;- CPU A18  
  ROM A24 &lt;- /11        BANDAI         38\ &lt;- CPU A19   
 ROM A23 &lt;- /12          2003           37\ &lt;- A3     
 ROM A22 &lt;- \13                         36/ &lt;- A2     
  ROM A17 &lt;- \14                       35/ &lt;- A1      
   ROM A16 &lt;- \15                     34/ &lt;- A0         
        Gnd -- \16                   33/ &lt;&gt; D0        
     ROM A20 &lt;- \17                 32/ &lt;&gt; D1           
      ROM A21 &lt;- \18               31/ &lt;&gt; D2            
       ROM A19 &lt;- \19             30/ -- Vcc          
        ROM A18 &lt;- \20           29/ &lt;&gt; D3              
        SRAM /CS &lt;- \21         28/ &lt;&gt; D4               
          ROM /CS &lt;- \22       27/ &lt;&gt; D5              
         ROM /BYTE &lt;- \23     26/ &lt;&gt; D6               
          D15 (A-1) &lt;Z \24 O 25/ &lt;&gt; D7                

Note the orientation of the text: "Bandai 2003" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>15187cb56f2f8af756135b1e7486bee4fae550a8</sha1>
  </revision>
  <revision>
    <id>64</id>
    <parentid>54</parentid>
    <timestamp>2023-08-21T06:42:50Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Reformats pinout to match other QFPs on NESdev. Adds orientation and legend.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2131" xml:space="preserve">                         _____
                        /     \
                Gnd -- / 1  48 \ &lt;- CLK
             GPO 3 &lt;? / 2  O 47 \ &lt;- /SEL
            GPO 2 &lt;? / 3      46 \ &lt;- /WR
           GPO 1 &lt;? / 4        45 \ &lt;- /RD
          GPO 0 &lt;? / 5          44 \ &lt;- M/IO
           Gnd -- / 6            43 \ -&gt; /MBC
      RTC SIO &lt;&gt; / 7              42 \ &lt;- /Reset
     RTC SCK &lt;- / 8                41 \ &lt;- CPU A16
     RTC CS &lt;- / 9                  40 \ &lt;- CPU A17
   ROM A25 &lt;- / 10                   39 \ &lt;- CPU A18
  ROM A24 &lt;- / 11                     38 \ &lt;- CPU A19      Orientation:
 ROM A23 &lt;- / 12                       37 \ &lt;- A3          ----------------
           /          BANDAI 2003          \                  36      25
           \        Package TQFP-48        /                   |      |
 ROM A22 &lt;- \ 13      0.5mm pitch      36 / &lt;- A2             .--------.
  ROM A17 &lt;- \ 14                     35 / &lt;- A1           37-|BANDAI O|-24
   ROM A16 &lt;- \ 15                   34 / &lt;- A0               |2003    |
        Gnd -- \ 16                 33 / &lt;&gt; D0             48-|O  039XR|-13
     ROM A20 &lt;- \ 17               32 / &lt;&gt; D1                 \--------'
      ROM A21 &lt;- \ 18             31 / &lt;&gt; D2                   |      |
       ROM A19 &lt;- \ 19           30 / -- Vcc                  01      12
        ROM A18 &lt;- \ 20         29 / &lt;&gt; D3
        SRAM /CS &lt;- \ 21       28 / &lt;&gt; D4            Legend:
          ROM /CS &lt;- \ 22     27 / &lt;&gt; D5             -------------------------------------------
         ROM /BYTE &lt;- \ 23 O 26 / &lt;&gt; D6              --[2003]-- Power
          D15 (A-1) &lt;Z \ 24 25 / &lt;&gt; D7               -&gt;[2003]&lt;- 2003 input
                        \     /                      &lt;-[2003]-&gt; 2003 output
                         \   /                       &lt;&gt;[2003]&lt;&gt; Bidirectional
                          \ /                        &lt;Z[2003]Z&gt; Output or high impedance
                           V                         &lt;?[2003]?&gt; Output, unknown if bidirectional
 
 (Note that the corner indicator for pin 1 is subtle
  compared to the other corners as well as other QFPs.)</text>
    <sha1>b76e09391767a3b116dbc915f1510c9fb1247461</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>2001 Mapper pinout</title>
  <ns>0</ns>
  <id>10</id>
  <revision>
    <id>55</id>
    <parentid>50</parentid>
    <timestamp>2023-08-20T19:08:03Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>link to corresponding mapper description</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1544" xml:space="preserve">[[Bandai 2001]]: 48-pin 0.5mm pitch TQFP

                 D4 &lt;&gt; /01 o 48\ &lt;&gt; D5                   
                D3 &lt;&gt; /02     47\ &lt;&gt; D6                  
               D2 &lt;&gt; /03       46\ &lt;&gt; D7                 
              D1 &lt;&gt; /04         45\ -&gt; SRAM /CS          
             D0 &lt;&gt; /05           44\ -- Vcc              
           Gnd -- /06             43\ -&gt; ROM /CS         
           A0 -&gt; /07               42\ -&gt; ROM A18        
          A1 -&gt; /08                 41\ -&gt; ROM A19       
        Vcc -- /09                   40\ -- Gnd          
        A2 -&gt; /10                     39\ -&gt; ROM A21     
       A3 -&gt; /11                       38\ -&gt; ROM A20    
 CPU A19 -&gt; /12         BANDAI          37\ -&gt; ROM A16   
 CPU A18 -&gt; \13          2001           36/ -&gt; ROM A17   
  CPU A17 -&gt; \14                       35/ -&gt; ROM A22    
   CPU A16 -&gt; \15                     34/ -- nc          
        Vcc -- \16                   33/ -&gt; Microwire CS 
      /Reset ?&gt; \17                 32/ -&gt; Microwire DI  
         /MBC &lt;- \18               31/ &lt;- Microwire DO   
          M/IO -&gt; \19             30/ -- Vcc             
            /RD -&gt; \20           29/ -&gt; Microwire SK     
             /WR -&gt; \21         28/ ?? Gnd               
             /SEL -&gt; \22       27/ ?? Gnd                
               CLK -&gt; \23     26/ ?? Gnd                 
                Gnd -- \24 O 25/ ?? Gnd                  

Note the orientation of the text: "Bandai 2001" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>bbb1ac87b80b864d0876155826b5af767ef519f1</sha1>
  </revision>
  <revision>
    <id>63</id>
    <parentid>55</parentid>
    <timestamp>2023-08-21T06:42:07Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Reformats pinout to match other QFPs on NESdev. Adds orientation and legend.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2173" xml:space="preserve">                         _____
                        /     \
                 D4 &lt;&gt; / 1  48 \ &lt;&gt; D5
                D3 &lt;&gt; / 2  O 47 \ &lt;&gt; D6
               D2 &lt;&gt; / 3      46 \ &lt;&gt; D7
              D1 &lt;&gt; / 4        45 \ -&gt; SRAM /CS
             D0 &lt;&gt; / 5          44 \ -- Vcc
           Gnd -- / 6            43 \ -&gt; ROM /CS
           A0 -&gt; / 7              42 \ -&gt; ROM A18
          A1 -&gt; / 8                41 \ -&gt; ROM A19
        Vcc -- / 9                  40 \ -- Gnd
        A2 -&gt; / 10                   39 \ -&gt; ROM A21
       A3 -&gt; / 11                     38 \ -&gt; ROM A20        Orientation:
 CPU A19 -&gt; / 12                       37 \ -&gt; ROM A16       ----------------
           /          BANDAI 2001          \                    36      25
           \        Package TQFP-48        /                     |      |
 CPU A18 -&gt; \ 13      0.5mm pitch      36 / -&gt; ROM A17          .--------.
  CPU A17 -&gt; \ 14                     35 / -&gt; ROM A22        37-|BANDAI O|-24
   CPU A16 -&gt; \ 15                   34 / -- n/c                |2001    |
        Vcc -- \ 16                 33 / -&gt; Microwire CS     48-|O  914XC|-13
      /Reset ?&gt; \ 17               32 / -&gt; Microwire DI         \--------'
         /MBC &lt;- \ 18             31 / &lt;- Microwire DO           |      |
          M/IO -&gt; \ 19           30 / -- Vcc                    01      12
            /RD -&gt; \ 20         29 / -&gt; Microwire SK
             /WR -&gt; \ 21       28 / ?? Gnd              Legend:
             /SEL -&gt; \ 22     27 / ?? Gnd               ------------------------------------------
               CLK -&gt; \ 23 O 26 / ?? Gnd                --[2001]-- Power, n/a
                Gnd -- \ 24 25 / ?? Gnd                 -&gt;[2001]&lt;- 2001 input
                        \     /                         &lt;-[2001]-&gt; 2001 output
                         \   /                          &lt;&gt;[2001]&lt;&gt; Bidirectional
                          \ /                           ??[2001]?? Unknown
                           V                            ?&gt;[2001]&lt;? Input, unknown if bidirectional
 
 (Note that the corner indicator for pin 1 is subtle
  compared to the other corners as well as other QFPs.)</text>
    <sha1>9f96bdf3f6a2e19c962186fb472fe59f1cafe012</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>56</id>
    <parentid>24</parentid>
    <timestamp>2023-08-20T19:09:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add cartridge I/o link</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17413" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | Timers
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! Interrupts
! $B0
| Interrupt Vector
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv v...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! UART
! $B1
| Serial Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! Interrupts
! $B2
| Interrupt Enable
|
| RW8
|
|-
! UART
! $B3
| Serial Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .rot&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Receive ready (r), Overrun (o), Transfer ready (t)
|-
! Interrupts
! $B4
| Interrupt Status
|
| RW8
|
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | Interrupts
! $B6
| Interrupt Acknowledge
|
| RW8
|
|-
! $B7
| Interrupt NMI Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>61956370f69113eb0fd3db95aba7f0cd511801b1</sha1>
  </revision>
  <revision>
    <id>58</id>
    <parentid>56</parentid>
    <timestamp>2023-08-20T19:10:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>consistency: add more URLs</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17441" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| Interrupt Vector
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv v...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| Serial Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| Interrupt Enable
|
| RW8
|
|-
! [[UART]]
! $B3
| Serial Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .rot&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Receive ready (r), Overrun (o), Transfer ready (t)
|-
! [[Interrupts]]
! $B4
| Interrupt Status
|
| RW8
|
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| Interrupt Acknowledge
|
| RW8
|
|-
! $B7
| Interrupt NMI Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>6e9c0e1dfb6846f50de0aca0791c062def9c2258</sha1>
  </revision>
  <revision>
    <id>77</id>
    <parentid>58</parentid>
    <timestamp>2023-08-22T05:32:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>update interrupt information</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17700" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| Serial Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! [[UART]]
! $B3
| Serial Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .rot&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Receive ready (r), Overrun (o), Transfer ready (t)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>a6de44a164976e1f28cf9fd29f4ee0423b156d1a</sha1>
  </revision>
  <revision>
    <id>79</id>
    <parentid>77</parentid>
    <timestamp>2023-08-22T05:39:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>update UART information</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17745" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| Timer Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| Horizontal Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| Vertical Blank Timer Reload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| Horizontal Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| Vertical Blank Timer Counter
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| [[UART#serial Data|Serial Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! [[UART]]
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .tor&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>8f5f79a511fbe5f1e76eb3071a6408d6efea71b0</sha1>
  </revision>
  <revision>
    <id>83</id>
    <parentid>79</parentid>
    <timestamp>2023-08-22T05:51:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>update timer information</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17868" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.e&lt;/tt&gt;
| RW8
| Volume segment status (v), Enable (e)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| [[UART#serial Data|Serial Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! [[UART]]
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .tor&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>c985e7981a44c5a778a3de456184708393824138</sha1>
  </revision>
  <revision>
    <id>98</id>
    <parentid>83</parentid>
    <timestamp>2023-08-22T09:13:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17867" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| Sound Channel 1 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| Sound Channel 2 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| Sound Channel 3 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| Sound Channel 4 Frequency
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| Sound Channel 1 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| Sound Channel 2 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| Sound Channel 2 Voice Sample
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| Sound Channel 3 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| Sound Channel 4 Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| Sound Channel 3 Sweep Amount
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| Sound Channel 3 Sweep Ticks
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| Sound Channel 4 Noise Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| Sound Wavetable Address
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| Sound Channel Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| Sound Output Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| Sound Channel 4 LFSR
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| Sound Channel 2 Voice Volume
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Sequencer Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Sequencer Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Sequencer Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| [[UART#serial Data|Serial Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! [[UART]]
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .tor&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>4f72cc5aab81576b03ada5fe9a6861e9cdcdef08</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>57</id>
    <parentid>21</parentid>
    <timestamp>2023-08-20T19:10:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>consistency: rename Serial port to UART</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1092" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Components ===

* [[Display]]
* [[Sound]]
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM]]
* [[DMA]] (WonderSwan Color only)
* [[Mapper]]
** [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>c2b42cba83f04e05b128d9d687f172ba2145f79c</sha1>
  </revision>
  <revision>
    <id>59</id>
    <parentid>57</parentid>
    <timestamp>2023-08-20T22:01:15Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>/* Pinouts */ a few other pinouts</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1151" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[Cartridge]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Components ===

* [[Display]]
* [[Sound]]
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM]]
* [[DMA]] (WonderSwan Color only)
* [[Mapper]]
** [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>9da09ba089aedbe1276ae0810927a05d3d5ca58b</sha1>
  </revision>
  <revision>
    <id>88</id>
    <parentid>59</parentid>
    <timestamp>2023-08-22T06:45:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>split console and cartridge components</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1173" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM]]
* [[DMA]] (WonderSwan Color only)

=== Cartridge components ===

* [[Mapper]]
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>4454948a05d0f271f33862b49b67d5dadf0eb6fc</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>KARNAK</title>
  <ns>0</ns>
  <id>18</id>
  <revision>
    <id>60</id>
    <timestamp>2023-08-20T22:27:05Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>create from various sources (include ares's source, scuttlebutt via the discord)</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2518" xml:space="preserve">KARNAK was only used in Pocket Challenge V2 edutainment games. 

It is not yet well-documented. It is thought to be a revision of [[Bandai 2003]] that removes the RTC interface, and adds a timer IRQ and a hardware IMA ADPCM decoder.

This page should not be taken as authoritative: it has been pieced together from multiple other pieces of research. It is unclear if the GPO and Self-Flash registers exist; from PCB photos the Self-Flash register is unused if it does exist.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|- 
! Timer
! $D6
| Programmable Interval Timer
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eppp pppp&lt;/tt&gt;
| RW8
| Enable (e); Period (p). Units are the 384kHz clock to the cartridge.
|-
! rowspan=2|ADPCM
! rowspan=2|$D8
| packed data
| ?
| W8
| Write two-sample packed ADPCM byte
|-
| unpacked data
| ?
| R16
| Read two one-byte unpacked PCM bytes
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.</text>
    <sha1>f17d5a5680696934a02a0480e2abc23a80686500</sha1>
  </revision>
  <revision>
    <id>61</id>
    <parentid>60</parentid>
    <timestamp>2023-08-20T22:54:20Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>remove copypasta</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2349" xml:space="preserve">KARNAK was only used in Pocket Challenge V2 edutainment games. 

It is not yet well-documented. It is thought to be a revision of [[Bandai 2003]] that removes the RTC interface, and adds a timer IRQ and a hardware IMA ADPCM decoder.

This page should not be taken as authoritative: it has been pieced together from multiple other pieces of research. It is unclear if the GPO and Self-Flash registers exist; from PCB photos the Self-Flash register is unused if it does exist.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|- 
! Timer
! $D6
| Programmable Interval Timer
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eppp pppp&lt;/tt&gt;
| RW8
| Enable (e); Period (p). Units are the 384kHz clock to the cartridge.
|-
! rowspan=2|ADPCM
! rowspan=2|$D8
| packed data
| ?
| W8
| Write two-sample packed ADPCM byte
|-
| unpacked data
| ?
| R16
| Read two one-byte unpacked PCM bytes
|}</text>
    <sha1>37a2a7ea75d2f3e5c853a9c861b5dd7149a4b4b6</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>KARNAK pinout</title>
  <ns>0</ns>
  <id>19</id>
  <revision>
    <id>62</id>
    <timestamp>2023-08-20T23:03:48Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>Half of the pinout is trivially visible by inspection of the PCBs - very close to a 180degree rotation of the 2003.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1109" xml:space="preserve">[[KARNAK]]: 48-pin 0.5mm pitch TQFP

                 D7 &lt;&gt; /01 o 48\ 
                D6 &lt;&gt; /02     47\
               D5 &lt;&gt; /03       46\
              D4 &lt;&gt; /04         45\
             D3 &lt;&gt; /05           44\
           Gnd -- /06             43\
           D2 &lt;&gt; /07               42\
          D1 &lt;&gt; /08                 41\ -- Gnd
         D0 &lt;&gt; /09                   40\
        A0 -&gt; /10                     39\
       A1 -&gt; /11                       38\
      A2 -&gt; /12         KARNAK          37\
      A3 -&gt; \13                         36/
  CPU A19 &lt;- \14                       35/
   CPU A18 &lt;- \15                     34/
    CPU A17 -&gt; \16                   33/
     CPU A16 -&gt; \17                 32/ -- Gnd
       /RESET -&gt; \18               31/ -- Gnd
          /MBC &lt;- \19             30/ -- Gnd
           M/IO -&gt; \20           29/ -- Vcc
             /RD -&gt; \21         28/
              /WR -&gt; \22       27/
              /SEL -&gt; \23     26/
               /IRQ &lt;- \24 O 25/ &lt;- CLK

Note the orientation of the text: "Karnak" when viewed upright specifies pin 1 is bottom face, leftmost.</text>
    <sha1>a2a6bfeb46e4643eccfdcdebf350f7d45747d151</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>WonderGate/bplXX.mopera.ne.jp</title>
  <ns>0</ns>
  <id>15</id>
  <revision>
    <id>65</id>
    <parentid>44</parentid>
    <timestamp>2023-08-21T18:00:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2279" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>3714bc040fc76cc90a3c50dfe427391ffb6b937f</sha1>
  </revision>
  <revision>
    <id>66</id>
    <parentid>65</parentid>
    <timestamp>2023-08-21T19:51:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>initial multipart block documentation</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2930" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

=== Multipart blocks ===

Sending a block with a block size of `0xFFFF` and a block type of `0x00` in a response will trigger a multipart block mode, which sends data in portions between a header and footer.

{| class="wikitable"
|+ Header
! Offset
! Length
! Description
|-
| 0x00 || 1 || Number of parts?
|-
| 0x01&lt;br/&gt;
0x04
| ?
| Unknown
|}

{| class="wikitable"
|+ Part
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|-
| 0x02
| 2
| Length of data, in bytes
|-
| 0x04&lt;br/&gt;
0x05
| ?
| Unknown
|-
| 0x06...
| &lt;length&gt;
| Data
|}

{| class="wikitable"
|+ Footer
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>d2f38296538f01a3546331346fea4ac2b5475e56</sha1>
  </revision>
  <revision>
    <id>67</id>
    <parentid>66</parentid>
    <timestamp>2023-08-21T19:51:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2952" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08 || 4 || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4 || Unknown (216.0.192.1?)
|-
| 0x14 || 4 || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

=== Multipart blocks ===

Sending a block with a block size of &lt;code&gt;0xFFFF&lt;/code&gt; and a block type of &lt;code&gt;0x00&lt;/code&gt; in a response will trigger a multipart block mode, which sends data in portions between a header and footer.

{| class="wikitable"
|+ Header
! Offset
! Length
! Description
|-
| 0x00 || 1 || Number of parts?
|-
| 0x01&lt;br/&gt;
0x04
| ?
| Unknown
|}

{| class="wikitable"
|+ Part
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|-
| 0x02
| 2
| Length of data, in bytes
|-
| 0x04&lt;br/&gt;
0x05
| ?
| Unknown
|-
| 0x06...
| &lt;length&gt;
| Data
|}

{| class="wikitable"
|+ Footer
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>605e83f6cee5167732e81b68dfb11871ed1c8f27</sha1>
  </revision>
  <revision>
    <id>68</id>
    <parentid>67</parentid>
    <timestamp>2023-08-21T19:53:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2963" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08&lt;br/&gt;
0x0F|| ? || Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4? || Unknown (216.0.192.1?)
|-
| 0x14 || 4? || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

=== Multipart blocks ===

Sending a block with a block size of &lt;code&gt;0xFFFF&lt;/code&gt; and a block type of &lt;code&gt;0x00&lt;/code&gt; in a response will trigger a multipart block mode, which sends data in portions between a header and footer.

{| class="wikitable"
|+ Header
! Offset
! Length
! Description
|-
| 0x00 || 1 || Number of parts?
|-
| 0x01&lt;br/&gt;
0x04
| ?
| Unknown
|}

{| class="wikitable"
|+ Part
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|-
| 0x02
| 2
| Length of data, in bytes
|-
| 0x04&lt;br/&gt;
0x05
| ?
| Unknown
|-
| 0x06...
| &lt;length&gt;
| Data
|}

{| class="wikitable"
|+ Footer
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>8fb089c205f3707ffd44c4bdfa3b6eeeea7a1b49</sha1>
  </revision>
  <revision>
    <id>69</id>
    <parentid>68</parentid>
    <timestamp>2023-08-21T19:53:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2962" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08&lt;br/&gt;
0x0F
| ?
| Unknown
|-
| 0x0C || 4 || Unknown
|-
| 0x10 || 4? || Unknown (216.0.192.1?)
|-
| 0x14 || 4? || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

=== Multipart blocks ===

Sending a block with a block size of &lt;code&gt;0xFFFF&lt;/code&gt; and a block type of &lt;code&gt;0x00&lt;/code&gt; in a response will trigger a multipart block mode, which sends data in portions between a header and footer.

{| class="wikitable"
|+ Header
! Offset
! Length
! Description
|-
| 0x00 || 1 || Number of parts?
|-
| 0x01&lt;br/&gt;
0x04
| ?
| Unknown
|}

{| class="wikitable"
|+ Part
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|-
| 0x02
| 2
| Length of data, in bytes
|-
| 0x04&lt;br/&gt;
0x05
| ?
| Unknown
|-
| 0x06...
| &lt;length&gt;
| Data
|}

{| class="wikitable"
|+ Footer
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>be6c3df9a1c4bd7b30d2306be8246328fda91e63</sha1>
  </revision>
  <revision>
    <id>70</id>
    <parentid>69</parentid>
    <timestamp>2023-08-21T19:53:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2936" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08&lt;br/&gt;
0x0F
| ?
| Unknown
|-
| 0x10 || 4? || Unknown (216.0.192.1?)
|-
| 0x14 || 4? || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

=== Multipart blocks ===

Sending a block with a block size of &lt;code&gt;0xFFFF&lt;/code&gt; and a block type of &lt;code&gt;0x00&lt;/code&gt; in a response will trigger a multipart block mode, which sends data in portions between a header and footer.

{| class="wikitable"
|+ Header
! Offset
! Length
! Description
|-
| 0x00 || 1 || Number of parts?
|-
| 0x01&lt;br/&gt;
0x04
| ?
| Unknown
|}

{| class="wikitable"
|+ Part
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|-
| 0x02
| 2
| Length of data, in bytes
|-
| 0x04&lt;br/&gt;
0x05
| ?
| Unknown
|-
| 0x06...
| &lt;length&gt;
| Data
|}

{| class="wikitable"
|+ Footer
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>54b72402dad3213bdc0886dc7b7f898d92f733c3</sha1>
  </revision>
  <revision>
    <id>96</id>
    <parentid>70</parentid>
    <timestamp>2023-08-22T08:29:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3110" xml:space="preserve">For the MobileWonderGate software, NTT DoCoMo operated network servers for handling URL requests:

* &lt;code&gt;bpl01.mopera.ne.jp&lt;/code&gt;
* &lt;code&gt;bpl02.mopera.ne.jp&lt;/code&gt;

These servers listened on TCP port 5555 for request packets in the following format, and issued a response in the same format.

Pages accessed via the mopera network server reported themselves as &lt;code&gt;Mozilla/3.0 (compatible; InfoBridge-mopera 1.1.1; Linux)&lt;/code&gt;, as opposed to the browser's own &lt;code&gt;SWAN/1.0&lt;/code&gt;.

== Packet format ==

Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers.

=== Header ===

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 1 || Unknown, always 0x01
|-
| 0x01 || 1 || Header size in bytes, always 0x18
|-
| rowspan="2" | 0x02
| rowspan="2" | 2
| Request type/Browser configuration:
&lt;pre&gt;
ee?i ?s?w ???? ??p?
|| |  | |        +- POST request
|| |  | +---------- Width: 0 = 1-screen, 1 = 2-screen
|| |  +------------ Image size: 0 = 50%, 1 = 100%
|| +--------------- Images: 0 = enabled, 1 = disabled
++----------------- Encoding: 0 = auto, 1 = S-JIS, 2 = EUC
&lt;/pre&gt;
|-
| Response type:
* 0x0010 - response: allow + 0 blocks
* 0x0012 - response: deny/redirect? + 1 block
* 0x0021 - response: require ID/password + 1 block
* 0x0023 - response: unknown (too large?) + 0 blocks
|-
| 0x04 || 4? (&gt;= 2) || Total packet size in bytes, including all headers and blocks
|-
| 0x08&lt;br/&gt;
0x0F
| ?
| Unknown
|-
| 0x10 || 4? || Unknown (216.0.192.1?)
|-
| 0x14 || 4? || Unknown (255.255.0.0?)
|}

=== Block header ===

Blocks typically consist of zero-terminated strings - a final zero appears to be omitted.

{| class="wikitable"
! Offset
! Length
! Description
|-
| 0x00 || 2 || Block size in bytes, including header
|-
| 0x02 || 1 || Block type:
* 0x01 - 0x00? byte, followed by requested URL string
* 0x03 - 0x00? byte, followed by previous URL string (referrer?)
* 0x11 - ID string, followed by PASS string
* 0x22 - 0x00? byte, followed by query field name string, followed by query field value string
|}

=== Multipart blocks ===

Sending a block with a block size of &lt;code&gt;0xFFFF&lt;/code&gt; and a block type of &lt;code&gt;0x00&lt;/code&gt; in a response will trigger a multipart block mode, which sends data in portions between a header and footer.

While the &lt;code&gt;0xFFFF/0x00&lt;/code&gt; preamble has to be included in the total length from the global header, the remainder of the multipart block section does not have to be.

{| class="wikitable"
|+ Header
! Offset
! Length
! Description
|-
| 0x00 || 1 || Number of parts?
|-
| 0x01&lt;br/&gt;
0x04
| ?
| Unknown
|}

{| class="wikitable"
|+ Part
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|-
| 0x02
| 2
| Length of data, in bytes
|-
| 0x04&lt;br/&gt;
0x05
| ?
| Unknown
|-
| 0x06...
| &lt;length&gt;
| Data
|}

{| class="wikitable"
|+ Footer
! Offset
! Length
! Description
|-
| 0x00&lt;br/&gt;
0x01
| ?
| Unknown
|}

== TODO ==

* How does one send an HTTP response through the bridge? This has to be possible, as the bridge had its own distinct user agent.</text>
    <sha1>938f10788d5e5b95e61e8785c71782af96a6ed15</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>GIZA pinout</title>
  <ns>0</ns>
  <id>20</id>
  <revision>
    <id>71</id>
    <timestamp>2023-08-21T20:01:38Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>Created page with "GIZA: 8-pin 0.05"-pitch SOP     Vbat -&gt; | 1  8 | &lt;- Vconsole    Vups &lt;- | 2  7 | ?? nc     Gnd -- | 3  6 | &lt;- /RESET   /CSin -&gt; | 4  5 | -&gt; /CSout  A 10kΩ resistor is placed between the coin cell and Vbat.  GIZA is a standard battery monitor and supervisor, similar to the MM1026."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="281" xml:space="preserve">GIZA: 8-pin 0.05"-pitch SOP

   Vbat -&gt; | 1  8 | &lt;- Vconsole
   Vups &lt;- | 2  7 | ?? nc
    Gnd -- | 3  6 | &lt;- /RESET
  /CSin -&gt; | 4  5 | -&gt; /CSout

A 10kΩ resistor is placed between the coin cell and Vbat.

GIZA is a standard battery monitor and supervisor, similar to the MM1026.</text>
    <sha1>8a143bb0fc41414647f982965df68ee55fcb9f1a</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>S-3511A pinout</title>
  <ns>0</ns>
  <id>21</id>
  <revision>
    <id>72</id>
    <timestamp>2023-08-21T20:05:15Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>from the datasheet</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="173" xml:space="preserve">Seiko Instruments Inc. S-3511A: 8-pin 0.65mm-pitch SSOP

 /INT &lt;- | 1  8 | -- Vdd
  XIN -&gt; | 2  7 | &lt;&gt; SIO
 XOUT &lt;- | 3  6 | &lt;- /SCK (falling edges)
  Gnd -- | 4  5 | &lt;- +CS</text>
    <sha1>40d57970f56b982b805f0d51ccacb00b2d0599c7</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Interrupts</title>
  <ns>0</ns>
  <id>22</id>
  <revision>
    <id>76</id>
    <timestamp>2023-08-22T05:31:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan features fourteen different interrupts:  * CPU interrupts - six provided by the V30MZ CPU ($00-$05), * Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;): ** Level - will be reissued so long as the prerequisite condition is raised or the interrupt is disabled, ** Edge - will only be issued once; acknowledging the interrupt prevents reissuing until the conditi..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2116" xml:space="preserve">The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be reissued so long as the prerequisite condition is raised or the interrupt is disabled,
** Edge - will only be issued once; acknowledging the interrupt prevents reissuing until the condition is toggled again.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}


== I/O Ports ==

=== Interrupt Vector ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
           (lowest three bits ignored)
&lt;/pre&gt;

=== Interrupt Enable ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

=== Interrupt Status ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

=== Interrupt Acknowledge ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

=== Interrupt NMI Control ===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>f6f9c7e235996f2478e0edc747943677205d08d3</sha1>
  </revision>
  <revision>
    <id>78</id>
    <parentid>76</parentid>
    <timestamp>2023-08-22T05:33:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2203" xml:space="preserve">The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}


== I/O Ports ==

=== Interrupt Vector ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
           (lowest three bits ignored)
&lt;/pre&gt;

=== Interrupt Enable ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

=== Interrupt Status ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

=== Interrupt Acknowledge ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

=== Interrupt NMI Control ===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>d06bcd77d4161ed584c09ec810e7524498c8fa72</sha1>
  </revision>
  <revision>
    <id>81</id>
    <parentid>78</parentid>
    <timestamp>2023-08-22T05:43:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2202" xml:space="preserve">The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

=== Interrupt Vector ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
           (lowest three bits ignored)
&lt;/pre&gt;

=== Interrupt Enable ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

=== Interrupt Status ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

=== Interrupt Acknowledge ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

=== Interrupt NMI Control ===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>0156bd473b9117bb546a2da5dee79cf9ce3d3619</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>UART</title>
  <ns>0</ns>
  <id>23</id>
  <revision>
    <id>80</id>
    <timestamp>2023-08-22T05:40:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan's EXT port features an UART operating with the following configuration:  * 9,600 or 38,400 bps (bauds per second), * 8N1 (8 data bits followed by 1 stop bit, no parity).  This allows for an effective maximum transfer speed of ~1066 or ~4266 bytes per second, respectively.  The hardware also features a one-byte transmit and receive buffer, which allows for a slight delay in code when handling data to/from the console.  == Interrupts ==  The UART features tw..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1251" xml:space="preserve">The WonderSwan's EXT port features an UART operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for an effective maximum transfer speed of ~1066 or ~4266 bytes per second, respectively.

The hardware also features a one-byte transmit and receive buffer, which allows for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly active while the transmit buffer is empty (Serial Control bit 2),
* UART Receive Ready - constantly active while the receive buffer contains a byte (Serial Control bit 0).

== I/O ports ==

=== Serial Data ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Read a byte from the transmit buffer;
           Write a byte into the receive buffer.
&lt;/pre&gt;

=== Serial Control ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. .tor
|||   ||+- 1 if the receive buffer contains a byte
|||   |+-- 1 on overrun (receive buffer overflow)
|||   +--- 1 if the transmit buffer is empty (can transmit another byte)
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>726d30de1fe86dbec16fbdad08aaffc594f213fa</sha1>
  </revision>
  <revision>
    <id>85</id>
    <parentid>80</parentid>
    <timestamp>2023-08-22T06:07:09Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>forgot start bits in byte rates</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1248" xml:space="preserve">The WonderSwan's EXT port features an UART operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for an effective maximum transfer speed of 960 or 3840 bytes per second, respectively.

The hardware also features a one-byte transmit and receive buffer, which allows for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly active while the transmit buffer is empty (Serial Control bit 2),
* UART Receive Ready - constantly active while the receive buffer contains a byte (Serial Control bit 0).

== I/O ports ==

=== Serial Data ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Read a byte from the transmit buffer;
           Write a byte into the receive buffer.
&lt;/pre&gt;

=== Serial Control ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. .tor
|||   ||+- 1 if the receive buffer contains a byte
|||   |+-- 1 on overrun (receive buffer overflow)
|||   +--- 1 if the transmit buffer is empty (can transmit another byte)
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>c25a9f9ab210d50c062db28f448bddc3674ac770</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Timers</title>
  <ns>0</ns>
  <id>24</id>
  <revision>
    <id>82</id>
    <timestamp>2023-08-22T05:51:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan features two timers:  * Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles), * Vertical Blank Timer - counts down every frame.  The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically.  == Interrupts ==  Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer cond..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1409" xml:space="preserve">The WonderSwan features two timers:

* Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles),
* Vertical Blank Timer - counts down every frame.

The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically.

== Interrupts ==

Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer condition occurs.

This leads to a quirk: the timer interrupt will be triggered if the reload value is set to one ''even if the timer countdown is disabled'', so long as the interrupt is enabled.

== I/O Ports ==

=== Timer Control ===

&lt;pre&gt;
7  bit  0
---- ----
.... VvHh
     |||+- Horizontal blank timer: Enable countdown.
     ||+-- Horizontal blank timer: 0: One-shot, 1: Repeat/auto-reload.
     |+--- Vertical blank timer: Enable countdown.
     +---- Vertical blank timer: 0: One-shot, 1: Repeat/auto-reload.
&lt;/pre&gt;

=== Timer Reload ===

Read/write; contains the initial counter value. The Timer Counter port is immediately initialized with this value upon writing. If auto-reload is enabled, the interrupt trigger will re-initialize the Timer Counter port with this value.

=== Timer Counter ===

Read-only; contains the current value of the counter.

Note that if auto-reload is enabled, this will never contain the value zero.</text>
    <sha1>fd967c298363adbd262dc97603dd4fd3f7b857d7</sha1>
  </revision>
  <revision>
    <id>86</id>
    <parentid>82</parentid>
    <timestamp>2023-08-22T06:22:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1442" xml:space="preserve">The WonderSwan features two timers:

* Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles),
* Vertical Blank Timer - counts down every vertical blank (beginning of line 144).

The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically.

== Interrupts ==

Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer condition occurs.

This leads to a quirk: the timer interrupt will be triggered if the reload value is set to one ''even if the timer countdown is disabled'', so long as the interrupt is enabled.

== I/O Ports ==

=== Timer Control ===

&lt;pre&gt;
7  bit  0
---- ----
.... VvHh
     |||+- Horizontal blank timer: Enable countdown.
     ||+-- Horizontal blank timer: 0: One-shot, 1: Repeat/auto-reload.
     |+--- Vertical blank timer: Enable countdown.
     +---- Vertical blank timer: 0: One-shot, 1: Repeat/auto-reload.
&lt;/pre&gt;

=== Timer Reload ===

Read/write; contains the initial counter value. The Timer Counter port is immediately initialized with this value upon writing. If auto-reload is enabled, the interrupt trigger will re-initialize the Timer Counter port with this value.

=== Timer Counter ===

Read-only; contains the current value of the counter.

Note that if auto-reload is enabled, this will never contain the value zero.</text>
    <sha1>46e7c3f6a0fbc79aa4e6e3304aa04d8b76bd9457</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Timing</title>
  <ns>0</ns>
  <id>7</id>
  <revision>
    <id>84</id>
    <parentid>18</parentid>
    <timestamp>2023-08-22T05:55:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1152" xml:space="preserve">== Clocks ==

The WonderSwan is clocked with a master clock of approximately 12288000 Hz (= 12.288 MHz).

This clock is split into four internal memory access quadrants, running at 3072000 Hz (= 3.072 MHz) each. Three of those are used by the console in "mono" mode: [[CPU|NEC V30MZ]], [[Display]] and [[Sound]]. On the WonderSwan Color, the fourth quadrant is used to handle color palette reads during display drawing.

Out of those, only the CPU quadrant can access the cartridge bus. It can be additionally configured to use one of two wait states:

* 1 cycle access - an effective bus speed of 3072000 Hz, same as the CPU,
* 3 cycle access - an effective bus speed of 1024000 Hz.

== Display ==

By default, a WonderSwan frame consists of 159 lines, 144 of which are visible. Each line consists of 256 clock cycles, of which 224 are used to draw a pixel at a time. This leads to a total duration of 40704 clock cycles per frame, for an effective default refresh rate of approximately 75.472 Hz.

Vertical blanks are always triggered on line 144; if the display is set to be shorter than 144 lines, vertical blank interrupts will never be triggered.</text>
    <sha1>60be051bf7aff01c78719733d2689cf35c3b09c7</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Memory map</title>
  <ns>0</ns>
  <id>25</id>
  <revision>
    <id>87</id>
    <timestamp>2023-08-22T06:44:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan's SoC enforces the following memory map layout:  {| class="wikitable" |+ WonderSwan SoC linear memory map ! Bus ! colspan="2" | Address range ! Access width ! Access speed ! Read/Write |- | Internal | colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF | 16-bit | 1 cycle | RW |- | rowspan="2" | Cartridge | rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF | style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF | 8-bit | ??? | RW |- | styl..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3313" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock. This allows for a mostly stall-free development experience.

However, a few elements of the memory live at fixed locations.

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
| rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>3c01fc9bb6a3b27a0fcea1aa4be4a130254c1bde</sha1>
  </revision>
  <revision>
    <id>89</id>
    <parentid>87</parentid>
    <timestamp>2023-08-22T06:46:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3353" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
| rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>8a0fc33423fcca5e8da906128ced94c41024823b</sha1>
  </revision>
  <revision>
    <id>90</id>
    <parentid>89</parentid>
    <timestamp>2023-08-22T06:46:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3365" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
| rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>2566d8299bf41085570e23e59bc810bd2c85e464</sha1>
  </revision>
  <revision>
    <id>91</id>
    <parentid>90</parentid>
    <timestamp>2023-08-22T06:46:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3365" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
! rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>c310c2adf5fa5213afd4f94023c3013547037247</sha1>
  </revision>
  <revision>
    <id>92</id>
    <parentid>91</parentid>
    <timestamp>2023-08-22T06:47:56Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3604" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
! rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

Remember that just because an element exists in memory, it doesn't have to be fully utilized; for example, it is common for a WonderSwan game to only reserve sixteen out of the 256 vectors, reusing the remaining 240 as general RAM space.

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>cd3314691954b040e8b554f89108be8b9af5aa78</sha1>
  </revision>
  <revision>
    <id>93</id>
    <parentid>92</parentid>
    <timestamp>2023-08-22T06:48:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3614" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
! rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

Remember that just because an element exists in memory, it doesn't have to be fully utilized; for example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space.

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>868c10ecec1911bae1a1b05132c9e31d5f2a4e10</sha1>
  </revision>
</page>
<page arvcontinue="20230820183526|51">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>94</id>
    <timestamp>2023-08-22T08:16:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>initial page</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5990" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... rrrr gggg bbbb
     |||| |||| ++++- Blue (0-15)
     |||| ++++------ Green (0-15)
     ++++----------- Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
vhbp pppt tttt tttt
|||| |||+-++++-++++- Tile index (0-511)
|||+-+++------------ Palette (0-15)
||+----------------- Tile bank (0-1) - color only
|+------------------ Horizontal flip
+------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites, with a limit of 32 visible sprites per line.

These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
31                 bit                  0
---- ---- ---- ----   ---- ---- ---- ----
xxxx xxxx yyyy yyyy   vhPi pppt tttt tttt
|||| |||| |||| ||||   |||| |||+-++++-++++- Tile index (0-511) - only bank 0
|||| |||| |||| ||||   |||| +++------------ Palette (0-7) - mapped to screen palettes 8-15
|||| |||| |||| ||||   |||+---------------- Window location - 0 = inside, 1 = outside
|||| |||| |||| ||||   ||+----------------- Priority - 0 = behind Screen 2, 1 = in front of Screen 2
|||| |||| |||| ||||   |+------------------ Horizontal flip
|||| |||| |||| ||||   +------------------- Vertical flip
|||| |||| ++++-++++----------------------- Y coordinate
++++-++++--------------------------------- X coordinate
&lt;/pre&gt;

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.</text>
    <sha1>71796d349a1bb36c3ef8ca4fd0ac9f1bcd899df5</sha1>
  </revision>
  <revision>
    <id>95</id>
    <parentid>94</parentid>
    <timestamp>2023-08-22T08:25:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8001" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... rrrr gggg bbbb
     |||| |||| ++++- Blue (0-15)
     |||| ++++------ Green (0-15)
     ++++----------- Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
vhbp pppt tttt tttt
|||| |||+-++++-++++- Tile index (0-511)
|||+-+++------------ Palette (0-15)
||+----------------- Tile bank (0-1) - color only
|+------------------ Horizontal flip
+------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites, with a limit of 32 visible sprites per line.

These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
31                 bit                  0
---- ---- ---- ----   ---- ---- ---- ----
xxxx xxxx yyyy yyyy   vhPi pppt tttt tttt
|||| |||| |||| ||||   |||| |||+-++++-++++- Tile index (0-511) - only bank 0
|||| |||| |||| ||||   |||| +++------------ Palette (0-7) - mapped to screen palettes 8-15
|||| |||| |||| ||||   |||+---------------- Window location - 0 = inside, 1 = outside
|||| |||| |||| ||||   ||+----------------- Priority - 0 = behind Screen 2, 1 = in front of Screen 2
|||| |||| |||| ||||   |+------------------ Horizontal flip
|||| |||| |||| ||||   +------------------- Vertical flip
|||| |||| ++++-++++----------------------- Y coordinate
++++-++++--------------------------------- X coordinate
&lt;/pre&gt;

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

=== Display Control ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

=== Display Background ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

=== Display Current Line ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

=== Display Interrupt Line ===

The line to emit an interrupt on.

=== Sprite Table Address ===

=== Sprite Table First ===

=== Sprite Table Count ===

=== Screen Address ===

=== LCD Control ===

=== LCD Icon Control ===

=== LCD Final Line ===

=== LCD Back Porch Line (WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

=== LCD Status ===

=== LCD Timing Configuration (SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.</text>
    <sha1>2d5ec5640684340fb317402ccebfe771786c63de</sha1>
  </revision>
  <revision>
    <id>97</id>
    <parentid>95</parentid>
    <timestamp>2023-08-22T08:38:25Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8231" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8   7  bit  0
 ---- ----   ---- ----
 .... rrrr   gggg bbbb
      ||||   |||| ||||
      ||||   |||| ++++- Blue (0-15)
      ||||   ++++------ Green (0-15)
      ++++------------- Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8   7  bit  0
 ---- ----   ---- ----
 vhbp pppt   tttt tttt
 |||| ||||   |||| ||||
 |||| |||+---++++-++++- Tile index (0-511)
 |||+-+++-------------- Palette (0-15)
 ||+------------------- Tile bank (0-1) - color only
 |+-------------------- Horizontal flip
 +--------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites, with a limit of 32 visible sprites per line.

These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
31  bit  24 23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----   ---- ----
 xxxx xxxx   yyyy yyyy   vhPi pppt   tttt tttt
 |||| ||||   |||| ||||   |||| ||||   |||| ||||
 |||| ||||   |||| ||||   |||| |||+---++++-++++- Tile index (0-511) - only bank 0
 |||| ||||   |||| ||||   |||| +++-------------- Palette (0-7) - mapped to screen palettes 8-15
 |||| ||||   |||| ||||   |||+------------------ Window location - 0 = inside, 1 = outside
 |||| ||||   |||| ||||   ||+------------------- Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |||| ||||   |||| ||||   |+-------------------- Horizontal flip
 |||| ||||   |||| ||||   +--------------------- Vertical flip
 |||| ||||   ++++-++++------------------------- Y coordinate
 ++++-++++------------------------------------- X coordinate
&lt;/pre&gt;

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

=== Display Control ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

=== Display Background ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

=== Display Current Line ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

=== Display Interrupt Line ===

The line to emit an interrupt on.

=== Sprite Table Address ===

=== Sprite Table First ===

=== Sprite Table Count ===

=== Screen Address ===

=== LCD Control ===

=== LCD Icon Control ===

=== LCD Final Line ===

=== LCD Back Porch Line (WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

=== LCD Status ===

=== LCD Timing Configuration (SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.</text>
    <sha1>b6a6a14041dd4b352c4a4e65009ab1e479b557b8</sha1>
  </revision>
  <revision>
    <id>99</id>
    <parentid>97</parentid>
    <timestamp>2023-08-22T09:15:27Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10327" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8   7  bit  0
 ---- ----   ---- ----
 .... rrrr   gggg bbbb
      ||||   |||| ||||
      ||||   |||| ++++- Blue (0-15)
      ||||   ++++------ Green (0-15)
      ++++------------- Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8   7  bit  0
 ---- ----   ---- ----
 vhbp pppt   tttt tttt
 |||| ||||   |||| ||||
 |||| |||+---++++-++++- Tile index (0-511)
 |||+-+++-------------- Palette (0-15)
 ||+------------------- Tile bank (0-1) - color only
 |+-------------------- Horizontal flip
 +--------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites, with a limit of 32 visible sprites per line.

These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
31  bit  24 23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----   ---- ----
 xxxx xxxx   yyyy yyyy   vhPi pppt   tttt tttt
 |||| ||||   |||| ||||   |||| ||||   |||| ||||
 |||| ||||   |||| ||||   |||| |||+---++++-++++- Tile index (0-511) - only bank 0
 |||| ||||   |||| ||||   |||| +++-------------- Palette (0-7) - mapped to screen palettes 8-15
 |||| ||||   |||| ||||   |||+------------------ Window location - 0 = inside, 1 = outside
 |||| ||||   |||| ||||   ||+------------------- Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |||| ||||   |||| ||||   |+-------------------- Horizontal flip
 |||| ||||   |||| ||||   +--------------------- Vertical flip
 |||| ||||   ++++-++++------------------------- Y coordinate
 ++++-++++------------------------------------- X coordinate
&lt;/pre&gt;

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

=== Display Control ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

=== Display Background ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

=== Display Current Line ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

=== Display Interrupt Line ===

The line to emit an interrupt on.

=== Sprite Table Address ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

=== Sprite Table First ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

=== Sprite Table Count ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

=== Screen Address ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

=== LCD Control ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

=== LCD Icon Control ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

=== LCD Final Line ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

=== LCD Back Porch Line (WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

=== LCD Status ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== LCD Timing Configuration (SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>7c7f89b52c9e5543d01bf50884cba7ce1ad3308b</sha1>
  </revision>
  <revision>
    <id>100</id>
    <parentid>99</parentid>
    <timestamp>2023-08-22T09:21:54Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Register formatting. Reworks sprite byte presentation for clarity.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10190" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites, with a limit of 32 visible sprites per line.

These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

=== Display Control ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

=== Display Background ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

=== Display Current Line ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

=== Display Interrupt Line ===

The line to emit an interrupt on.

=== Sprite Table Address ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

=== Sprite Table First ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

=== Sprite Table Count ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

=== Screen Address ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

=== LCD Control ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

=== LCD Icon Control ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

=== LCD Final Line ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

=== LCD Back Porch Line (WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

=== LCD Status ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== LCD Timing Configuration (SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>51a1cad85493db4a12cf8fc494667b8f240f4a79</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>101</id>
    <parentid>98</parentid>
    <timestamp>2023-08-22T09:58:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18461" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| [[UART#serial Data|Serial Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! [[UART]]
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .tor&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>a8a41e3fc17cc26e90de382bac208d735b5ac017</sha1>
  </revision>
  <revision>
    <id>102</id>
    <parentid>101</parentid>
    <timestamp>2023-08-22T09:58:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18462" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| [[UART#serial Data|Serial Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! [[UART]]
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. .tor&lt;/tt&gt;
| RW8
| Enable (e), Baud rate (b), Reset Overrun (O),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>37acd8dc350f521577baf03fc2f4dbc3c3d06cc3</sha1>
  </revision>
  <revision>
    <id>115</id>
    <parentid>102</parentid>
    <timestamp>2023-08-22T11:34:13Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Splits Serial Control into Status and Control.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18633" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! [[UART]]
! $B1
| [[UART#serial Data|Serial Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>60e9d8f0e55f5d3883559756bbbd229ebb7f3c9c</sha1>
  </revision>
  <revision>
    <id>124</id>
    <parentid>115</parentid>
    <timestamp>2023-08-22T12:07:24Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Splits Serial Data into Serial Receive Data and Serial Transmit Data.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18817" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>8a8559dc8c973cd36b56b73817186d1c7173585d</sha1>
  </revision>
  <revision>
    <id>126</id>
    <parentid>124</parentid>
    <timestamp>2023-08-22T12:08:26Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>More explicit Serial Data descriptions.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18848" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>afc5e49e69423646bad0b59d4bd07f4e8ded65df</sha1>
  </revision>
  <revision>
    <id>141</id>
    <parentid>126</parentid>
    <timestamp>2023-08-22T12:46:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18991" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="20" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
| $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>8379a2abae9a8450ba981076ea738c8562dc72ff</sha1>
  </revision>
  <revision>
    <id>142</id>
    <parentid>141</parentid>
    <timestamp>2023-08-22T12:47:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18991" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="3" | Internal EEPROM
! $BA
| Internal EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| Internal EEPROM Command
|
| RW16
|
|-
! $BE
| Internal EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... PEWR ..rd&lt;/tt&gt;
| RW16
| Protect (P), Erase (E), Write (W), Read (R),
Ready (r), Done (d)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>74ada3cb20536887a3e61a506a5c4facb30e2f17</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Sound</title>
  <ns>0</ns>
  <id>27</id>
  <revision>
    <id>103</id>
    <timestamp>2023-08-22T10:00:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan features the following sound hardware:  * Four audio channels: ** channel 1 - wavetable (32 x 4-bit samples), ** channel 2 - wavetable or 8-bit unsigned PCM sample, ** channel 3 - wavetable with optional hardware sweep, ** channel 4 - wavetable or LFSR noise, * [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output, * 24000 Hz output: ** internal speaker - 8-bit, mono, ** headphone output - 16-bit, stereo.  The sound is mix..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5772" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

=== Sound Channel Frequency ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---------  ---------
 .... .ddd  dddd dddd
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

=== Sound Channel Volume ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

=== Sound Channel 2 Voice Sample ===

&lt;pre&gt;
7  bit  0
---------
ssss ssss
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

=== Sound Channel 3 Sweep Amount ===

&lt;pre&gt;
7  bit  0
---------
vvvv vvvv
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

=== Sound Channel 3 Sweep Ticks ===

&lt;pre&gt;
7  bit  0
---------
...t tttt
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

=== Sound Channel 4 Noise Control ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

1. Create a new bit by XORing bit 7 with the tap bit.
2. Shift the LFSR register one bit to the left.
3. Write the new bit as bit 0.
4. Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

=== Sound Wavetable Address ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

=== Sound Channel Control ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

=== Sound Output Control ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

=== Sound Channel 4 LFSR Register ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

=== Sound Channel 2 Voice Volume ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>281bb4a2d3ed5342e07ac0f3c97b9665d8c16374</sha1>
  </revision>
  <revision>
    <id>104</id>
    <parentid>103</parentid>
    <timestamp>2023-08-22T10:01:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5768" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

=== Sound Channel Frequency ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---------  ---------
 .... .ddd  dddd dddd
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

=== Sound Channel Volume ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

=== Sound Channel 2 Voice Sample ===

&lt;pre&gt;
7  bit  0
---------
ssss ssss
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

=== Sound Channel 3 Sweep Amount ===

&lt;pre&gt;
7  bit  0
---------
vvvv vvvv
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

=== Sound Channel 3 Sweep Ticks ===

&lt;pre&gt;
7  bit  0
---------
...t tttt
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

=== Sound Channel 4 Noise Control ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

=== Sound Wavetable Address ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

=== Sound Channel Control ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

=== Sound Output Control ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

=== Sound Channel 4 LFSR Register ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

=== Sound Channel 2 Voice Volume ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>c958317b70f4dfaf25b9e807be7c3c9b9a659a13</sha1>
  </revision>
  <revision>
    <id>105</id>
    <parentid>104</parentid>
    <timestamp>2023-08-22T10:09:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7194" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

=== Sound Channel Frequency ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---------  ---------
 .... .ddd  dddd dddd
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

=== Sound Channel Volume ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

=== Sound Channel 2 Voice Sample ===

&lt;pre&gt;
7  bit  0
---------
ssss ssss
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

=== Sound Channel 3 Sweep Amount ===

&lt;pre&gt;
7  bit  0
---------
vvvv vvvv
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

=== Sound Channel 3 Sweep Ticks ===

&lt;pre&gt;
7  bit  0
---------
...t tttt
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

=== Sound Channel 4 Noise Control ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

=== Sound Wavetable Address ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

=== Sound Channel Control ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

=== Sound Output Control ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

=== Sound Channel 4 LFSR Register ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

=== Sound Channel 2 Voice Volume ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>ab4290edf1a78bb26fd886a725a7414cda6975ba</sha1>
  </revision>
  <revision>
    <id>106</id>
    <parentid>105</parentid>
    <timestamp>2023-08-22T10:10:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7374" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

=== Sound Channel Frequency ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---------  ---------
 .... .ddd  dddd dddd
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

=== Sound Channel Volume ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

=== Sound Channel 2 Voice Sample ===

&lt;pre&gt;
7  bit  0
---------
ssss ssss
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

=== Sound Channel 3 Sweep Amount ===

&lt;pre&gt;
7  bit  0
---------
vvvv vvvv
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

=== Sound Channel 3 Sweep Ticks ===

&lt;pre&gt;
7  bit  0
---------
...t tttt
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

=== Sound Channel 4 Noise Control ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

=== Sound Wavetable Address ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

=== Sound Channel Control ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

=== Sound Output Control ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

=== Sound Channel 4 LFSR Register ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

=== Sound Channel 2 Voice Volume ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>e34c49ad924c8300bc2d806f91f86c91ee38bc9c</sha1>
  </revision>
  <revision>
    <id>107</id>
    <parentid>106</parentid>
    <timestamp>2023-08-22T10:36:39Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7508" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

=== Sound Channel Frequency ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

=== Sound Channel Volume ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

=== Sound Channel 2 Voice Sample ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

=== Sound Channel 3 Sweep Amount ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

=== Sound Channel 3 Sweep Ticks ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

=== Sound Channel 4 Noise Control ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

=== Sound Wavetable Address ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

=== Sound Channel Control ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

=== Sound Output Control ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

=== Sound Channel 4 LFSR Register ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

=== Sound Channel 2 Voice Volume ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>da0c63c9675ff538908c8f73233c74e655f7b49c</sha1>
  </revision>
  <revision>
    <id>119</id>
    <parentid>107</parentid>
    <timestamp>2023-08-22T11:55:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>adjust port category name formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8042" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>ba9f2fd5b05f6f5e6a024d314fb7ba5774ada07b</sha1>
  </revision>
  <revision>
    <id>120</id>
    <parentid>119</parentid>
    <timestamp>2023-08-22T11:56:09Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8042" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

[[Hyper Voice]] functionality is documented on its own sub-page.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>93b4bd92460a9225a15821ef72100ec43db6b8c7</sha1>
  </revision>
  <revision>
    <id>125</id>
    <parentid>120</parentid>
    <timestamp>2023-08-22T12:08:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8065" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.</text>
    <sha1>3af9bda4a3bdbf03e3809535585fc943928bad3e</sha1>
  </revision>
  <revision>
    <id>127</id>
    <parentid>125</parentid>
    <timestamp>2023-08-22T12:11:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8707" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Channel Output Right}}
=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>bdf9dfdae7d8ce5560cf92ed8be8196440f71563</sha1>
  </revision>
  <revision>
    <id>147</id>
    <parentid>127</parentid>
    <timestamp>2023-08-22T14:08:42Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8773" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /
                  port $96     | &lt;&lt;5 |      port $9A
                               |_____|
                                 | |
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Channel Output Right}}
=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>e39a122aa082e9bd17f06d6296043cbac289e10b</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Timers</title>
  <ns>0</ns>
  <id>24</id>
  <revision>
    <id>108</id>
    <parentid>86</parentid>
    <timestamp>2023-08-22T10:50:33Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1452" xml:space="preserve">The WonderSwan features two timers:

* Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles),
* Vertical Blank Timer - counts down every vertical blank (beginning of line 144).

The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically.

== Interrupts ==

Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer condition occurs.

This leads to a quirk: the timer interrupt will be triggered if the reload value is set to one ''even if the timer countdown is disabled'', so long as the interrupt is enabled.

== I/O Ports ==

=== Timer Control ===

&lt;pre&gt;
7  bit  0
---- ----
.... VvHh
     ||||
     |||+- Horizontal blank timer: Enable countdown.
     ||+-- Horizontal blank timer: 0: One-shot, 1: Repeat/auto-reload.
     |+--- Vertical blank timer: Enable countdown.
     +---- Vertical blank timer: 0: One-shot, 1: Repeat/auto-reload.
&lt;/pre&gt;

=== Timer Reload ===

Read/write; contains the initial counter value. The Timer Counter port is immediately initialized with this value upon writing. If auto-reload is enabled, the interrupt trigger will re-initialize the Timer Counter port with this value.

=== Timer Counter ===

Read-only; contains the current value of the counter.

Note that if auto-reload is enabled, this will never contain the value zero.</text>
    <sha1>ee1589b1d5e228967f28f19788a66ec00e318d77</sha1>
  </revision>
  <revision>
    <id>117</id>
    <parentid>108</parentid>
    <timestamp>2023-08-22T11:51:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>adjust port category name formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1652" xml:space="preserve">The WonderSwan features two timers:

* Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles),
* Vertical Blank Timer - counts down every vertical blank (beginning of line 144).

The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically.

== Interrupts ==

Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer condition occurs.

This leads to a quirk: the timer interrupt will be triggered if the reload value is set to one ''even if the timer countdown is disabled'', so long as the interrupt is enabled.

== I/O Ports ==

=== Timer Control ($A2, $A3) ===

&lt;pre&gt;
7  bit  0
---- ----
.... VvHh
     ||||
     |||+- Horizontal blank timer: Enable countdown.
     ||+-- Horizontal blank timer: 0: One-shot, 1: Repeat/auto-reload.
     |+--- Vertical blank timer: Enable countdown.
     +---- Vertical blank timer: 0: One-shot, 1: Repeat/auto-reload.
&lt;/pre&gt;

{{Anchor|Timer Reload}}
=== Horizontal Blank Timer Reload ($A4, $A5) ===

=== Vertical Blank Timer Reload ($A6, $A7) ===

Contains the initial counter value. The Timer Counter port is immediately initialized with this value upon writing. If auto-reload is enabled, the interrupt trigger will re-initialize the Timer Counter port with this value.

{{Anchor|Timer Counter}}
=== Horizontal Blank Timer Counter ($A8, $A9 read) ===

=== Vertical Blank Timer Counter ($AA, $AB read) ===

Contains the current value of the counter.

Note that if auto-reload is enabled, this will never contain the value zero.</text>
    <sha1>2da5adcb175b3fb05cb340c185cab789b3c34b60</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>UART</title>
  <ns>0</ns>
  <id>23</id>
  <revision>
    <id>109</id>
    <parentid>85</parentid>
    <timestamp>2023-08-22T10:51:18Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1258" xml:space="preserve">The WonderSwan's EXT port features an UART operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for an effective maximum transfer speed of 960 or 3840 bytes per second, respectively.

The hardware also features a one-byte transmit and receive buffer, which allows for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly active while the transmit buffer is empty (Serial Control bit 2),
* UART Receive Ready - constantly active while the receive buffer contains a byte (Serial Control bit 0).

== I/O ports ==

=== Serial Data ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Read a byte from the transmit buffer;
           Write a byte into the receive buffer.
&lt;/pre&gt;

=== Serial Control ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. .tor
|||   |||
|||   ||+- 1 if the receive buffer contains a byte
|||   |+-- 1 on overrun (receive buffer overflow)
|||   +--- 1 if the transmit buffer is empty (can transmit another byte)
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>7576a61b5a2c1f3268a4b357edbb271eb6d1222d</sha1>
  </revision>
  <revision>
    <id>114</id>
    <parentid>109</parentid>
    <timestamp>2023-08-22T11:30:47Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Fixes data register. Adds register addresses and access types. Splits Serial Control into Status and Control.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1522" xml:space="preserve">The WonderSwan's EXT port features an UART operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for an effective maximum transfer speed of 960 or 3840 bytes per second, respectively.

The hardware also features one-byte transmit and receive buffers, which allow for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly active while the transmit buffer is empty (Serial Status bit 2),
* UART Receive Ready - constantly active while the receive buffer contains a byte (Serial Status bit 0).

== I/O ports ==

{{Anchor|Serial Data}}
=== Serial Data ($B1) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Read a byte from the receive buffer, or
           Write a byte into the transmit buffer.
&lt;/pre&gt;

{{Anchor|Serial Status}}
=== Serial Status ($B3 read) ===

&lt;pre&gt;
7  bit  0
---- ----
eb.. .tor
||    |||
||    ||+- 1 if the receive buffer contains a byte
||    |+-- 1 on overrun (receive buffer overflow)
||    +--- 1 if the transmit buffer is empty (can transmit another byte)
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;

{{Anchor|Serial Control}}
=== Serial Control ($B3 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. ....
|||
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>03f36154be516590cd1f795c76fcb9cd907ba267</sha1>
  </revision>
  <revision>
    <id>123</id>
    <parentid>114</parentid>
    <timestamp>2023-08-22T12:05:15Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Splits Serial Data into Serial Receive Data and Serial Transmit Data</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1635" xml:space="preserve">The WonderSwan's EXT port features an UART operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for an effective maximum transfer speed of 960 or 3840 bytes per second, respectively.

The hardware also features one-byte transmit and receive buffers, which allow for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly active while the transmit buffer is empty (Serial Status bit 2),
* UART Receive Ready - constantly active while the receive buffer contains a byte (Serial Status bit 0).

== I/O ports ==

{{Anchor|Serial Receive Data}}
=== Serial Receive Data ($B1 read) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Receive buffer value
&lt;/pre&gt;

{{Anchor|Serial Transmit Data}}
=== Serial Transmit Data ($B1 write) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Transmit buffer value
&lt;/pre&gt;

{{Anchor|Serial Status}}
=== Serial Status ($B3 read) ===

&lt;pre&gt;
7  bit  0
---- ----
eb.. .tor
||    |||
||    ||+- 1 if the receive buffer contains a byte
||    |+-- 1 on overrun (receive buffer overflow)
||    +--- 1 if the transmit buffer is empty (can transmit another byte)
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;

{{Anchor|Serial Control}}
=== Serial Control ($B3 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. ....
|||
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>f8c48f74235142dc49c79d44086399927796ae9a</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Interrupts</title>
  <ns>0</ns>
  <id>22</id>
  <revision>
    <id>110</id>
    <parentid>81</parentid>
    <timestamp>2023-08-22T10:53:02Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2207" xml:space="preserve">The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

=== Interrupt Vector ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
           (lowest three bits ignored)
&lt;/pre&gt;

=== Interrupt Enable ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

=== Interrupt Status ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

=== Interrupt Acknowledge ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

=== Interrupt NMI Control ===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>1dde55d95e5d78904c7751698637520bdac3c324</sha1>
  </revision>
  <revision>
    <id>111</id>
    <parentid>110</parentid>
    <timestamp>2023-08-22T11:04:22Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Moves Interrupts below table of contents.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2224" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

=== Interrupt Vector ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
           (lowest three bits ignored)
&lt;/pre&gt;

=== Interrupt Enable ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

=== Interrupt Status ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

=== Interrupt Acknowledge ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

=== Interrupt NMI Control ===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>ad649ec7d38abb9856b70cbaca9b3c6b901671b6</sha1>
  </revision>
  <revision>
    <id>116</id>
    <parentid>111</parentid>
    <timestamp>2023-08-22T11:48:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>adjust port category name formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2373" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector}}
=== Interrupt Vector ($B0) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Enable}}
=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

{{Anchor|Interrupt Status}}
=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
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</page>
<page arvcontinue="20230822095816|101">
  <title>Template:Anchor</title>
  <ns>10</ns>
  <id>28</id>
  <revision>
    <id>112</id>
    <timestamp>2023-08-22T11:24:56Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds anchor template.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="704" xml:space="preserve">{{#if:{{{1|&lt;noinclude&gt;1&lt;/noinclude&gt;}}}|&lt;ins id="{{{1|&lt;noinclude&gt;test-anchor&lt;/noinclude&gt;}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{2|}}}|&lt;ins id="{{{2|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{3|}}}|&lt;ins id="{{{3|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{4|}}}|&lt;ins id="{{{4|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{5|}}}|&lt;ins id="{{{5|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{6|}}}|&lt;ins id="{{{6|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{7|}}}|&lt;ins id="{{{7|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{8|}}}|&lt;ins id="{{{8|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{9|}}}|&lt;ins id="{{{9|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{10|}}}|&lt;ins id="{{{10|}}}"&gt;&lt;/ins&gt;}}&lt;!--
--&gt;{{#if:{{{11|}}}|&lt;span class="error"&gt;[[Template:Anchor]]: Too many anchors; maximum is 10.&lt;/span&gt;}}&lt;noinclude&gt;{{Template:Anchor/doc}}&lt;/noinclude&gt;</text>
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  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Template:Anchor/doc</title>
  <ns>10</ns>
  <id>29</id>
  <revision>
    <id>113</id>
    <timestamp>2023-08-22T11:25:25Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds anchor template doc.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="552" xml:space="preserve">{| class="wikitable"
| This documentation is at: [[Template:Anchor/doc]]
|}

This template manually adds one or more HTML anchors, allowing links to locations other than section headings.

Usage can create a single named anchor, or many at the same location:

&lt;code&gt;&lt;nowiki&gt;
 {{Anchor|name1}}
&lt;/nowiki&gt;&lt;/code&gt;

&lt;code&gt;&lt;nowiki&gt;
 {{Anchor|name1|name2|name3...}}
&lt;/nowiki&gt;&lt;/code&gt;

Linking can be used within the same page, or in cross-page links:

&lt;code&gt;&lt;nowiki&gt;
 [[#name1|name1]]
&lt;/nowiki&gt;&lt;/code&gt;

&lt;code&gt;&lt;nowiki&gt;
 [[Pagename#name1|name1]]
&lt;/nowiki&gt;&lt;/code&gt;</text>
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  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Keypad</title>
  <ns>0</ns>
  <id>9</id>
  <revision>
    <id>118</id>
    <parentid>26</parentid>
    <timestamp>2023-08-22T11:52:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2797" xml:space="preserve">The WonderSwan SoC features a 4 by 3 keypad matrix.

== I/O Ports ==

=== Keypad Scan ($B5) ===

Scanning is done via writing to and reading from port $B5.

&lt;pre&gt;
7  bit  0
---- ----
.iii oooo
 ||| ++++- Output rows (0-3)
 +++------ Input rows  (4-6)
&lt;/pre&gt;

The standard procedure is to read rows 4, 5 and 6 in order, shifting their values into one twelve-bit mask like so:

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... 4444 5555 6666
&lt;/pre&gt;

Typical keypad scanning implementations introduce a delay between writing to and reading from the matrix, allowing the scanned values to stabilize. For example, one can use the DAA opcode for doing so.

== Startup override ==

On startup, the [[boot ROM]] checks whether or not certain output rows are forced high when all input rows are disabled. This triggers a startup override prior to the boot logo:

* Input row 0 - jump to 4000:0000,
* Input row 1 - jump to 4000:0010.

As this override is done before boot ROM lockout, it can be used to dump the boot ROM.

== Keypad arrangement ==

=== WonderSwan ===

==== Layout ====

&lt;pre&gt;
    Y1
 Y4    Y2
    Y3


    X1
 X4    X2                              A
    X3       Sound Start Power      B
                    (St)
&lt;/pre&gt;

Sound and Power buttons are not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Y4 - Y3 - Y2 - Y1 -
      |    |    |    |
5--- X4 - X3 - X2 - X1 -
      |    |    |    |
6---  B -  A - St ---+--
      |    |    |    |

&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... yyyy xxxx bas.
     |||| |||| ||+- Start
     |||| |||| |+-- A
     |||| |||| +--- B
     |||| ++++----- X4, X3, X2, X1
     ++++---------- Y4, Y3, Y2, Y1      
&lt;/pre&gt;

=== Pocket Challenge V2 ===

==== Layout ====

&lt;pre&gt;
  Power


     Esc
                                 View
   Up                                  Clear
                                       (Clr)
 Lft Rgh                           Circle
                                    (Crc)
   Dwn                           Pass
                                (Pas)
&lt;/pre&gt;

The Power switch is not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Pas  Crc --+-- Clr -
      |    |    |    |
5--- Rgh  Esc --+- View -
      |    |    |    |
6--- Up - Dwn --+-- Lft -
      |    |    |    |
               [1]
&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15      bit       0
---- ---- ---- ----
.... pc1C re1v ud1l
     || | || | || +- Left
     || | || | |+--- Down
     || | || | +---- Up
     || | || +------ View
     || | |+-------- Esc
     || | +--------- Right
     || +----------- Clear
     |+------------- Circle
     +-------------- Pass
&lt;/pre&gt;</text>
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</page>
<page arvcontinue="20230822095816|101">
  <title>Display</title>
  <ns>0</ns>
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    <id>121</id>
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      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>adjust port category name formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10688" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites, with a limit of 32 visible sprites per line.

These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}
=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== LCD Timing Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>7655e18ba632a081d55fa75f2261d9f46fe59337</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>122</id>
    <parentid>27</parentid>
    <timestamp>2023-08-22T12:03:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>adjust port category name formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4908" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || ?
|-
| $2F || HTR || ?
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]]
|-
| $01 || [[Bandai 2003]]
|-
| $02 || [[KARNAK]] (Pocket Challenge V2)
|}</text>
    <sha1>2f32eef755f8983aaf5fbe43bf1ec315d4ecaef8</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Hyper Voice</title>
  <ns>0</ns>
  <id>30</id>
  <revision>
    <id>128</id>
    <timestamp>2023-08-22T12:20:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.  == I/O Ports ==  === Hyper Voice Left Output ($64, $65) ===  === Hyper Voice Right Output ($66, $67) ===  &lt;pre&gt; 15  bit  8  7  bit  0  ---- ----  ---- ----  ssss ssss  ssss ssss  ++++-++++--++++-++++..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2105" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

=== Hyper Voice Left Output ($64, $65) ===

=== Hyper Voice Right Output ($66, $67) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] output registers, these can be written to - allowing for direct 16-bit sample output.

=== Hyper Voice Left Input ($68) ===

=== Hyper Voice Right Input ($69) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  0  7  bit  0
 ---- ----  ---- ----
 .mmc ....  errr ffss
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Input channel: 0 = left, 1 = right
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>1e8ef6830e0e57e1cdc5a12c98702ee09a8f767a</sha1>
  </revision>
  <revision>
    <id>129</id>
    <parentid>128</parentid>
    <timestamp>2023-08-22T12:21:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2202" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65) ===

=== Hyper Voice Right Output ($66, $67) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68) ===

=== Hyper Voice Right Input ($69) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  0  7  bit  0
 ---- ----  ---- ----
 .mmc ....  errr ffss
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Input channel: 0 = left, 1 = right
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>264d841844b9f7dab15743e5ce92d9adee458e8d</sha1>
  </revision>
  <revision>
    <id>131</id>
    <parentid>129</parentid>
    <timestamp>2023-08-22T12:23:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2202" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65) ===

=== Hyper Voice Right Output ($66, $67) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68) ===

=== Hyper Voice Right Input ($69) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ....  errr ffss
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Input channel: 0 = left, 1 = right
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>51d0f63401642a3c00d3e9660e48f6ad8abc6fa5</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>130</id>
    <parentid>88</parentid>
    <timestamp>2023-08-22T12:23:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1204" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM]]
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Mapper]]
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>e7ad637cb3abfe2283f6842c5b5c5806ea23e799</sha1>
  </revision>
  <revision>
    <id>136</id>
    <parentid>130</parentid>
    <timestamp>2023-08-22T12:40:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1256" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM]]
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>1247e7a32bb26d31de899b303f39ac8b6036522a</sha1>
  </revision>
  <revision>
    <id>146</id>
    <parentid>136</parentid>
    <timestamp>2023-08-22T13:52:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1334" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>75d6c30c02e8346d5ed309791b5de20b66993cdf</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>DMA</title>
  <ns>0</ns>
  <id>31</id>
  <revision>
    <id>132</id>
    <timestamp>2023-08-22T12:35:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan Color introduced two DMA blocks:  * General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers, * Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.  == General DMA ==  {{Anchor|GDMA Source Address Low}} {{Anchor|GDMA Source Address High}} === GDMA Source Address ($40, $41, $42) ===  &lt;pre&gt; 23  bit 16 15  bit  8  7  bit  0  ---- ----  ---- ----  ---- ----  .... hhhh  llll llll  llll llll..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3202" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

DMA allows source addresses in IRAM and ROM; any attempt to access SRAM causes DMA to immediately return, even if in the middle of a transfer.

TODO: What about source addresses in ROM configured as 8-bit?

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaaa
 ++++-++++--++++-++++- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($50) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t r?ff
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.</text>
    <sha1>6d4aac1e8190fe8bcb5d7156cc1d75e913ffa279</sha1>
  </revision>
  <revision>
    <id>133</id>
    <parentid>132</parentid>
    <timestamp>2023-08-22T12:36:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3251" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

DMA allows source addresses in IRAM and ROM; any attempt to access SRAM causes DMA to immediately return, even if in the middle of a transfer.

TODO: What about source addresses in ROM configured as 8-bit?

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaaa
 ++++-++++--++++-++++- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t r?ff
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.</text>
    <sha1>e950d4ec16d0d2133faf08e3a0db2c09c8e89744</sha1>
  </revision>
  <revision>
    <id>134</id>
    <parentid>133</parentid>
    <timestamp>2023-08-22T12:38:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3269" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit 16  15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFF)
&lt;/pre&gt;

DMA allows source addresses in IRAM and ROM; any attempt to access SRAM causes DMA to immediately return, even if in the middle of a transfer.

TODO: What about source addresses in ROM configured as 8-bit?

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaaa
 ++++-++++--++++-++++- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit 16  15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t r?ff
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.</text>
    <sha1>81a0562286fe1850e951e4a95947e9e41ebe90ad</sha1>
  </revision>
  <revision>
    <id>135</id>
    <parentid>134</parentid>
    <timestamp>2023-08-22T12:38:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3277" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit 16  15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFF)
&lt;/pre&gt;

DMA allows source addresses in IRAM and ROM; any attempt to access SRAM causes DMA to immediately return, even if in the middle of a transfer.

TODO: What about source addresses in ROM configured as 8-bit?

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaaa
 ++++-++++--++++-++++- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit 16  15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit 16  15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t r?ff
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.</text>
    <sha1>9d9660d38614efd86ecdbc55e4d698510e7ac56a</sha1>
  </revision>
  <revision>
    <id>145</id>
    <parentid>135</parentid>
    <timestamp>2023-08-22T13:13:49Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Register formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3439" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFF)
&lt;/pre&gt;

DMA allows source addresses in IRAM and ROM; any attempt to access SRAM causes DMA to immediately return, even if in the middle of a transfer.

TODO: What about source addresses in ROM configured as 8-bit?

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaaa
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t r?ff
|| | | ||
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * length)&lt;/code&gt; cycles to complete.</text>
    <sha1>e651e8c40646f83c3fe88264bc2663c5b7c136e2</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>KARNAK</title>
  <ns>0</ns>
  <id>18</id>
  <revision>
    <id>137</id>
    <parentid>61</parentid>
    <timestamp>2023-08-22T12:41:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2359" xml:space="preserve">KARNAK was only used in Pocket Challenge V2 edutainment games. 

It is not yet well-documented. It is thought to be a revision of [[Bandai 2003]] that removes the RTC interface, and adds a timer IRQ and a hardware IMA ADPCM decoder.

This page should not be taken as authoritative: it has been pieced together from multiple other pieces of research. It is unclear if the GPO and Self-Flash registers exist; from PCB photos the Self-Flash register is unused if it does exist.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|- 
! Timer
! $D6
| Programmable Interval Timer
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eppp pppp&lt;/tt&gt;
| RW8
| Enable (e); Period (p). Units are the 384kHz clock to the cartridge.
|-
! rowspan=2|ADPCM
! $D8
| Packed data
| ?
| W8?
| Write two-sample packed ADPCM byte
|-
| $D9
| Unpacked data
| ?
| R8?
| Read two one-byte unpacked PCM bytes, in sequence
|}</text>
    <sha1>d62a73fb69e545595272d7d9f98e9ea07022111f</sha1>
  </revision>
  <revision>
    <id>138</id>
    <parentid>137</parentid>
    <timestamp>2023-08-22T12:41:27Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2359" xml:space="preserve">KARNAK was only used in Pocket Challenge V2 edutainment games. 

It is not yet well-documented. It is thought to be a revision of [[Bandai 2003]] that removes the RTC interface, and adds a timer IRQ and a hardware IMA ADPCM decoder.

This page should not be taken as authoritative: it has been pieced together from multiple other pieces of research. It is unclear if the GPO and Self-Flash registers exist; from PCB photos the Self-Flash register is unused if it does exist.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|- 
! Timer
! $D6
| Programmable Interval Timer
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eppp pppp&lt;/tt&gt;
| RW8
| Enable (e); Period (p). Units are the 384kHz clock to the cartridge.
|-
! rowspan=2|ADPCM
! $D8
| Packed data
| ?
| W8?
| Write two-sample packed ADPCM byte
|-
! $D9
| Unpacked data
| ?
| R8?
| Read two one-byte unpacked PCM bytes, in sequence
|}</text>
    <sha1>8c2e993b07630345cce063edaa06f4b127d9bfe8</sha1>
  </revision>
  <revision>
    <id>139</id>
    <parentid>138</parentid>
    <timestamp>2023-08-22T12:42:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2554" xml:space="preserve">KARNAK was only used in Pocket Challenge V2 edutainment games. 

It is not yet well-documented. It is thought to be a revision of [[Bandai 2003]] that removes the RTC interface, and adds a timer IRQ and a hardware IMA ADPCM decoder.

This page should not be taken as authoritative: it has been pieced together from multiple other pieces of research. It is unclear if the GPO and Self-Flash registers exist; from PCB photos the Self-Flash register is unused if it does exist.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|- 
! Timer
! $D6
| Programmable Interval Timer
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eppp pppp&lt;/tt&gt;
| RW8
| Enable (e); Period (p). Units are the 384kHz clock to the cartridge.
|-
! rowspan=2|ADPCM
! $D8
| Packed data
| ?
| W8?
| Write two-sample packed ADPCM byte
|-
! $D9
| Unpacked data
| ?
| R8?
| Read two one-byte unpacked PCM bytes, in sequence
|}

== Timer ==

If enabled, the timer will emit a [[Interrupts|cartridge interrupt]] every &lt;code&gt;((period + 1) * 2)&lt;/code&gt; cartridge clocks, where "one cartridge clock" = 384KHz = 1/8th CPU clock.</text>
    <sha1>73e45ad837d4aab16198f6550e1f8c22c8a7e28f</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Timing</title>
  <ns>0</ns>
  <id>7</id>
  <revision>
    <id>140</id>
    <parentid>84</parentid>
    <timestamp>2023-08-22T12:42:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1249" xml:space="preserve">== Clocks ==

The WonderSwan is clocked with a master clock of approximately 12288000 Hz (= 12.288 MHz).

This clock is split into four internal memory access quadrants, running at 3072000 Hz (= 3.072 MHz) each. Three of those are used by the console in "mono" mode: [[CPU|NEC V30MZ]], [[Display]] and [[Sound]]. On the WonderSwan Color, the fourth quadrant is used to handle color palette reads during display drawing.

Out of those, only the CPU quadrant can access the cartridge bus. It can be additionally configured to use one of two wait states:

* 1 cycle access - an effective bus speed of 3072000 Hz, same as the CPU,
* 3 cycle access - an effective bus speed of 1024000 Hz.

In addition, a separate 384000 Hz (3072000 / 8) clock is provided on one of the cartridge pins.

== Display ==

By default, a WonderSwan frame consists of 159 lines, 144 of which are visible. Each line consists of 256 clock cycles, of which 224 are used to draw a pixel at a time. This leads to a total duration of 40704 clock cycles per frame, for an effective default refresh rate of approximately 75.472 Hz.

Vertical blanks are always triggered on line 144; if the display is set to be shorter than 144 lines, vertical blank interrupts will never be triggered.</text>
    <sha1>0cd23cad2bf08244b0d8838df22cec6d7660e15a</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Category:Deletion requests</title>
  <ns>14</ns>
  <id>32</id>
  <revision>
    <id>143</id>
    <timestamp>2023-08-22T12:52:42Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds deletion-request category.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="153" xml:space="preserve">This is a list of pages including the &lt;nowiki&gt;{{delete}}&lt;/nowiki&gt; template, requesting a moderator to review them for deletion.

See: [[Template:Delete]]</text>
    <sha1>f5fc73d29d81cdb615aefd3b4fd885759b595dfb</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Template:Delete</title>
  <ns>10</ns>
  <id>33</id>
  <revision>
    <id>144</id>
    <timestamp>2023-08-22T12:53:13Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds deletion-request template.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="292" xml:space="preserve">&lt;noinclude&gt;Place this template on a page that you think should be deleted.

For a list of pending deletion requests see: [[:Category:Deletion requests]]

&lt;/noinclude&gt;'''''This page is requested for deletion review by a moderator.'''''
&lt;includeonly&gt;[[Category:Deletion requests]]&lt;/includeonly&gt;</text>
    <sha1>97de1a9d59533764786c50377a5383f61fabc645</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>Splash animation</title>
  <ns>0</ns>
  <id>34</id>
  <revision>
    <id>148</id>
    <timestamp>2023-08-22T14:09:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan Color upgraded the [[EEPROM|internal EEPROM]] from 128 bytes to 2 kilobytes; most of the additional space is utilized to allow for branding consoles in the form of unique, custom splash animations on console startup.  == Format ==  {| class="wikitable" |- ! Offset !! Length !! Contents |- | $83 || 1 || WSC-specific configuration. Bit 7 enables custom splash animation. |- | $84 || 1 || Name color |- | $85 || 1 || Must be $00 |- | $86 || 1 || Size; 0 = ends..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2086" xml:space="preserve">The WonderSwan Color upgraded the [[EEPROM|internal EEPROM]] from 128 bytes to 2 kilobytes; most of the additional space is utilized to allow for branding consoles in the form of unique, custom splash animations on console startup.

== Format ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $83 || 1 || WSC-specific configuration. Bit 7 enables custom splash animation.
|-
| $84 || 1 || Name color
|-
| $85 || 1 || Must be $00
|-
| $86 || 1 || Size; 0 = ends at &lt;= $3FF, 1 = ends at &lt;= $7FF
|-
| $87 || 1 || First frame
|-
| $88 || 1 || Last frame
|-
| $89 || 1 || Sprite count
|-
| $8A || 1 || Palette flags
|-
| $8B || 1 || Tile count
|-
| $8C || 2 || Palette location - $80
|-
| $8E || 2 || Tile data location - $80
|-
| $90 || 2 || Tilemap location - $80
|-
| $92 || 2 || Screen offset (Horizontal)
|-
| $94 || 2 || Screen offset (Vertical)
|-
| $96 || 1 || Tilemap width
|-
| $97 || 1 || Tilemap height
|-
| $98 || 2 || VBlank IRQ handler offset
|-
| $9A || 2 || VBlank IRQ handler segment
|-
| $9C || 1 || Owner name X (horizontal)
|-
| $9D || 1 || Owner name Y (horizontal)
|-
| $9E || 1 || Owner name X (vertical)
|-
| $9F || 1 || Owner name Y (vertical)
|-
| $A0 || 2 || Padding, unused
|-
| $A2 || 2 || Sound wavetable location - $80
|-
| $A4 || 2 || Sound channel 1 data offset - $80
|-
| $A6 || 2 || Sound channel 2 data offset - $80
|-
| $A8 || 2 || Sound channel 3 data offset - $80
|-
| $AA || 2 || Sound channel 4 data offset - $80
|-
| $AC || 10 || SwanCrystal TFT LCD configuration
|-
| $B6 || 10 || Padding, unused
|-
| $C0 || ... || Arbitrary data - palettes, tilemaps, etc.
|}

=== Palette flags ===

&lt;pre&gt;
7  bit  0
---- ----
b..p pppp
|  +-++++- Palette count (0-16)
+--------- Tile/palette bits per pixel:
             0 = 1 bit per pixel
             1 = 2 bits per pixel
&lt;/pre&gt;

=== Name colors ===

{| class="wikitable"
|-
! Value !! RGB code
|-
| 0 || #000
|-
| 1 || #f00
|-
| 2 || #f70
|-
| 3 || #ff0
|-
| 4 || #7f0
|-
| 5 || #0f0
|-
| 6 || #0f7
|-
| 7 || #0ff
|-
| 8 || #07f
|-
| 9 || #00f
|-
| 10 || #70f
|-
| 11 || #f0f
|-
| 12 || #f07
|}</text>
    <sha1>30b8c12184dda3369d503840be15e06a7967323e</sha1>
  </revision>
  <revision>
    <id>149</id>
    <parentid>148</parentid>
    <timestamp>2023-08-22T14:12:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2677" xml:space="preserve">The WonderSwan Color upgraded the [[EEPROM|internal EEPROM]] from 128 bytes to 2 kilobytes; most of the additional space is utilized to allow for branding consoles in the form of unique, custom splash animations on console startup.

== Format ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $83 || 1 || WSC-specific configuration. Bit 7 enables custom splash animation.
|-
| $84 || 1 || Name color
|-
| $85 || 1 || Must be $00
|-
| $86 || 1 || Size; 0 = ends at &lt;= $3FF, 1 = ends at &lt;= $7FF
|-
| $87 || 1 || First frame
|-
| $88 || 1 || Last frame
|-
| $89 || 1 || Sprite count
|-
| $8A || 1 || Palette flags
|-
| $8B || 1 || Tile count
|-
| $8C || 2 || Palette location - $80
|-
| $8E || 2 || Tile data location - $80
|-
| $90 || 2 || Tilemap location - $80
|-
| $92 || 2 || Screen offset (Horizontal)
|-
| $94 || 2 || Screen offset (Vertical)
|-
| $96 || 1 || Tilemap width
|-
| $97 || 1 || Tilemap height
|-
| $98 || 2 || VBlank IRQ handler offset
|-
| $9A || 2 || VBlank IRQ handler segment, must be $0600
|-
| $9C || 1 || Owner name X (horizontal)
|-
| $9D || 1 || Owner name Y (horizontal)
|-
| $9E || 1 || Owner name X (vertical)
|-
| $9F || 1 || Owner name Y (vertical)
|-
| $A0 || 2 || Padding, unused
|-
| $A2 || 2 || Sound wavetable location - $80
|-
| $A4 || 2 || Sound channel 1 data offset - $80
|-
| $A6 || 2 || Sound channel 2 data offset - $80
|-
| $A8 || 2 || Sound channel 3 data offset - $80
|-
| $AA || 2 || Sound channel 4 data offset - $80
|-
| $AC || 10 || SwanCrystal TFT LCD configuration
|-
| $B6 || 10 || Padding, unused
|-
| $C0 || ... || Arbitrary data - palettes, tilemaps, etc.
|}

=== Palette flags ===

&lt;pre&gt;
7  bit  0
---- ----
b..p pppp
|  +-++++- Palette count (0-16)
+--------- Tile/palette bits per pixel:
             0 = 1 bit per pixel
             1 = 2 bits per pixel
&lt;/pre&gt;

=== Name colors ===

{| class="wikitable"
|-
! Value !! RGB code
|-
| 0 || #000
|-
| 1 || #f00
|-
| 2 || #f70
|-
| 3 || #ff0
|-
| 4 || #7f0
|-
| 5 || #0f0
|-
| 6 || #0f7
|-
| 7 || #0ff
|-
| 8 || #07f
|-
| 9 || #00f
|-
| 10 || #70f
|-
| 11 || #f0f
|-
| 12 || #f07
|}

=== VBlank IRQ handler ===

A custom splash animation ''must'' provide a valid VBlank IRQ handler, with the following rules:

* The segment must be ''0x0600''; the offset is provided relative to ''$80'', as with other data offsets.
* The code must end with a ''retf'' opcode, or equivalent.

=== Horizontal/Vertical orientation handling ===

The splash animation loader will automatically rotate the tile data and tilemap when booting a cartridge whose [[ROM header||header]] declares vertical orientation as its startup orientation.

=== Sound channel data format ===

TODO</text>
    <sha1>1f03303a60af2978ee2f3eed1970d407b2e71cd3</sha1>
  </revision>
</page>
<page arvcontinue="20230822095816|101">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>150</id>
    <timestamp>2023-08-22T16:41:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan utilizes M93LCx6-compatible EEPROMs:  * in the SoC: ** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan, ** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color, * on cartridges: ** 1 Kbit cartridge EEPROM (M93LC46-compatible) ** 8 Kbit cartridge EEPROM (M93LC76-compatible) ** 16 Kbit cartridge EEPROM (M93LC86-compatible)  Additional variants exists which were not seen on any production cartridge:  * 2 Kbit EEPROM (M93LC56-comp..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3400" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa     (1 Kbit - M93LC46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pewr ....
            ||||
            |||+------ 1 for READ command, 0 otherwise
            ||+------- 1 for WRITE and WRAL command, 0 otherwise
            |+-------- 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>5f304b0451bf528ca115012752867f7de948eb27</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>151</id>
    <parentid>142</parentid>
    <timestamp>2023-08-22T16:43:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19288" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>7026be789c8610f73a79c4bac349bc445ec4acc6</sha1>
  </revision>
  <revision>
    <id>152</id>
    <parentid>151</parentid>
    <timestamp>2023-08-22T16:44:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19288" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | System&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| System Control 2
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| System Control 3
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! System
! $A0
| System Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>c25e07d0cb8cf63bc3ca3678ea8bffdeaf1ca2fb</sha1>
  </revision>
  <revision>
    <id>194</id>
    <parentid>152</parentid>
    <timestamp>2023-08-25T16:50:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add System/SoC links</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19363" xml:space="preserve">* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
|
| Forwarded by the SoC
|}</text>
    <sha1>fbc2c02d11c3c4a621f4e1d7a00e76e5b50cc997</sha1>
  </revision>
  <revision>
    <id>198</id>
    <parentid>194</parentid>
    <timestamp>2023-08-27T10:47:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document routing etc</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="20414" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.</text>
    <sha1>22ef1e7debbf80bc06c69b5559700a5a37bd03d9</sha1>
  </revision>
  <revision>
    <id>200</id>
    <parentid>198</parentid>
    <timestamp>2023-08-27T10:50:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="20611" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| Hyper Voice Left Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| Hyper Voice Right Output
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| Hyper Voice Left Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| Hyper Voice Right Input
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| Hyper Voice Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>16d411851b1935e4546c8d5184de2b6450a59c53</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Frame timing</title>
  <ns>0</ns>
  <id>36</id>
  <revision>
    <id>153</id>
    <timestamp>2023-08-22T18:15:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "Notes:  * Sprite indices are given negatively. Sprites are filtered for every line, and are drawn from last found to first found. * Fetches may be off by one cycle. This stuff is complicated.  {| class="wikitable" ! rowspan="2" | Cycle ! rowspan="2" | CPU ! colspan="4" | PPU ! rowspan="2" | APU ! rowspan="2" | Palette |- ! Mono/2BPP ! Color/2BPP ! Color/4BPP ! Line 144 |- | 0 | rowspan="117" style="vertical-align:top;" | V30MZ ! rowspan="256" style="text-align: center;"..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9084" xml:space="preserve">Notes:

* Sprite indices are given negatively. Sprites are filtered for every line, and are drawn from last found to first found.
* Fetches may be off by one cycle. This stuff is complicated.

{| class="wikitable"
! rowspan="2" | Cycle
! rowspan="2" | CPU
! colspan="4" | PPU
! rowspan="2" | APU
! rowspan="2" | Palette
|-
! Mono/2BPP
! Color/2BPP
! Color/4BPP
! Line 144
|-
| 0
| rowspan="117" style="vertical-align:top;" | V30MZ
! rowspan="256" style="text-align: center;" | TODO
| Fetch screen 1 cell (0, Y)
! rowspan="256" style="text-align: center;" | TODO
| rowspan="256" style="vertical-align:top;" | Sprite table DMA&lt;br/&gt;
Copy one word every cycle
| rowspan="122" style="vertical-align:top;" | 
| rowspan="224" style="vertical-align:top;" | Fetch palette for pixel (N, Y)
|-
| 1
| Fetch tile data for above
|-
| 2
| Fetch screen 1 cell (1, Y)
|-
| 3
| Fetch tile data for above
|-
| 4
| Fetch screen 1 cell (2, Y)
|-
| 5
| Fetch tile data for above
|-
| 6
| Fetch screen 1 cell (3, Y)
|-
| 7
| Fetch tile data for above
|-
| 8
| Fetch screen 1 cell (4, Y)
|-
| 9
| Fetch tile data for above
|-
| 10
| Fetch screen 1 cell (5, Y)
|-
| 11
| Fetch tile data for above
|-
| 12
| Fetch screen 1 cell (6, Y)
|-
| 13
| Fetch tile data for above
|-
| 14
| Fetch screen 1 cell (7, Y)
|-
| 15
| Fetch tile data for above
|-
| 16
| Fetch screen 1 cell (8, Y)
|-
| 17
| Fetch tile data for above
|-
| 18
| Fetch screen 1 cell (9, Y)
|-
| 19
| Fetch tile data for above
|-
| 20
| Fetch screen 1 cell (10, Y)
|-
| 21
| Fetch tile data for above
|-
| 22
| Fetch screen 1 cell (11, Y)
|-
| 23
| Fetch tile data for above
|-
| 24
| Fetch screen 1 cell (12, Y)
|-
| 25
| Fetch tile data for above
|-
| 26
| Fetch screen 1 cell (13, Y)
|-
| 27
| Fetch tile data for above
|-
| 28
| Fetch screen 1 cell (14, Y)
|-
| 29
| Fetch tile data for above
|-
| 30
| Fetch screen 1 cell (15, Y)
|-
| 31
| Fetch tile data for above
|-
| 32
| Fetch screen 1 cell (16, Y)
|-
| 33
| Fetch tile data for above
|-
| 34
| Fetch screen 1 cell (17, Y)
|-
| 35
| Fetch tile data for above
|-
| 36
| Fetch screen 1 cell (18, Y)
|-
| 37
| Fetch tile data for above
|-
| 38
| Fetch screen 1 cell (19, Y)
|-
| 39
| Fetch tile data for above
|-
| 40
| Fetch screen 1 cell (20, Y)
|-
| 41
| Fetch tile data for above
|-
| 42
| Fetch screen 1 cell (21, Y)
|-
| 43
| Fetch tile data for above
|-
| 44
| Fetch screen 1 cell (22, Y)
|-
| 45
| Fetch tile data for above
|-
| 46
| Fetch screen 1 cell (23, Y)
|-
| 47
| Fetch tile data for above
|-
| 48
| Fetch screen 1 cell (24, Y)
|-
| 49
| Fetch tile data for above
|-
| 50
| Fetch screen 1 cell (25, Y)
|-
| 51
| Fetch tile data for above
|-
| 52
| Fetch screen 1 cell (26, Y)
|-
| 53
| Fetch tile data for above
|-
| 54
| Fetch screen 1 cell (27, Y)
|-
| 55
| Fetch tile data for above
|-
| 56
| Fetch screen 1 cell (28, Y)
|-
| 57
| Fetch tile data for above
|-
| 58
| Fetch screen 1 cell (29, Y)
|-
| 59
| Fetch tile data for above
|-
| 60
| Fetch screen 1 cell (30, Y)
|-
| 61
| Fetch tile data for above
|-
| 62
| Fetch screen 1 cell (31, Y)
|-
| 63
| Fetch tile data for above
|-
| 64
| Fetch screen 1 cell (0, Y)
|-
| 65
| Fetch tile data for above
|-
| 66
| Fetch screen 2 cell (0, Y)
|-
| 67
| Fetch tile data for above
|-
| 68
| Fetch screen 2 cell (1, Y)
|-
| 69
| Fetch tile data for above
|-
| 70
| Fetch screen 2 cell (2, Y)
|-
| 71
| Fetch tile data for above
|-
| 72
| Fetch screen 2 cell (3, Y)
|-
| 73
| Fetch tile data for above
|-
| 74
| Fetch screen 2 cell (4, Y)
|-
| 75
| Fetch tile data for above
|-
| 76
| Fetch screen 2 cell (5, Y)
|-
| 77
| Fetch tile data for above
|-
| 78
| Fetch screen 2 cell (6, Y)
|-
| 79
| Fetch tile data for above
|-
| 80
| Fetch screen 2 cell (7, Y)
|-
| 81
| Fetch tile data for above
|-
| 82
| Fetch screen 2 cell (8, Y)
|-
| 83
| Fetch tile data for above
|-
| 84
| Fetch screen 2 cell (9, Y)
|-
| 85
| Fetch tile data for above
|-
| 86
| Fetch screen 2 cell (10, Y)
|-
| 87
| Fetch tile data for above
|-
| 88
| Fetch screen 2 cell (11, Y)
|-
| 89
| Fetch tile data for above
|-
| 90
| Fetch screen 2 cell (12, Y)
|-
| 91
| Fetch tile data for above
|-
| 92
| Fetch screen 2 cell (13, Y)
|-
| 93
| Fetch tile data for above
|-
| 94
| Fetch screen 2 cell (14, Y)
|-
| 95
| Fetch tile data for above
|-
| 96
| Fetch screen 2 cell (15, Y)
|-
| 97
| Fetch tile data for above
|-
| 98
| Fetch screen 2 cell (16, Y)
|-
| 99
| Fetch tile data for above
|-
| 100
| Fetch screen 2 cell (17, Y)
|-
| 101
| Fetch tile data for above
|-
| 102
| Fetch screen 2 cell (18, Y)
|-
| 103
| Fetch tile data for above
|-
| 104
| Fetch screen 2 cell (19, Y)
|-
| 105
| Fetch tile data for above
|-
| 106
| Fetch screen 2 cell (20, Y)
|-
| 107
| Fetch tile data for above
|-
| 108
| Fetch screen 2 cell (21, Y)
|-
| 109
| Fetch tile data for above
|-
| 110
| Fetch screen 2 cell (22, Y)
|-
| 111
| Fetch tile data for above
|-
| 112
| Fetch screen 2 cell (23, Y)
|-
| 113
| Fetch tile data for above
|-
| 114
| Fetch screen 2 cell (24, Y)
|-
| 115
| Fetch tile data for above
|-
| 116
| Fetch screen 2 cell (25, Y)
|-
| 117
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
| Fetch tile data for above
|-
| 118
| Fetch screen 2 cell (26, Y)
|-
| 119
| Fetch tile data for above
|-
| 120
| Fetch screen 2 cell (27, Y)
|-
| 121
| Fetch tile data for above
|-
| 122
| (SDMA) Fetch RAM byte
| Fetch screen 2 cell (28, Y)
| Reset sound output
|-
| 123
| (SDMA) Write sound port
| Fetch tile data for above
| Fetch channel 1 wavetable sample
|-
| 124
| rowspan="121" style="vertical-align:top;" | V30MZ
| Fetch screen 2 cell (29, Y)
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 125
| Fetch tile data for above
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 126
| Fetch screen 2 cell (30, Y)
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 127
| Fetch tile data for above
| Add channel 4 output
|-
| 128
| Fetch screen 2 cell (31, Y)
| rowspan="122" |
|-
| 129
| Fetch tile data for above
|-
| 130
| Fetch screen 2 cell (0, Y)
|-
| 131
| Fetch tile data for above
|-
| 132
! rowspan="26" | TODO
|-
| 133
|-
| 134
|-
| 135
|-
| 136
|-
| 137
|-
| 138
|-
| 139
|-
| 140
|-
| 141
|-
| 142
|-
| 143
|-
| 144
|-
| 145
|-
| 146
|-
| 147
|-
| 148
|-
| 149
|-
| 150
|-
| 151
|-
| 152
|-
| 153
|-
| 154
|-
| 155
|-
| 156
|-
| 157
|-
| 158
| Fetch tile data for sprite -1
|-
| 159
! TODO
|-
| 160
| Fetch tile data for sprite -2
|-
| 161
! TODO
|-
| 162
| Fetch tile data for sprite -3
|-
| 163
! rowspan="3" | TODO
|-
| 164
|-
| 165
|-
| 166
| Fetch tile data for sprite -4
|-
| 167
! TODO
|-
| 168
| Fetch tile data for sprite -5
|-
| 169
! TODO
|-
| 170
| Fetch tile data for sprite -6
|-
| 171
! rowspan="3" | TODO
|-
| 172
|-
| 173
|-
| 174
| Fetch tile data for sprite -7
|-
| 175
! TODO
|-
| 176
| Fetch tile data for sprite -8
|-
| 177
! TODO
|-
| 178
| Fetch tile data for sprite -9
|-
| 179
! rowspan="3" | TODO
|-
| 180
|-
| 181
|-
| 182
| Fetch tile data for sprite -10
|-
| 183
! TODO
|-
| 184
| Fetch tile data for sprite -11
|-
| 185
! TODO
|-
| 186
| Fetch tile data for sprite -12
|-
| 187
! rowspan="3" | TODO
|-
| 188
|-
| 189
|-
| 190
| Fetch tile data for sprite -13
|-
| 191
! TODO
|-
| 192
| Fetch tile data for sprite -14
|-
| 193
! TODO
|-
| 194
| Fetch tile data for sprite -15
|-
| 195
! rowspan="3" | TODO
|-
| 196
|-
| 197
|-
| 198
| Fetch tile data for sprite -16
|-
| 199
! TODO
|-
| 200
| Fetch tile data for sprite -17
|-
| 201
! TODO
|-
| 202
| Fetch tile data for sprite -18
|-
| 203
! rowspan="3" | TODO
|-
| 204
|-
| 205
|-
| 206
| Fetch tile data for sprite -19
|-
| 207
! TODO
|-
| 208
| Fetch tile data for sprite -20
|-
| 209
! TODO
|-
| 210
| Fetch tile data for sprite -21
|-
| 211
! rowspan="3" | TODO
|-
| 212
|-
| 213
|-
| 214
| Fetch tile data for sprite -22
|-
| 215
! TODO
|-
| 216
| Fetch tile data for sprite -23
|-
| 217
! TODO
|-
| 218
| Fetch tile data for sprite -24
|-
| 219
! rowspan="3" | TODO
|-
| 220
|-
| 221
|-
| 222
| Fetch tile data for sprite -25
|-
| 223
! TODO
|-
| 224
| Fetch tile data for sprite -26
! rowspan="32" | TODO
|-
| 225
! TODO
|-
| 226
| Fetch tile data for sprite -27
|-
| 227
! rowspan="3" | TODO
|-
| 228
|-
| 229
|-
| 230
| Fetch tile data for sprite -28
|-
| 231
! TODO
|-
| 232
| Fetch tile data for sprite -29
|-
| 233
! TODO
|-
| 234
| Fetch tile data for sprite -30
|-
| 235
! rowspan="3" | TODO
|-
| 236
|-
| 237
|-
| 238
| Fetch tile data for sprite -31
|-
| 239
! TODO
|-
| 240
| Fetch tile data for sprite -32
|-
| 241
! rowspan="15" | TODO
|-
| 242
|-
| 243
|-
| 244
|-
| 245
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
|-
| 246
|-
| 247
|-
| 248
|-
| 249
|-
| 250
| (SDMA) Fetch RAM byte
| Reset sound output
|-
| 251
| (SDMA) Write sound port
| Fetch channel 1 wavetable sample
|-
| 252
| rowspan="4" style="vertical-align:top;" | V30MZ
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 253
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 254
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 255
| Add channel 4 output
|}</text>
    <sha1>60f10a865098288e3751e3981ced65278be08257</sha1>
  </revision>
  <revision>
    <id>154</id>
    <parentid>153</parentid>
    <timestamp>2023-08-22T18:17:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9112" xml:space="preserve">Notes:

* Sprite indices are given negatively. Sprites are filtered for every line, and are drawn from last found to first found.
* Fetches may be off by one cycle. This stuff is complicated.

{| class="wikitable"
! rowspan="3" | Cycle
! colspan="7" | Quadrant
|-
! rowspan="2" | CPU
! colspan="4" | PPU
! rowspan="2" | APU
! rowspan="2" | Palette
|-
! Mono/2BPP
! Color/2BPP
! Color/4BPP
! Line 144
|-
| 0
| rowspan="117" style="vertical-align:top;" | V30MZ
! rowspan="256" style="text-align: center;" | TODO
| Fetch screen 1 cell (0, Y)
! rowspan="256" style="text-align: center;" | TODO
| rowspan="256" style="vertical-align:top;" | Sprite table DMA&lt;br/&gt;
Copy one word every cycle
| rowspan="122" style="vertical-align:top;" | 
| rowspan="224" style="vertical-align:top;" | Fetch palette for pixel (N, Y)
|-
| 1
| Fetch tile data for above
|-
| 2
| Fetch screen 1 cell (1, Y)
|-
| 3
| Fetch tile data for above
|-
| 4
| Fetch screen 1 cell (2, Y)
|-
| 5
| Fetch tile data for above
|-
| 6
| Fetch screen 1 cell (3, Y)
|-
| 7
| Fetch tile data for above
|-
| 8
| Fetch screen 1 cell (4, Y)
|-
| 9
| Fetch tile data for above
|-
| 10
| Fetch screen 1 cell (5, Y)
|-
| 11
| Fetch tile data for above
|-
| 12
| Fetch screen 1 cell (6, Y)
|-
| 13
| Fetch tile data for above
|-
| 14
| Fetch screen 1 cell (7, Y)
|-
| 15
| Fetch tile data for above
|-
| 16
| Fetch screen 1 cell (8, Y)
|-
| 17
| Fetch tile data for above
|-
| 18
| Fetch screen 1 cell (9, Y)
|-
| 19
| Fetch tile data for above
|-
| 20
| Fetch screen 1 cell (10, Y)
|-
| 21
| Fetch tile data for above
|-
| 22
| Fetch screen 1 cell (11, Y)
|-
| 23
| Fetch tile data for above
|-
| 24
| Fetch screen 1 cell (12, Y)
|-
| 25
| Fetch tile data for above
|-
| 26
| Fetch screen 1 cell (13, Y)
|-
| 27
| Fetch tile data for above
|-
| 28
| Fetch screen 1 cell (14, Y)
|-
| 29
| Fetch tile data for above
|-
| 30
| Fetch screen 1 cell (15, Y)
|-
| 31
| Fetch tile data for above
|-
| 32
| Fetch screen 1 cell (16, Y)
|-
| 33
| Fetch tile data for above
|-
| 34
| Fetch screen 1 cell (17, Y)
|-
| 35
| Fetch tile data for above
|-
| 36
| Fetch screen 1 cell (18, Y)
|-
| 37
| Fetch tile data for above
|-
| 38
| Fetch screen 1 cell (19, Y)
|-
| 39
| Fetch tile data for above
|-
| 40
| Fetch screen 1 cell (20, Y)
|-
| 41
| Fetch tile data for above
|-
| 42
| Fetch screen 1 cell (21, Y)
|-
| 43
| Fetch tile data for above
|-
| 44
| Fetch screen 1 cell (22, Y)
|-
| 45
| Fetch tile data for above
|-
| 46
| Fetch screen 1 cell (23, Y)
|-
| 47
| Fetch tile data for above
|-
| 48
| Fetch screen 1 cell (24, Y)
|-
| 49
| Fetch tile data for above
|-
| 50
| Fetch screen 1 cell (25, Y)
|-
| 51
| Fetch tile data for above
|-
| 52
| Fetch screen 1 cell (26, Y)
|-
| 53
| Fetch tile data for above
|-
| 54
| Fetch screen 1 cell (27, Y)
|-
| 55
| Fetch tile data for above
|-
| 56
| Fetch screen 1 cell (28, Y)
|-
| 57
| Fetch tile data for above
|-
| 58
| Fetch screen 1 cell (29, Y)
|-
| 59
| Fetch tile data for above
|-
| 60
| Fetch screen 1 cell (30, Y)
|-
| 61
| Fetch tile data for above
|-
| 62
| Fetch screen 1 cell (31, Y)
|-
| 63
| Fetch tile data for above
|-
| 64
| Fetch screen 1 cell (0, Y)
|-
| 65
| Fetch tile data for above
|-
| 66
| Fetch screen 2 cell (0, Y)
|-
| 67
| Fetch tile data for above
|-
| 68
| Fetch screen 2 cell (1, Y)
|-
| 69
| Fetch tile data for above
|-
| 70
| Fetch screen 2 cell (2, Y)
|-
| 71
| Fetch tile data for above
|-
| 72
| Fetch screen 2 cell (3, Y)
|-
| 73
| Fetch tile data for above
|-
| 74
| Fetch screen 2 cell (4, Y)
|-
| 75
| Fetch tile data for above
|-
| 76
| Fetch screen 2 cell (5, Y)
|-
| 77
| Fetch tile data for above
|-
| 78
| Fetch screen 2 cell (6, Y)
|-
| 79
| Fetch tile data for above
|-
| 80
| Fetch screen 2 cell (7, Y)
|-
| 81
| Fetch tile data for above
|-
| 82
| Fetch screen 2 cell (8, Y)
|-
| 83
| Fetch tile data for above
|-
| 84
| Fetch screen 2 cell (9, Y)
|-
| 85
| Fetch tile data for above
|-
| 86
| Fetch screen 2 cell (10, Y)
|-
| 87
| Fetch tile data for above
|-
| 88
| Fetch screen 2 cell (11, Y)
|-
| 89
| Fetch tile data for above
|-
| 90
| Fetch screen 2 cell (12, Y)
|-
| 91
| Fetch tile data for above
|-
| 92
| Fetch screen 2 cell (13, Y)
|-
| 93
| Fetch tile data for above
|-
| 94
| Fetch screen 2 cell (14, Y)
|-
| 95
| Fetch tile data for above
|-
| 96
| Fetch screen 2 cell (15, Y)
|-
| 97
| Fetch tile data for above
|-
| 98
| Fetch screen 2 cell (16, Y)
|-
| 99
| Fetch tile data for above
|-
| 100
| Fetch screen 2 cell (17, Y)
|-
| 101
| Fetch tile data for above
|-
| 102
| Fetch screen 2 cell (18, Y)
|-
| 103
| Fetch tile data for above
|-
| 104
| Fetch screen 2 cell (19, Y)
|-
| 105
| Fetch tile data for above
|-
| 106
| Fetch screen 2 cell (20, Y)
|-
| 107
| Fetch tile data for above
|-
| 108
| Fetch screen 2 cell (21, Y)
|-
| 109
| Fetch tile data for above
|-
| 110
| Fetch screen 2 cell (22, Y)
|-
| 111
| Fetch tile data for above
|-
| 112
| Fetch screen 2 cell (23, Y)
|-
| 113
| Fetch tile data for above
|-
| 114
| Fetch screen 2 cell (24, Y)
|-
| 115
| Fetch tile data for above
|-
| 116
| Fetch screen 2 cell (25, Y)
|-
| 117
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
| Fetch tile data for above
|-
| 118
| Fetch screen 2 cell (26, Y)
|-
| 119
| Fetch tile data for above
|-
| 120
| Fetch screen 2 cell (27, Y)
|-
| 121
| Fetch tile data for above
|-
| 122
| (SDMA) Fetch RAM byte
| Fetch screen 2 cell (28, Y)
| Reset sound output
|-
| 123
| (SDMA) Write sound port
| Fetch tile data for above
| Fetch channel 1 wavetable sample
|-
| 124
| rowspan="121" style="vertical-align:top;" | V30MZ
| Fetch screen 2 cell (29, Y)
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 125
| Fetch tile data for above
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 126
| Fetch screen 2 cell (30, Y)
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 127
| Fetch tile data for above
| Add channel 4 output
|-
| 128
| Fetch screen 2 cell (31, Y)
| rowspan="122" |
|-
| 129
| Fetch tile data for above
|-
| 130
| Fetch screen 2 cell (0, Y)
|-
| 131
| Fetch tile data for above
|-
| 132
! rowspan="26" | TODO
|-
| 133
|-
| 134
|-
| 135
|-
| 136
|-
| 137
|-
| 138
|-
| 139
|-
| 140
|-
| 141
|-
| 142
|-
| 143
|-
| 144
|-
| 145
|-
| 146
|-
| 147
|-
| 148
|-
| 149
|-
| 150
|-
| 151
|-
| 152
|-
| 153
|-
| 154
|-
| 155
|-
| 156
|-
| 157
|-
| 158
| Fetch tile data for sprite -1
|-
| 159
! TODO
|-
| 160
| Fetch tile data for sprite -2
|-
| 161
! TODO
|-
| 162
| Fetch tile data for sprite -3
|-
| 163
! rowspan="3" | TODO
|-
| 164
|-
| 165
|-
| 166
| Fetch tile data for sprite -4
|-
| 167
! TODO
|-
| 168
| Fetch tile data for sprite -5
|-
| 169
! TODO
|-
| 170
| Fetch tile data for sprite -6
|-
| 171
! rowspan="3" | TODO
|-
| 172
|-
| 173
|-
| 174
| Fetch tile data for sprite -7
|-
| 175
! TODO
|-
| 176
| Fetch tile data for sprite -8
|-
| 177
! TODO
|-
| 178
| Fetch tile data for sprite -9
|-
| 179
! rowspan="3" | TODO
|-
| 180
|-
| 181
|-
| 182
| Fetch tile data for sprite -10
|-
| 183
! TODO
|-
| 184
| Fetch tile data for sprite -11
|-
| 185
! TODO
|-
| 186
| Fetch tile data for sprite -12
|-
| 187
! rowspan="3" | TODO
|-
| 188
|-
| 189
|-
| 190
| Fetch tile data for sprite -13
|-
| 191
! TODO
|-
| 192
| Fetch tile data for sprite -14
|-
| 193
! TODO
|-
| 194
| Fetch tile data for sprite -15
|-
| 195
! rowspan="3" | TODO
|-
| 196
|-
| 197
|-
| 198
| Fetch tile data for sprite -16
|-
| 199
! TODO
|-
| 200
| Fetch tile data for sprite -17
|-
| 201
! TODO
|-
| 202
| Fetch tile data for sprite -18
|-
| 203
! rowspan="3" | TODO
|-
| 204
|-
| 205
|-
| 206
| Fetch tile data for sprite -19
|-
| 207
! TODO
|-
| 208
| Fetch tile data for sprite -20
|-
| 209
! TODO
|-
| 210
| Fetch tile data for sprite -21
|-
| 211
! rowspan="3" | TODO
|-
| 212
|-
| 213
|-
| 214
| Fetch tile data for sprite -22
|-
| 215
! TODO
|-
| 216
| Fetch tile data for sprite -23
|-
| 217
! TODO
|-
| 218
| Fetch tile data for sprite -24
|-
| 219
! rowspan="3" | TODO
|-
| 220
|-
| 221
|-
| 222
| Fetch tile data for sprite -25
|-
| 223
! TODO
|-
| 224
| Fetch tile data for sprite -26
! rowspan="32" | TODO
|-
| 225
! TODO
|-
| 226
| Fetch tile data for sprite -27
|-
| 227
! rowspan="3" | TODO
|-
| 228
|-
| 229
|-
| 230
| Fetch tile data for sprite -28
|-
| 231
! TODO
|-
| 232
| Fetch tile data for sprite -29
|-
| 233
! TODO
|-
| 234
| Fetch tile data for sprite -30
|-
| 235
! rowspan="3" | TODO
|-
| 236
|-
| 237
|-
| 238
| Fetch tile data for sprite -31
|-
| 239
! TODO
|-
| 240
| Fetch tile data for sprite -32
|-
| 241
! rowspan="15" | TODO
|-
| 242
|-
| 243
|-
| 244
|-
| 245
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
|-
| 246
|-
| 247
|-
| 248
|-
| 249
|-
| 250
| (SDMA) Fetch RAM byte
| Reset sound output
|-
| 251
| (SDMA) Write sound port
| Fetch channel 1 wavetable sample
|-
| 252
| rowspan="4" style="vertical-align:top;" | V30MZ
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 253
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 254
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 255
| Add channel 4 output
|}</text>
    <sha1>dde35f5530e1f0b38efc8cd979669c26db8de836</sha1>
  </revision>
  <revision>
    <id>155</id>
    <parentid>154</parentid>
    <timestamp>2023-08-22T18:17:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9116" xml:space="preserve">Notes:

* Sprite indices are given negatively. Sprites are filtered for every line, and are drawn from last found to first found.
* Fetches may be off by one cycle. This stuff is complicated.

{| class="wikitable"
! rowspan="3" | Cycle
! colspan="7" | Quadrant
|-
! rowspan="2" | CPU
! colspan="4" | PPU
! rowspan="2" | APU
! rowspan="2" | Palette
|-
! Mono/2BPP
! Color/2BPP
! Color/4BPP
! Line 144
|-
| 0
| rowspan="117" style="vertical-align:top;" | V30MZ
! rowspan="256" style="text-align: center;" | TODO
| Fetch screen 1 cell (0, Y)
! rowspan="256" style="text-align: center;" | TODO
| rowspan="256" style="vertical-align:top;" | Sprite table DMA&lt;br/&gt;
Copy one word every cycle
| rowspan="122" style="vertical-align:top;" | 
| rowspan="224" style="vertical-align:top;" | Fetch palette for pixel (N, Y - 1)
|-
| 1
| Fetch tile data for above
|-
| 2
| Fetch screen 1 cell (1, Y)
|-
| 3
| Fetch tile data for above
|-
| 4
| Fetch screen 1 cell (2, Y)
|-
| 5
| Fetch tile data for above
|-
| 6
| Fetch screen 1 cell (3, Y)
|-
| 7
| Fetch tile data for above
|-
| 8
| Fetch screen 1 cell (4, Y)
|-
| 9
| Fetch tile data for above
|-
| 10
| Fetch screen 1 cell (5, Y)
|-
| 11
| Fetch tile data for above
|-
| 12
| Fetch screen 1 cell (6, Y)
|-
| 13
| Fetch tile data for above
|-
| 14
| Fetch screen 1 cell (7, Y)
|-
| 15
| Fetch tile data for above
|-
| 16
| Fetch screen 1 cell (8, Y)
|-
| 17
| Fetch tile data for above
|-
| 18
| Fetch screen 1 cell (9, Y)
|-
| 19
| Fetch tile data for above
|-
| 20
| Fetch screen 1 cell (10, Y)
|-
| 21
| Fetch tile data for above
|-
| 22
| Fetch screen 1 cell (11, Y)
|-
| 23
| Fetch tile data for above
|-
| 24
| Fetch screen 1 cell (12, Y)
|-
| 25
| Fetch tile data for above
|-
| 26
| Fetch screen 1 cell (13, Y)
|-
| 27
| Fetch tile data for above
|-
| 28
| Fetch screen 1 cell (14, Y)
|-
| 29
| Fetch tile data for above
|-
| 30
| Fetch screen 1 cell (15, Y)
|-
| 31
| Fetch tile data for above
|-
| 32
| Fetch screen 1 cell (16, Y)
|-
| 33
| Fetch tile data for above
|-
| 34
| Fetch screen 1 cell (17, Y)
|-
| 35
| Fetch tile data for above
|-
| 36
| Fetch screen 1 cell (18, Y)
|-
| 37
| Fetch tile data for above
|-
| 38
| Fetch screen 1 cell (19, Y)
|-
| 39
| Fetch tile data for above
|-
| 40
| Fetch screen 1 cell (20, Y)
|-
| 41
| Fetch tile data for above
|-
| 42
| Fetch screen 1 cell (21, Y)
|-
| 43
| Fetch tile data for above
|-
| 44
| Fetch screen 1 cell (22, Y)
|-
| 45
| Fetch tile data for above
|-
| 46
| Fetch screen 1 cell (23, Y)
|-
| 47
| Fetch tile data for above
|-
| 48
| Fetch screen 1 cell (24, Y)
|-
| 49
| Fetch tile data for above
|-
| 50
| Fetch screen 1 cell (25, Y)
|-
| 51
| Fetch tile data for above
|-
| 52
| Fetch screen 1 cell (26, Y)
|-
| 53
| Fetch tile data for above
|-
| 54
| Fetch screen 1 cell (27, Y)
|-
| 55
| Fetch tile data for above
|-
| 56
| Fetch screen 1 cell (28, Y)
|-
| 57
| Fetch tile data for above
|-
| 58
| Fetch screen 1 cell (29, Y)
|-
| 59
| Fetch tile data for above
|-
| 60
| Fetch screen 1 cell (30, Y)
|-
| 61
| Fetch tile data for above
|-
| 62
| Fetch screen 1 cell (31, Y)
|-
| 63
| Fetch tile data for above
|-
| 64
| Fetch screen 1 cell (0, Y)
|-
| 65
| Fetch tile data for above
|-
| 66
| Fetch screen 2 cell (0, Y)
|-
| 67
| Fetch tile data for above
|-
| 68
| Fetch screen 2 cell (1, Y)
|-
| 69
| Fetch tile data for above
|-
| 70
| Fetch screen 2 cell (2, Y)
|-
| 71
| Fetch tile data for above
|-
| 72
| Fetch screen 2 cell (3, Y)
|-
| 73
| Fetch tile data for above
|-
| 74
| Fetch screen 2 cell (4, Y)
|-
| 75
| Fetch tile data for above
|-
| 76
| Fetch screen 2 cell (5, Y)
|-
| 77
| Fetch tile data for above
|-
| 78
| Fetch screen 2 cell (6, Y)
|-
| 79
| Fetch tile data for above
|-
| 80
| Fetch screen 2 cell (7, Y)
|-
| 81
| Fetch tile data for above
|-
| 82
| Fetch screen 2 cell (8, Y)
|-
| 83
| Fetch tile data for above
|-
| 84
| Fetch screen 2 cell (9, Y)
|-
| 85
| Fetch tile data for above
|-
| 86
| Fetch screen 2 cell (10, Y)
|-
| 87
| Fetch tile data for above
|-
| 88
| Fetch screen 2 cell (11, Y)
|-
| 89
| Fetch tile data for above
|-
| 90
| Fetch screen 2 cell (12, Y)
|-
| 91
| Fetch tile data for above
|-
| 92
| Fetch screen 2 cell (13, Y)
|-
| 93
| Fetch tile data for above
|-
| 94
| Fetch screen 2 cell (14, Y)
|-
| 95
| Fetch tile data for above
|-
| 96
| Fetch screen 2 cell (15, Y)
|-
| 97
| Fetch tile data for above
|-
| 98
| Fetch screen 2 cell (16, Y)
|-
| 99
| Fetch tile data for above
|-
| 100
| Fetch screen 2 cell (17, Y)
|-
| 101
| Fetch tile data for above
|-
| 102
| Fetch screen 2 cell (18, Y)
|-
| 103
| Fetch tile data for above
|-
| 104
| Fetch screen 2 cell (19, Y)
|-
| 105
| Fetch tile data for above
|-
| 106
| Fetch screen 2 cell (20, Y)
|-
| 107
| Fetch tile data for above
|-
| 108
| Fetch screen 2 cell (21, Y)
|-
| 109
| Fetch tile data for above
|-
| 110
| Fetch screen 2 cell (22, Y)
|-
| 111
| Fetch tile data for above
|-
| 112
| Fetch screen 2 cell (23, Y)
|-
| 113
| Fetch tile data for above
|-
| 114
| Fetch screen 2 cell (24, Y)
|-
| 115
| Fetch tile data for above
|-
| 116
| Fetch screen 2 cell (25, Y)
|-
| 117
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
| Fetch tile data for above
|-
| 118
| Fetch screen 2 cell (26, Y)
|-
| 119
| Fetch tile data for above
|-
| 120
| Fetch screen 2 cell (27, Y)
|-
| 121
| Fetch tile data for above
|-
| 122
| (SDMA) Fetch RAM byte
| Fetch screen 2 cell (28, Y)
| Reset sound output
|-
| 123
| (SDMA) Write sound port
| Fetch tile data for above
| Fetch channel 1 wavetable sample
|-
| 124
| rowspan="121" style="vertical-align:top;" | V30MZ
| Fetch screen 2 cell (29, Y)
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 125
| Fetch tile data for above
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 126
| Fetch screen 2 cell (30, Y)
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 127
| Fetch tile data for above
| Add channel 4 output
|-
| 128
| Fetch screen 2 cell (31, Y)
| rowspan="122" |
|-
| 129
| Fetch tile data for above
|-
| 130
| Fetch screen 2 cell (0, Y)
|-
| 131
| Fetch tile data for above
|-
| 132
! rowspan="26" | TODO
|-
| 133
|-
| 134
|-
| 135
|-
| 136
|-
| 137
|-
| 138
|-
| 139
|-
| 140
|-
| 141
|-
| 142
|-
| 143
|-
| 144
|-
| 145
|-
| 146
|-
| 147
|-
| 148
|-
| 149
|-
| 150
|-
| 151
|-
| 152
|-
| 153
|-
| 154
|-
| 155
|-
| 156
|-
| 157
|-
| 158
| Fetch tile data for sprite -1
|-
| 159
! TODO
|-
| 160
| Fetch tile data for sprite -2
|-
| 161
! TODO
|-
| 162
| Fetch tile data for sprite -3
|-
| 163
! rowspan="3" | TODO
|-
| 164
|-
| 165
|-
| 166
| Fetch tile data for sprite -4
|-
| 167
! TODO
|-
| 168
| Fetch tile data for sprite -5
|-
| 169
! TODO
|-
| 170
| Fetch tile data for sprite -6
|-
| 171
! rowspan="3" | TODO
|-
| 172
|-
| 173
|-
| 174
| Fetch tile data for sprite -7
|-
| 175
! TODO
|-
| 176
| Fetch tile data for sprite -8
|-
| 177
! TODO
|-
| 178
| Fetch tile data for sprite -9
|-
| 179
! rowspan="3" | TODO
|-
| 180
|-
| 181
|-
| 182
| Fetch tile data for sprite -10
|-
| 183
! TODO
|-
| 184
| Fetch tile data for sprite -11
|-
| 185
! TODO
|-
| 186
| Fetch tile data for sprite -12
|-
| 187
! rowspan="3" | TODO
|-
| 188
|-
| 189
|-
| 190
| Fetch tile data for sprite -13
|-
| 191
! TODO
|-
| 192
| Fetch tile data for sprite -14
|-
| 193
! TODO
|-
| 194
| Fetch tile data for sprite -15
|-
| 195
! rowspan="3" | TODO
|-
| 196
|-
| 197
|-
| 198
| Fetch tile data for sprite -16
|-
| 199
! TODO
|-
| 200
| Fetch tile data for sprite -17
|-
| 201
! TODO
|-
| 202
| Fetch tile data for sprite -18
|-
| 203
! rowspan="3" | TODO
|-
| 204
|-
| 205
|-
| 206
| Fetch tile data for sprite -19
|-
| 207
! TODO
|-
| 208
| Fetch tile data for sprite -20
|-
| 209
! TODO
|-
| 210
| Fetch tile data for sprite -21
|-
| 211
! rowspan="3" | TODO
|-
| 212
|-
| 213
|-
| 214
| Fetch tile data for sprite -22
|-
| 215
! TODO
|-
| 216
| Fetch tile data for sprite -23
|-
| 217
! TODO
|-
| 218
| Fetch tile data for sprite -24
|-
| 219
! rowspan="3" | TODO
|-
| 220
|-
| 221
|-
| 222
| Fetch tile data for sprite -25
|-
| 223
! TODO
|-
| 224
| Fetch tile data for sprite -26
! rowspan="32" | TODO
|-
| 225
! TODO
|-
| 226
| Fetch tile data for sprite -27
|-
| 227
! rowspan="3" | TODO
|-
| 228
|-
| 229
|-
| 230
| Fetch tile data for sprite -28
|-
| 231
! TODO
|-
| 232
| Fetch tile data for sprite -29
|-
| 233
! TODO
|-
| 234
| Fetch tile data for sprite -30
|-
| 235
! rowspan="3" | TODO
|-
| 236
|-
| 237
|-
| 238
| Fetch tile data for sprite -31
|-
| 239
! TODO
|-
| 240
| Fetch tile data for sprite -32
|-
| 241
! rowspan="15" | TODO
|-
| 242
|-
| 243
|-
| 244
|-
| 245
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
|-
| 246
|-
| 247
|-
| 248
|-
| 249
|-
| 250
| (SDMA) Fetch RAM byte
| Reset sound output
|-
| 251
| (SDMA) Write sound port
| Fetch channel 1 wavetable sample
|-
| 252
| rowspan="4" style="vertical-align:top;" | V30MZ
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 253
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 254
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 255
| Add channel 4 output
|}</text>
    <sha1>0a13eb77ee228532c22ac14fa7fedbc6ebb00c37</sha1>
  </revision>
  <revision>
    <id>157</id>
    <parentid>155</parentid>
    <timestamp>2023-08-22T18:21:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9122" xml:space="preserve">Notes:

* Sprite indices are given negatively. Sprites are filtered for every line, and are drawn from last found to first found.
* Fetches may be off by one cycle. This stuff is complicated.

{| class="wikitable"
! rowspan="3" | Cycle
! colspan="7" | Quadrant
|-
! rowspan="2" | CPU
! colspan="4" | Display
! rowspan="2" | Sound
! rowspan="2" | Palette
|-
! Mono/2BPP
! Color/2BPP
! Color/4BPP
! Line 144
|-
| 0
| rowspan="117" style="vertical-align:top;" | V30MZ
! rowspan="256" style="text-align: center;" | TODO
| Fetch screen 1 cell (0, Y)
! rowspan="256" style="text-align: center;" | TODO
| rowspan="256" style="vertical-align:top;" | Sprite table DMA&lt;br/&gt;
Copy one word every cycle
| rowspan="122" style="vertical-align:top;" | 
| rowspan="224" style="vertical-align:top;" | Fetch palette for pixel (N, Y - 1)
|-
| 1
| Fetch tile data for above
|-
| 2
| Fetch screen 1 cell (1, Y)
|-
| 3
| Fetch tile data for above
|-
| 4
| Fetch screen 1 cell (2, Y)
|-
| 5
| Fetch tile data for above
|-
| 6
| Fetch screen 1 cell (3, Y)
|-
| 7
| Fetch tile data for above
|-
| 8
| Fetch screen 1 cell (4, Y)
|-
| 9
| Fetch tile data for above
|-
| 10
| Fetch screen 1 cell (5, Y)
|-
| 11
| Fetch tile data for above
|-
| 12
| Fetch screen 1 cell (6, Y)
|-
| 13
| Fetch tile data for above
|-
| 14
| Fetch screen 1 cell (7, Y)
|-
| 15
| Fetch tile data for above
|-
| 16
| Fetch screen 1 cell (8, Y)
|-
| 17
| Fetch tile data for above
|-
| 18
| Fetch screen 1 cell (9, Y)
|-
| 19
| Fetch tile data for above
|-
| 20
| Fetch screen 1 cell (10, Y)
|-
| 21
| Fetch tile data for above
|-
| 22
| Fetch screen 1 cell (11, Y)
|-
| 23
| Fetch tile data for above
|-
| 24
| Fetch screen 1 cell (12, Y)
|-
| 25
| Fetch tile data for above
|-
| 26
| Fetch screen 1 cell (13, Y)
|-
| 27
| Fetch tile data for above
|-
| 28
| Fetch screen 1 cell (14, Y)
|-
| 29
| Fetch tile data for above
|-
| 30
| Fetch screen 1 cell (15, Y)
|-
| 31
| Fetch tile data for above
|-
| 32
| Fetch screen 1 cell (16, Y)
|-
| 33
| Fetch tile data for above
|-
| 34
| Fetch screen 1 cell (17, Y)
|-
| 35
| Fetch tile data for above
|-
| 36
| Fetch screen 1 cell (18, Y)
|-
| 37
| Fetch tile data for above
|-
| 38
| Fetch screen 1 cell (19, Y)
|-
| 39
| Fetch tile data for above
|-
| 40
| Fetch screen 1 cell (20, Y)
|-
| 41
| Fetch tile data for above
|-
| 42
| Fetch screen 1 cell (21, Y)
|-
| 43
| Fetch tile data for above
|-
| 44
| Fetch screen 1 cell (22, Y)
|-
| 45
| Fetch tile data for above
|-
| 46
| Fetch screen 1 cell (23, Y)
|-
| 47
| Fetch tile data for above
|-
| 48
| Fetch screen 1 cell (24, Y)
|-
| 49
| Fetch tile data for above
|-
| 50
| Fetch screen 1 cell (25, Y)
|-
| 51
| Fetch tile data for above
|-
| 52
| Fetch screen 1 cell (26, Y)
|-
| 53
| Fetch tile data for above
|-
| 54
| Fetch screen 1 cell (27, Y)
|-
| 55
| Fetch tile data for above
|-
| 56
| Fetch screen 1 cell (28, Y)
|-
| 57
| Fetch tile data for above
|-
| 58
| Fetch screen 1 cell (29, Y)
|-
| 59
| Fetch tile data for above
|-
| 60
| Fetch screen 1 cell (30, Y)
|-
| 61
| Fetch tile data for above
|-
| 62
| Fetch screen 1 cell (31, Y)
|-
| 63
| Fetch tile data for above
|-
| 64
| Fetch screen 1 cell (0, Y)
|-
| 65
| Fetch tile data for above
|-
| 66
| Fetch screen 2 cell (0, Y)
|-
| 67
| Fetch tile data for above
|-
| 68
| Fetch screen 2 cell (1, Y)
|-
| 69
| Fetch tile data for above
|-
| 70
| Fetch screen 2 cell (2, Y)
|-
| 71
| Fetch tile data for above
|-
| 72
| Fetch screen 2 cell (3, Y)
|-
| 73
| Fetch tile data for above
|-
| 74
| Fetch screen 2 cell (4, Y)
|-
| 75
| Fetch tile data for above
|-
| 76
| Fetch screen 2 cell (5, Y)
|-
| 77
| Fetch tile data for above
|-
| 78
| Fetch screen 2 cell (6, Y)
|-
| 79
| Fetch tile data for above
|-
| 80
| Fetch screen 2 cell (7, Y)
|-
| 81
| Fetch tile data for above
|-
| 82
| Fetch screen 2 cell (8, Y)
|-
| 83
| Fetch tile data for above
|-
| 84
| Fetch screen 2 cell (9, Y)
|-
| 85
| Fetch tile data for above
|-
| 86
| Fetch screen 2 cell (10, Y)
|-
| 87
| Fetch tile data for above
|-
| 88
| Fetch screen 2 cell (11, Y)
|-
| 89
| Fetch tile data for above
|-
| 90
| Fetch screen 2 cell (12, Y)
|-
| 91
| Fetch tile data for above
|-
| 92
| Fetch screen 2 cell (13, Y)
|-
| 93
| Fetch tile data for above
|-
| 94
| Fetch screen 2 cell (14, Y)
|-
| 95
| Fetch tile data for above
|-
| 96
| Fetch screen 2 cell (15, Y)
|-
| 97
| Fetch tile data for above
|-
| 98
| Fetch screen 2 cell (16, Y)
|-
| 99
| Fetch tile data for above
|-
| 100
| Fetch screen 2 cell (17, Y)
|-
| 101
| Fetch tile data for above
|-
| 102
| Fetch screen 2 cell (18, Y)
|-
| 103
| Fetch tile data for above
|-
| 104
| Fetch screen 2 cell (19, Y)
|-
| 105
| Fetch tile data for above
|-
| 106
| Fetch screen 2 cell (20, Y)
|-
| 107
| Fetch tile data for above
|-
| 108
| Fetch screen 2 cell (21, Y)
|-
| 109
| Fetch tile data for above
|-
| 110
| Fetch screen 2 cell (22, Y)
|-
| 111
| Fetch tile data for above
|-
| 112
| Fetch screen 2 cell (23, Y)
|-
| 113
| Fetch tile data for above
|-
| 114
| Fetch screen 2 cell (24, Y)
|-
| 115
| Fetch tile data for above
|-
| 116
| Fetch screen 2 cell (25, Y)
|-
| 117
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
| Fetch tile data for above
|-
| 118
| Fetch screen 2 cell (26, Y)
|-
| 119
| Fetch tile data for above
|-
| 120
| Fetch screen 2 cell (27, Y)
|-
| 121
| Fetch tile data for above
|-
| 122
| (SDMA) Fetch RAM byte
| Fetch screen 2 cell (28, Y)
| Reset sound output
|-
| 123
| (SDMA) Write sound port
| Fetch tile data for above
| Fetch channel 1 wavetable sample
|-
| 124
| rowspan="121" style="vertical-align:top;" | V30MZ
| Fetch screen 2 cell (29, Y)
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 125
| Fetch tile data for above
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 126
| Fetch screen 2 cell (30, Y)
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 127
| Fetch tile data for above
| Add channel 4 output
|-
| 128
| Fetch screen 2 cell (31, Y)
| rowspan="122" |
|-
| 129
| Fetch tile data for above
|-
| 130
| Fetch screen 2 cell (0, Y)
|-
| 131
| Fetch tile data for above
|-
| 132
! rowspan="26" | TODO
|-
| 133
|-
| 134
|-
| 135
|-
| 136
|-
| 137
|-
| 138
|-
| 139
|-
| 140
|-
| 141
|-
| 142
|-
| 143
|-
| 144
|-
| 145
|-
| 146
|-
| 147
|-
| 148
|-
| 149
|-
| 150
|-
| 151
|-
| 152
|-
| 153
|-
| 154
|-
| 155
|-
| 156
|-
| 157
|-
| 158
| Fetch tile data for sprite -1
|-
| 159
! TODO
|-
| 160
| Fetch tile data for sprite -2
|-
| 161
! TODO
|-
| 162
| Fetch tile data for sprite -3
|-
| 163
! rowspan="3" | TODO
|-
| 164
|-
| 165
|-
| 166
| Fetch tile data for sprite -4
|-
| 167
! TODO
|-
| 168
| Fetch tile data for sprite -5
|-
| 169
! TODO
|-
| 170
| Fetch tile data for sprite -6
|-
| 171
! rowspan="3" | TODO
|-
| 172
|-
| 173
|-
| 174
| Fetch tile data for sprite -7
|-
| 175
! TODO
|-
| 176
| Fetch tile data for sprite -8
|-
| 177
! TODO
|-
| 178
| Fetch tile data for sprite -9
|-
| 179
! rowspan="3" | TODO
|-
| 180
|-
| 181
|-
| 182
| Fetch tile data for sprite -10
|-
| 183
! TODO
|-
| 184
| Fetch tile data for sprite -11
|-
| 185
! TODO
|-
| 186
| Fetch tile data for sprite -12
|-
| 187
! rowspan="3" | TODO
|-
| 188
|-
| 189
|-
| 190
| Fetch tile data for sprite -13
|-
| 191
! TODO
|-
| 192
| Fetch tile data for sprite -14
|-
| 193
! TODO
|-
| 194
| Fetch tile data for sprite -15
|-
| 195
! rowspan="3" | TODO
|-
| 196
|-
| 197
|-
| 198
| Fetch tile data for sprite -16
|-
| 199
! TODO
|-
| 200
| Fetch tile data for sprite -17
|-
| 201
! TODO
|-
| 202
| Fetch tile data for sprite -18
|-
| 203
! rowspan="3" | TODO
|-
| 204
|-
| 205
|-
| 206
| Fetch tile data for sprite -19
|-
| 207
! TODO
|-
| 208
| Fetch tile data for sprite -20
|-
| 209
! TODO
|-
| 210
| Fetch tile data for sprite -21
|-
| 211
! rowspan="3" | TODO
|-
| 212
|-
| 213
|-
| 214
| Fetch tile data for sprite -22
|-
| 215
! TODO
|-
| 216
| Fetch tile data for sprite -23
|-
| 217
! TODO
|-
| 218
| Fetch tile data for sprite -24
|-
| 219
! rowspan="3" | TODO
|-
| 220
|-
| 221
|-
| 222
| Fetch tile data for sprite -25
|-
| 223
! TODO
|-
| 224
| Fetch tile data for sprite -26
! rowspan="32" | TODO
|-
| 225
! TODO
|-
| 226
| Fetch tile data for sprite -27
|-
| 227
! rowspan="3" | TODO
|-
| 228
|-
| 229
|-
| 230
| Fetch tile data for sprite -28
|-
| 231
! TODO
|-
| 232
| Fetch tile data for sprite -29
|-
| 233
! TODO
|-
| 234
| Fetch tile data for sprite -30
|-
| 235
! rowspan="3" | TODO
|-
| 236
|-
| 237
|-
| 238
| Fetch tile data for sprite -31
|-
| 239
! TODO
|-
| 240
| Fetch tile data for sprite -32
|-
| 241
! rowspan="15" | TODO
|-
| 242
|-
| 243
|-
| 244
|-
| 245
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
|-
| 246
|-
| 247
|-
| 248
|-
| 249
|-
| 250
| (SDMA) Fetch RAM byte
| Reset sound output
|-
| 251
| (SDMA) Write sound port
| Fetch channel 1 wavetable sample
|-
| 252
| rowspan="4" style="vertical-align:top;" | V30MZ
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 253
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 254
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 255
| Add channel 4 output
|}</text>
    <sha1>70508b43a2892aaafad4b97ea9a81617598518fc</sha1>
  </revision>
  <revision>
    <id>158</id>
    <parentid>157</parentid>
    <timestamp>2023-08-22T18:25:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9141" xml:space="preserve">== Line timing ==

Notes:

* Sprite indices are given negatively. Sprites are filtered for every line, and are drawn from last found to first found.
* Fetches may be off by one cycle. This stuff is complicated.

{| class="wikitable"
! rowspan="3" | Cycle
! colspan="7" | Quadrant
|-
! rowspan="2" | CPU
! colspan="4" | Display
! rowspan="2" | Sound
! rowspan="2" | Palette
|-
! Mono/2BPP
! Color/2BPP
! Color/4BPP
! Line 144
|-
| 0
| rowspan="117" style="vertical-align:top;" | V30MZ
! rowspan="256" style="text-align: center;" | TODO
| Fetch screen 1 cell (0, Y)
! rowspan="256" style="text-align: center;" | TODO
| rowspan="256" style="vertical-align:top;" | Sprite table DMA&lt;br/&gt;
Copy one word every cycle
| rowspan="122" style="vertical-align:top;" | 
| rowspan="224" style="vertical-align:top;" | Fetch palette for pixel (N, Y - 1)
|-
| 1
| Fetch tile data for above
|-
| 2
| Fetch screen 1 cell (1, Y)
|-
| 3
| Fetch tile data for above
|-
| 4
| Fetch screen 1 cell (2, Y)
|-
| 5
| Fetch tile data for above
|-
| 6
| Fetch screen 1 cell (3, Y)
|-
| 7
| Fetch tile data for above
|-
| 8
| Fetch screen 1 cell (4, Y)
|-
| 9
| Fetch tile data for above
|-
| 10
| Fetch screen 1 cell (5, Y)
|-
| 11
| Fetch tile data for above
|-
| 12
| Fetch screen 1 cell (6, Y)
|-
| 13
| Fetch tile data for above
|-
| 14
| Fetch screen 1 cell (7, Y)
|-
| 15
| Fetch tile data for above
|-
| 16
| Fetch screen 1 cell (8, Y)
|-
| 17
| Fetch tile data for above
|-
| 18
| Fetch screen 1 cell (9, Y)
|-
| 19
| Fetch tile data for above
|-
| 20
| Fetch screen 1 cell (10, Y)
|-
| 21
| Fetch tile data for above
|-
| 22
| Fetch screen 1 cell (11, Y)
|-
| 23
| Fetch tile data for above
|-
| 24
| Fetch screen 1 cell (12, Y)
|-
| 25
| Fetch tile data for above
|-
| 26
| Fetch screen 1 cell (13, Y)
|-
| 27
| Fetch tile data for above
|-
| 28
| Fetch screen 1 cell (14, Y)
|-
| 29
| Fetch tile data for above
|-
| 30
| Fetch screen 1 cell (15, Y)
|-
| 31
| Fetch tile data for above
|-
| 32
| Fetch screen 1 cell (16, Y)
|-
| 33
| Fetch tile data for above
|-
| 34
| Fetch screen 1 cell (17, Y)
|-
| 35
| Fetch tile data for above
|-
| 36
| Fetch screen 1 cell (18, Y)
|-
| 37
| Fetch tile data for above
|-
| 38
| Fetch screen 1 cell (19, Y)
|-
| 39
| Fetch tile data for above
|-
| 40
| Fetch screen 1 cell (20, Y)
|-
| 41
| Fetch tile data for above
|-
| 42
| Fetch screen 1 cell (21, Y)
|-
| 43
| Fetch tile data for above
|-
| 44
| Fetch screen 1 cell (22, Y)
|-
| 45
| Fetch tile data for above
|-
| 46
| Fetch screen 1 cell (23, Y)
|-
| 47
| Fetch tile data for above
|-
| 48
| Fetch screen 1 cell (24, Y)
|-
| 49
| Fetch tile data for above
|-
| 50
| Fetch screen 1 cell (25, Y)
|-
| 51
| Fetch tile data for above
|-
| 52
| Fetch screen 1 cell (26, Y)
|-
| 53
| Fetch tile data for above
|-
| 54
| Fetch screen 1 cell (27, Y)
|-
| 55
| Fetch tile data for above
|-
| 56
| Fetch screen 1 cell (28, Y)
|-
| 57
| Fetch tile data for above
|-
| 58
| Fetch screen 1 cell (29, Y)
|-
| 59
| Fetch tile data for above
|-
| 60
| Fetch screen 1 cell (30, Y)
|-
| 61
| Fetch tile data for above
|-
| 62
| Fetch screen 1 cell (31, Y)
|-
| 63
| Fetch tile data for above
|-
| 64
| Fetch screen 1 cell (0, Y)
|-
| 65
| Fetch tile data for above
|-
| 66
| Fetch screen 2 cell (0, Y)
|-
| 67
| Fetch tile data for above
|-
| 68
| Fetch screen 2 cell (1, Y)
|-
| 69
| Fetch tile data for above
|-
| 70
| Fetch screen 2 cell (2, Y)
|-
| 71
| Fetch tile data for above
|-
| 72
| Fetch screen 2 cell (3, Y)
|-
| 73
| Fetch tile data for above
|-
| 74
| Fetch screen 2 cell (4, Y)
|-
| 75
| Fetch tile data for above
|-
| 76
| Fetch screen 2 cell (5, Y)
|-
| 77
| Fetch tile data for above
|-
| 78
| Fetch screen 2 cell (6, Y)
|-
| 79
| Fetch tile data for above
|-
| 80
| Fetch screen 2 cell (7, Y)
|-
| 81
| Fetch tile data for above
|-
| 82
| Fetch screen 2 cell (8, Y)
|-
| 83
| Fetch tile data for above
|-
| 84
| Fetch screen 2 cell (9, Y)
|-
| 85
| Fetch tile data for above
|-
| 86
| Fetch screen 2 cell (10, Y)
|-
| 87
| Fetch tile data for above
|-
| 88
| Fetch screen 2 cell (11, Y)
|-
| 89
| Fetch tile data for above
|-
| 90
| Fetch screen 2 cell (12, Y)
|-
| 91
| Fetch tile data for above
|-
| 92
| Fetch screen 2 cell (13, Y)
|-
| 93
| Fetch tile data for above
|-
| 94
| Fetch screen 2 cell (14, Y)
|-
| 95
| Fetch tile data for above
|-
| 96
| Fetch screen 2 cell (15, Y)
|-
| 97
| Fetch tile data for above
|-
| 98
| Fetch screen 2 cell (16, Y)
|-
| 99
| Fetch tile data for above
|-
| 100
| Fetch screen 2 cell (17, Y)
|-
| 101
| Fetch tile data for above
|-
| 102
| Fetch screen 2 cell (18, Y)
|-
| 103
| Fetch tile data for above
|-
| 104
| Fetch screen 2 cell (19, Y)
|-
| 105
| Fetch tile data for above
|-
| 106
| Fetch screen 2 cell (20, Y)
|-
| 107
| Fetch tile data for above
|-
| 108
| Fetch screen 2 cell (21, Y)
|-
| 109
| Fetch tile data for above
|-
| 110
| Fetch screen 2 cell (22, Y)
|-
| 111
| Fetch tile data for above
|-
| 112
| Fetch screen 2 cell (23, Y)
|-
| 113
| Fetch tile data for above
|-
| 114
| Fetch screen 2 cell (24, Y)
|-
| 115
| Fetch tile data for above
|-
| 116
| Fetch screen 2 cell (25, Y)
|-
| 117
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
| Fetch tile data for above
|-
| 118
| Fetch screen 2 cell (26, Y)
|-
| 119
| Fetch tile data for above
|-
| 120
| Fetch screen 2 cell (27, Y)
|-
| 121
| Fetch tile data for above
|-
| 122
| (SDMA) Fetch RAM byte
| Fetch screen 2 cell (28, Y)
| Reset sound output
|-
| 123
| (SDMA) Write sound port
| Fetch tile data for above
| Fetch channel 1 wavetable sample
|-
| 124
| rowspan="121" style="vertical-align:top;" | V30MZ
| Fetch screen 2 cell (29, Y)
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 125
| Fetch tile data for above
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 126
| Fetch screen 2 cell (30, Y)
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 127
| Fetch tile data for above
| Add channel 4 output
|-
| 128
| Fetch screen 2 cell (31, Y)
| rowspan="122" |
|-
| 129
| Fetch tile data for above
|-
| 130
| Fetch screen 2 cell (0, Y)
|-
| 131
| Fetch tile data for above
|-
| 132
! rowspan="26" | TODO
|-
| 133
|-
| 134
|-
| 135
|-
| 136
|-
| 137
|-
| 138
|-
| 139
|-
| 140
|-
| 141
|-
| 142
|-
| 143
|-
| 144
|-
| 145
|-
| 146
|-
| 147
|-
| 148
|-
| 149
|-
| 150
|-
| 151
|-
| 152
|-
| 153
|-
| 154
|-
| 155
|-
| 156
|-
| 157
|-
| 158
| Fetch tile data for sprite -1
|-
| 159
! TODO
|-
| 160
| Fetch tile data for sprite -2
|-
| 161
! TODO
|-
| 162
| Fetch tile data for sprite -3
|-
| 163
! rowspan="3" | TODO
|-
| 164
|-
| 165
|-
| 166
| Fetch tile data for sprite -4
|-
| 167
! TODO
|-
| 168
| Fetch tile data for sprite -5
|-
| 169
! TODO
|-
| 170
| Fetch tile data for sprite -6
|-
| 171
! rowspan="3" | TODO
|-
| 172
|-
| 173
|-
| 174
| Fetch tile data for sprite -7
|-
| 175
! TODO
|-
| 176
| Fetch tile data for sprite -8
|-
| 177
! TODO
|-
| 178
| Fetch tile data for sprite -9
|-
| 179
! rowspan="3" | TODO
|-
| 180
|-
| 181
|-
| 182
| Fetch tile data for sprite -10
|-
| 183
! TODO
|-
| 184
| Fetch tile data for sprite -11
|-
| 185
! TODO
|-
| 186
| Fetch tile data for sprite -12
|-
| 187
! rowspan="3" | TODO
|-
| 188
|-
| 189
|-
| 190
| Fetch tile data for sprite -13
|-
| 191
! TODO
|-
| 192
| Fetch tile data for sprite -14
|-
| 193
! TODO
|-
| 194
| Fetch tile data for sprite -15
|-
| 195
! rowspan="3" | TODO
|-
| 196
|-
| 197
|-
| 198
| Fetch tile data for sprite -16
|-
| 199
! TODO
|-
| 200
| Fetch tile data for sprite -17
|-
| 201
! TODO
|-
| 202
| Fetch tile data for sprite -18
|-
| 203
! rowspan="3" | TODO
|-
| 204
|-
| 205
|-
| 206
| Fetch tile data for sprite -19
|-
| 207
! TODO
|-
| 208
| Fetch tile data for sprite -20
|-
| 209
! TODO
|-
| 210
| Fetch tile data for sprite -21
|-
| 211
! rowspan="3" | TODO
|-
| 212
|-
| 213
|-
| 214
| Fetch tile data for sprite -22
|-
| 215
! TODO
|-
| 216
| Fetch tile data for sprite -23
|-
| 217
! TODO
|-
| 218
| Fetch tile data for sprite -24
|-
| 219
! rowspan="3" | TODO
|-
| 220
|-
| 221
|-
| 222
| Fetch tile data for sprite -25
|-
| 223
! TODO
|-
| 224
| Fetch tile data for sprite -26
! rowspan="32" | TODO
|-
| 225
! TODO
|-
| 226
| Fetch tile data for sprite -27
|-
| 227
! rowspan="3" | TODO
|-
| 228
|-
| 229
|-
| 230
| Fetch tile data for sprite -28
|-
| 231
! TODO
|-
| 232
| Fetch tile data for sprite -29
|-
| 233
! TODO
|-
| 234
| Fetch tile data for sprite -30
|-
| 235
! rowspan="3" | TODO
|-
| 236
|-
| 237
|-
| 238
| Fetch tile data for sprite -31
|-
| 239
! TODO
|-
| 240
| Fetch tile data for sprite -32
|-
| 241
! rowspan="15" | TODO
|-
| 242
|-
| 243
|-
| 244
|-
| 245
| rowspan="5" style="vertical-align:top;" | (SDMA) Initialize
|-
| 246
|-
| 247
|-
| 248
|-
| 249
|-
| 250
| (SDMA) Fetch RAM byte
| Reset sound output
|-
| 251
| (SDMA) Write sound port
| Fetch channel 1 wavetable sample
|-
| 252
| rowspan="4" style="vertical-align:top;" | V30MZ
| Fetch channel 2 wavetable sample&lt;br/&gt;
Add channel 1 output
|-
| 253
| Fetch channel 3 wavetable sample&lt;br/&gt;
Add channel 2 output
|-
| 254
| Fetch channel 4 wavetable sample&lt;br/&gt;
Add channel 3 output
|-
| 255
| Add channel 4 output
|}</text>
    <sha1>c1951496d14387bde92fcf7868cf8fe0502ca2fd</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Timing</title>
  <ns>0</ns>
  <id>7</id>
  <revision>
    <id>156</id>
    <parentid>140</parentid>
    <timestamp>2023-08-22T18:20:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1308" xml:space="preserve">== Clocks ==

The WonderSwan is clocked with a ''master clock'' of approximately 12288000 Hz (= 12.288 MHz).

This clock is split into four internal memory access quadrants, running at 3072000 Hz (= 3.072 MHz) each. Three of those are used by the console in "mono" mode:

* [[CPU|NEC V30MZ]] - referred to as the ''CPU clock'',
* [[Display]],
* [[Sound]].

On the WonderSwan Color, the fourth quadrant is used to handle color palette reads during display drawing.

Only the CPU quadrant can access the cartridge bus; this means that [[DMA]] necessarily stalls the CPU.

In addition, a separate 384000 Hz (3072000 / 8) ''cartridge clock'' is provided on one of the cartridge pins.

== Display timing ==

By default, a WonderSwan frame consists of 159 lines, 144 of which are visible. Each line consists of 256 clock cycles, of which 224 are used to draw a pixel at a time. This leads to a total duration of 40704 clock cycles per frame, for an effective default refresh rate of approximately 75.472 Hz.

Vertical blanks are always triggered on line 144; if the display is set to be shorter than 144 lines, vertical blank interrupts will never be triggered.

TODO: back/front porches, etc.

== Frame timing ==

The details of per-line and per-frame timing are available in a table on the [[Frame timing]] page.</text>
    <sha1>b31a880c4ad1ef04654c9cbde1411ebc890fadad</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>159</id>
    <parentid>150</parentid>
    <timestamp>2023-08-22T19:09:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4062" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

TODO

=== ERAL - Erase All ===

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa     (1 Kbit - M93LC46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pewr ....
            ||||
            |||+------ 1 for READ command, 0 otherwise
            ||+------- 1 for WRITE and WRAL command, 0 otherwise
            |+-------- 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>92a61e487fe5574da58651ecd0302bcc1911428a</sha1>
  </revision>
  <revision>
    <id>160</id>
    <parentid>159</parentid>
    <timestamp>2023-08-22T19:17:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5943" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

TODO

=== ERAL - Erase All ===

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa     (1 Kbit - M93LC46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pewr ....
            ||||
            |||+------ 1 for READ command, 0 otherwise
            ||+------- 1 for WRITE and WRAL command, 0 otherwise
            |+-------- 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==


{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>4ddf82adaf0bc56b6a0250630bdd217913ecc73e</sha1>
  </revision>
  <revision>
    <id>161</id>
    <parentid>160</parentid>
    <timestamp>2023-08-22T19:29:30Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>/* I/O ports */ timing caveat</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6144" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

TODO

=== ERAL - Erase All ===

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa     (1 Kbit - M93LC46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pewr ....
            ||||
            |||+------ 1 for READ command, 0 otherwise
            ||+------- 1 for WRITE and WRAL command, 0 otherwise
            |+-------- 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==


{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>33522c9b8dc8c1e4c856be4e15526ddf1d8872f1</sha1>
  </revision>
  <revision>
    <id>162</id>
    <parentid>161</parentid>
    <timestamp>2023-08-22T20:11:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6856" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original/"mono" WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data. This has been fixed on the WonderSwan Color, even for "mono" compatibility mode.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa     (1 Kbit - M93LC46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pewr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Erase mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Erase mode: Sends 16 bits from Command, de-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.


{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==


{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>97f5e503a8501bd068e8d55b76bf690c234657cc</sha1>
  </revision>
  <revision>
    <id>163</id>
    <parentid>162</parentid>
    <timestamp>2023-08-22T20:12:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>fix spacing</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6854" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original/"mono" WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data. This has been fixed on the WonderSwan Color, even for "mono" compatibility mode.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa     (1 Kbit - M93LC46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pewr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Erase mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Erase mode: Sends 16 bits from Command, de-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>e986b04c6b3fbf3623ed7ad94951ef1f70023d5a</sha1>
  </revision>
  <revision>
    <id>164</id>
    <parentid>163</parentid>
    <timestamp>2023-08-22T23:37:16Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>despite the name, setting the 0x20s bit in the control register doesn't cause the WSC/2001 to poll for completion when sending WEN. So unless it snoops the command bits...</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6955" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original/"mono" WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data. This has been fixed on the WonderSwan Color, even for "mono" compatibility mode.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>9fffba4035c4c7c521befd948664b95b9d5f5dd2</sha1>
  </revision>
  <revision>
    <id>199</id>
    <parentid>164</parentid>
    <timestamp>2023-08-27T10:49:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add errata</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7557" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original/"mono" WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data. This has been fixed on the WonderSwan Color, even for "mono" compatibility mode.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

As such, it is recommended to only use word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
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</page>
<page arvcontinue="20230822164322|151">
  <title>Splash animation</title>
  <ns>0</ns>
  <id>34</id>
  <revision>
    <id>165</id>
    <parentid>149</parentid>
    <timestamp>2023-08-23T06:11:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>fix URL</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2676" xml:space="preserve">The WonderSwan Color upgraded the [[EEPROM|internal EEPROM]] from 128 bytes to 2 kilobytes; most of the additional space is utilized to allow for branding consoles in the form of unique, custom splash animations on console startup.

== Format ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $83 || 1 || WSC-specific configuration. Bit 7 enables custom splash animation.
|-
| $84 || 1 || Name color
|-
| $85 || 1 || Must be $00
|-
| $86 || 1 || Size; 0 = ends at &lt;= $3FF, 1 = ends at &lt;= $7FF
|-
| $87 || 1 || First frame
|-
| $88 || 1 || Last frame
|-
| $89 || 1 || Sprite count
|-
| $8A || 1 || Palette flags
|-
| $8B || 1 || Tile count
|-
| $8C || 2 || Palette location - $80
|-
| $8E || 2 || Tile data location - $80
|-
| $90 || 2 || Tilemap location - $80
|-
| $92 || 2 || Screen offset (Horizontal)
|-
| $94 || 2 || Screen offset (Vertical)
|-
| $96 || 1 || Tilemap width
|-
| $97 || 1 || Tilemap height
|-
| $98 || 2 || VBlank IRQ handler offset
|-
| $9A || 2 || VBlank IRQ handler segment, must be $0600
|-
| $9C || 1 || Owner name X (horizontal)
|-
| $9D || 1 || Owner name Y (horizontal)
|-
| $9E || 1 || Owner name X (vertical)
|-
| $9F || 1 || Owner name Y (vertical)
|-
| $A0 || 2 || Padding, unused
|-
| $A2 || 2 || Sound wavetable location - $80
|-
| $A4 || 2 || Sound channel 1 data offset - $80
|-
| $A6 || 2 || Sound channel 2 data offset - $80
|-
| $A8 || 2 || Sound channel 3 data offset - $80
|-
| $AA || 2 || Sound channel 4 data offset - $80
|-
| $AC || 10 || SwanCrystal TFT LCD configuration
|-
| $B6 || 10 || Padding, unused
|-
| $C0 || ... || Arbitrary data - palettes, tilemaps, etc.
|}

=== Palette flags ===

&lt;pre&gt;
7  bit  0
---- ----
b..p pppp
|  +-++++- Palette count (0-16)
+--------- Tile/palette bits per pixel:
             0 = 1 bit per pixel
             1 = 2 bits per pixel
&lt;/pre&gt;

=== Name colors ===

{| class="wikitable"
|-
! Value !! RGB code
|-
| 0 || #000
|-
| 1 || #f00
|-
| 2 || #f70
|-
| 3 || #ff0
|-
| 4 || #7f0
|-
| 5 || #0f0
|-
| 6 || #0f7
|-
| 7 || #0ff
|-
| 8 || #07f
|-
| 9 || #00f
|-
| 10 || #70f
|-
| 11 || #f0f
|-
| 12 || #f07
|}

=== VBlank IRQ handler ===

A custom splash animation ''must'' provide a valid VBlank IRQ handler, with the following rules:

* The segment must be ''0x0600''; the offset is provided relative to ''$80'', as with other data offsets.
* The code must end with a ''retf'' opcode, or equivalent.

=== Horizontal/Vertical orientation handling ===

The splash animation loader will automatically rotate the tile data and tilemap when booting a cartridge whose [[ROM header|header]] declares vertical orientation as its startup orientation.

=== Sound channel data format ===

TODO</text>
    <sha1>b329fcd773f12e2e38e4995970dd769d3d2dd8dc</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>166</id>
    <parentid>146</parentid>
    <timestamp>2023-08-23T06:24:23Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>Fiskbit moved page [[Main Page]] to [[WSdev Wiki]]: Rename main page to match wiki name.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1334" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[FreyaBIOS]]
* [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>75d6c30c02e8346d5ed309791b5de20b66993cdf</sha1>
  </revision>
  <revision>
    <id>178</id>
    <parentid>166</parentid>
    <timestamp>2023-08-25T06:02:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1369" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[FreyaBIOS]]
** [[FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>0f6d5f98637e80076bd5e95c74f017375023d452</sha1>
  </revision>
  <revision>
    <id>179</id>
    <parentid>178</parentid>
    <timestamp>2023-08-25T06:06:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1411" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>5b1dd5d24a5c32bbb635543760d88aab4c570e74</sha1>
  </revision>
  <revision>
    <id>189</id>
    <parentid>179</parentid>
    <timestamp>2023-08-25T16:36:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1450" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[Display]]
* [[Sound]]
** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Keypad]]
* [[Timers]]
* [[Interrupts]]
* [[UART]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>95c33705be94f518f4d3e573b6c2e4056fc66247</sha1>
  </revision>
  <revision>
    <id>193</id>
    <parentid>189</parentid>
    <timestamp>2023-08-25T16:49:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Console components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1468" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>dc765d975223ec7acd0a2006e153928891a0140a</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Main Page</title>
  <ns>0</ns>
  <id>37</id>
  <revision>
    <id>167</id>
    <timestamp>2023-08-23T06:24:23Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Fiskbit moved page [[Main Page]] to [[WSdev Wiki]]: Rename main page to match wiki name.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="24" xml:space="preserve">#REDIRECT [[WSdev Wiki]]</text>
    <sha1>d4a3115c654c6d60b2ff1677bf90ce8b9817d25c</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>MediaWiki:Mainpage</title>
  <ns>8</ns>
  <id>38</id>
  <revision>
    <id>168</id>
    <timestamp>2023-08-23T06:24:55Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Point to the new main page name.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10" xml:space="preserve">WSdev Wiki</text>
    <sha1>a830bc53ff68da5503384ab6a4ea98619b59ae8f</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>169</id>
    <parentid>51</parentid>
    <timestamp>2023-08-23T11:17:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add SoC name</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1746" xml:space="preserve">The Bandai 2001 (LUXSOR) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;
or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ACWR ....&lt;/tt&gt;
| W8
| Abort (A), Command (C), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

The specific meaning of the "Command" register depends on the model of EEPROM on the PCB. Only three Microwire EEPROMs have been seen used (equivalent to 93C46, 93C76, and 93C86)

On the 2001, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

If more than ACWR bit is set at the same time, the 2001 ignores it.

The CWR bits specify how many data bits are sent/received. C: No data bits. W: Send Data register after command register. R: Receive data register after sending command register.

If the A bit is set, the transaction immediately stops.

(Upload logic analyzer traces here)</text>
    <sha1>e0987b1db12efc55cba425e4b9c48d6f737fff07</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Bandai 2003</title>
  <ns>0</ns>
  <id>13</id>
  <revision>
    <id>170</id>
    <parentid>75</parentid>
    <timestamp>2023-08-23T11:17:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add SoC name</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4181" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.

== 2003 RTC interface ==
The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

(Put logic analyzer traces here)

Values are as follows:

=== $00-$0F, $1C-$1F ===
Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

=== $10, $11 ===
Send command byte ($60 or $61 respectively) and stop.

=== $12 ===
Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

=== $13 ===
Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

=== $14 ===
Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the ''first'' byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

=== $15 ===
Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

=== $16 ===
Send command byte ($66), then send three bytes of payload, then stop.

=== $17 ===
Send command byte ($67), then receive three bytes of payload, then stop.

=== $18, $1A ===
Send command byte ($68 or $6A), then send two bytes of payload, then stop.

=== $19, $1B ===
Send command byte ($69 or $6B), then receive two bytes of payload, then stop.</text>
    <sha1>260f7f0e96b5cc553681bb7168e1a9e022c4d2b5</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>KARNAK</title>
  <ns>0</ns>
  <id>18</id>
  <revision>
    <id>171</id>
    <parentid>139</parentid>
    <timestamp>2023-08-23T11:17:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2573" xml:space="preserve">The KARNAK mapper is only used in some Pocket Challenge V2 edutainment cartridges.

It is not yet well-documented. It is thought to be a revision of [[Bandai 2003]] that removes the RTC interface, and adds a timer IRQ and a hardware IMA ADPCM decoder.

This page should not be taken as authoritative: it has been pieced together from multiple other pieces of research. It is unclear if the GPO and Self-Flash registers exist; from PCB photos the Self-Flash register is unused if it does exist.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|- 
! Timer
! $D6
| Programmable Interval Timer
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eppp pppp&lt;/tt&gt;
| RW8
| Enable (e); Period (p). Units are the 384kHz clock to the cartridge.
|-
! rowspan=2|ADPCM
! $D8
| Packed data
| ?
| W8?
| Write two-sample packed ADPCM byte
|-
! $D9
| Unpacked data
| ?
| R8?
| Read two one-byte unpacked PCM bytes, in sequence
|}

== Timer ==

If enabled, the timer will emit a [[Interrupts|cartridge interrupt]] every &lt;code&gt;((period + 1) * 2)&lt;/code&gt; cartridge clocks, where "one cartridge clock" = 384KHz = 1/8th CPU clock.</text>
    <sha1>8b487e952deb84c1e2ea1efb2162140fe1c7234c</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>NEC V30MZ</title>
  <ns>0</ns>
  <id>39</id>
  <revision>
    <id>172</id>
    <timestamp>2023-08-23T16:27:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The NEC V30MZ is the CPU component of the WonderSwan SoC.  == Sections ==  * [[NEC V30MZ/Undocumented|CPU undocumented behavior]]  == Links ==  * [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="226" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

== Sections ==

* [[NEC V30MZ/Undocumented|CPU undocumented behavior]]

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]</text>
    <sha1>cdf08baff9b18a1658ca8b9b1d20c8e07df5ff80</sha1>
  </revision>
  <revision>
    <id>173</id>
    <parentid>172</parentid>
    <timestamp>2023-08-23T16:29:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="703" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki has standardized on.

== Sections ==

* [[NEC V30MZ/Undocumented|CPU undocumented behavior]]

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]</text>
    <sha1>d867a96624eef10d13a212d35634fb1c2cbc76bc</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Real-Time Clock</title>
  <ns>0</ns>
  <id>40</id>
  <revision>
    <id>174</id>
    <timestamp>2023-08-23T23:15:43Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>get something here</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4064" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Internal operation ==
The RTC consists of 10 total bytes of user-visible state.
The following are always interpreted as 2 digit packed BCD.
* Year (always assumes 00 is a leap year)
* Month (1=January)
* Day-of-month (1-indexed)
* Day-of-week (0-indexed and free-running, no predefined mapping of number to legal day)
* Hour
* Minute
* Second

* Configuration
* Alarm configuration

=== Configuration ===

 7  bit  0
 P2A0 M0F0
 |||| ||||
 |||+--+-+--- always 0
 ||+--+-+---- IRQ mode
 |+---------- 1: 24 hour mode   0: 12 hour mode
 +----------- power failure occurred

Sending the Reset or Read Configuration commands clear the "power failure" bit.

Interrupts:

 AMF
 000 -- "No interrupts" - continuously deasserts /IRQ pin
 100 -- "Alarm" - Treat "alarm configuration" as packed BCD HHMM. Assert /IRQ during that hour and minute. Hour encoding must match 12/24 bit setting.
 x10 -- "Per-minute edge" - Asserts /IRQ during the first 10 ms of each minute. During following 990ms, /IRQ can be deasserted by reading the configuration register.
 x11 -- "Per-minute steady" - Asserts /IRQ during the first 10ms of each minute. De-asserts /IRQ at the 30th second.
 x01 -- "Frequency" - subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while Cassette interrupts are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>a63417d1cb1746d69e0e3151e8ecbca6ea98b07b</sha1>
  </revision>
  <revision>
    <id>175</id>
    <parentid>174</parentid>
    <timestamp>2023-08-23T23:51:49Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>/* Internal operation */ reflow</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4090" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Internal operation ==
The RTC consists of 10 total bytes of user-visible state.
* Configuration
* Alarm configuration
The following are always interpreted as 2 digit packed BCD.
* Year (always assumes 00 is a leap year)
* Month (1=January)
* Day-of-month (1-indexed)
* Day-of-week (0-indexed and free-running, no predefined mapping of number to legal day)
* Hour (0x80s bit is 12/24 state)
* Minute
* Second

=== Configuration ===

 7  bit  0
 P2A0 M0F0
 |||| ||||
 |||+--+-+--- always 0
 ||+--+-+---- IRQ mode
 |+---------- 1: 24 hour mode   0: 12 hour mode
 +----------- power failure occurred

Sending the Reset or Read Configuration commands clear the "power failure" bit.

Interrupts:

 AMF
 000 -- "No interrupts" - continuously deasserts /IRQ pin
 100 -- "Alarm" - Treat "alarm configuration" as packed BCD HHMM. Assert /IRQ during that hour and minute. Hour encoding must match 12/24 bit setting.
 x10 -- "Per-minute edge" - Asserts /IRQ during the first 10 ms of each minute. During following 990ms, /IRQ can be deasserted by reading the configuration register.
 x11 -- "Per-minute steady" - Asserts /IRQ during the first 10ms of each minute. De-asserts /IRQ at the 30th second.
 x01 -- "Frequency" - subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while Cassette interrupts are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>a5d1ea33868139574015d329f2b463cecf02fb19</sha1>
  </revision>
  <revision>
    <id>176</id>
    <parentid>175</parentid>
    <timestamp>2023-08-24T07:28:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>adjust terminology to match wiki</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4085" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Internal operation ==
The RTC consists of 10 total bytes of user-visible state.
* Configuration
* Alarm configuration
The following are always interpreted as 2 digit packed BCD.
* Year (always assumes 00 is a leap year)
* Month (1=January)
* Day-of-month (1-indexed)
* Day-of-week (0-indexed and free-running, no predefined mapping of number to legal day)
* Hour (0x80s bit is 12/24 state)
* Minute
* Second

=== Configuration ===

 7  bit  0
 P2A0 M0F0
 |||| ||||
 |||+--+-+--- always 0
 ||+--+-+---- IRQ mode
 |+---------- 1: 24 hour mode   0: 12 hour mode
 +----------- power failure occurred

Sending the Reset or Read Configuration commands clear the "power failure" bit.

Interrupts:

 AMF
 000 -- "No interrupts" - continuously deasserts /IRQ pin
 100 -- "Alarm" - Treat "alarm configuration" as packed BCD HHMM. Assert /IRQ during that hour and minute. Hour encoding must match 12/24 bit setting.
 x10 -- "Per-minute edge" - Asserts /IRQ during the first 10 ms of each minute. During following 990ms, /IRQ can be deasserted by reading the configuration register.
 x11 -- "Per-minute steady" - Asserts /IRQ during the first 10ms of each minute. De-asserts /IRQ at the 30th second.
 x01 -- "Frequency" - subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>510ff6fb004672590762e9735a6a7063929a5ed1</sha1>
  </revision>
  <revision>
    <id>177</id>
    <parentid>176</parentid>
    <timestamp>2023-08-24T17:41:27Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>/* Internal operation */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4095" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Internal operation ==
The RTC consists of 10 total bytes of user-visible state.
* Configuration
* Alarm configuration (2 bytes)
The following are always interpreted as 2 digit packed BCD.
* Year (always assumes 00 is a leap year)
* Month (1=January)
* Day-of-month (1-indexed)
* Day-of-week (0-indexed and free-running, no predefined mapping of number to legal day)
* Hour (0x80s bit is 12/24 state)
* Minute
* Second

=== Configuration ===

 7  bit  0
 P2A0 M0F0
 |||| ||||
 |||+--+-+--- always 0
 ||+--+-+---- IRQ mode
 |+---------- 1: 24 hour mode   0: 12 hour mode
 +----------- power failure occurred

Sending the Reset or Read Configuration commands clear the "power failure" bit.

Interrupts:

 AMF
 000 -- "No interrupts" - continuously deasserts /IRQ pin
 100 -- "Alarm" - Treat "alarm configuration" as packed BCD HHMM. Assert /IRQ during that hour and minute. Hour encoding must match 12/24 bit setting.
 x10 -- "Per-minute edge" - Asserts /IRQ during the first 10 ms of each minute. During following 990ms, /IRQ can be deasserted by reading the configuration register.
 x11 -- "Per-minute steady" - Asserts /IRQ during the first 10ms of each minute. De-asserts /IRQ at the 30th second.
 x01 -- "Frequency" - subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>aad9bb9c4a478d115abf42b6e5149e2657527904</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>WonderWitch</title>
  <ns>0</ns>
  <id>41</id>
  <revision>
    <id>180</id>
    <timestamp>2023-08-25T06:10:28Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderWitch is an official homebrew development kit released by Qute Corporation on July 18th, 2000.  == Hardware ==  The WonderWitch cartridge is based on the [[Bandai 2003]] mapper. It provides an RTC, as well as NOR self-flashing functionality using the Fujitsu MBM29DL400TC chip.  There were three ways available to acquire WonderWitch cartridges:  * '''WonderWitch''', a software development kit containing a reflashable cartridge, a WonderSwan&lt;-&gt;RS-232 adapter, a d..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1343" xml:space="preserve">The WonderWitch is an official homebrew development kit released by Qute Corporation on July 18th, 2000.

== Hardware ==

The WonderWitch cartridge is based on the [[Bandai 2003]] mapper. It provides an RTC, as well as NOR self-flashing functionality using the Fujitsu MBM29DL400TC chip.

There were three ways available to acquire WonderWitch cartridges:

* '''WonderWitch''', a software development kit containing a reflashable cartridge, a WonderSwan&lt;-&gt;RS-232 adapter, a development manual and a development tool CD;
* '''WonderWitch Player''', a priced-down user-only version omitting the development manual and tooling;
* The VAR program, allowing independent creators to buy reflashable cartridges in bulk, in units of 20 or 100.

== Software ==

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/File system|File system]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}

== Development Tools ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Fujitsu MBM29DL400TC datasheet]</text>
    <sha1>566f634e6aae48b73f50f4bb68d44303d03a5fae</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>WonderWitch/FreyaBIOS</title>
  <ns>0</ns>
  <id>42</id>
  <revision>
    <id>181</id>
    <timestamp>2023-08-25T06:16:03Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.  It provides the following functionality:  * bring-up code, * interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware, * a monitor program, allowing FreyaOS recovery and updates via XMODEM.  Other functionality (like file system access) is instead includ..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1177" xml:space="preserve">FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.

It provides the following functionality:

* bring-up code,
* interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware,
* a monitor program, allowing FreyaOS recovery and updates via XMODEM.

Other functionality (like file system access) is instead included as part of [[WonderWitch/FreyaOS|FreyaOS]]' system libraries; some other functionality (like WonderSwan Color support is implemented as part of the development tooling.

== Revisions ==

TODO

== Interrupts ==

* [[WonderWitch/FreyaBIOS/Exit|Exit]] (INT $10)
* [[WonderWitch/FreyaBIOS/Key|Key]] (INT $11)
* [[WonderWitch/FreyaBIOS/Display|Display]] (INT $12)
* [[WonderWitch/FreyaBIOS/Text|Text]] (INT $13)
* [[WonderWitch/FreyaBIOS/Communication|Communication]] (INT $14)
* [[WonderWitch/FreyaBIOS/Sound|Sound]] (INT $15)
* [[WonderWitch/FreyaBIOS/Timer|Timer]] (INT $16)
* [[WonderWitch/FreyaBIOS/System|System]] (INT $17)
* [[WonderWitch/FreyaBIOS/Bank|Bank]] (INT $18)

== Freya Monitor ==

TODO</text>
    <sha1>6bd7cf8d2d0effa3cb049dfbfc970055d9dee56d</sha1>
  </revision>
  <revision>
    <id>182</id>
    <parentid>181</parentid>
    <timestamp>2023-08-25T06:20:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1206" xml:space="preserve">FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.

It provides the following functionality:

* bring-up code,
* interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware,
* 8x8 ASCII and kanji fonts,
* a monitor program, allowing FreyaOS recovery and updates via XMODEM.

Other functionality (like file system access) is instead included as part of [[WonderWitch/FreyaOS|FreyaOS]]' system libraries; some other functionality (like WonderSwan Color support is implemented as part of the development tooling.

== Revisions ==

TODO

== Interrupts ==

* [[WonderWitch/FreyaBIOS/Exit|Exit]] (INT $10)
* [[WonderWitch/FreyaBIOS/Key|Key]] (INT $11)
* [[WonderWitch/FreyaBIOS/Display|Display]] (INT $12)
* [[WonderWitch/FreyaBIOS/Text|Text]] (INT $13)
* [[WonderWitch/FreyaBIOS/Communication|Communication]] (INT $14)
* [[WonderWitch/FreyaBIOS/Sound|Sound]] (INT $15)
* [[WonderWitch/FreyaBIOS/Timer|Timer]] (INT $16)
* [[WonderWitch/FreyaBIOS/System|System]] (INT $17)
* [[WonderWitch/FreyaBIOS/Bank|Bank]] (INT $18)

== Freya Monitor ==

TODO</text>
    <sha1>7e33c04d2b0a361866b0b73a4721cc7d6eaaa98b</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Keypad</title>
  <ns>0</ns>
  <id>9</id>
  <revision>
    <id>183</id>
    <parentid>118</parentid>
    <timestamp>2023-08-25T06:24:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2921" xml:space="preserve">The WonderSwan SoC features a 4 by 3 keypad matrix.

== I/O Ports ==

=== Keypad Scan ($B5) ===

Scanning is done via writing to and reading from port $B5.

&lt;pre&gt;
7  bit  0
---- ----
.iii oooo
 ||| ||||
 ||| ++++- Output rows (0-3)
 +++------ Input rows  (4-6)
&lt;/pre&gt;

The standard procedure is to read rows controlled by bit 4, bit 5, then bit 6 in order, shifting their values into one twelve-bit mask like so:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... 4444  5555 6666
&lt;/pre&gt;

Typical keypad scanning implementations introduce a delay between writing to and reading from the matrix, allowing the scanned values to stabilize. For example, one can use the DAA opcode for doing so.

== Startup override ==

On startup, the [[boot ROM]] checks whether or not certain output rows are forced high when all input rows are disabled. This triggers a startup override prior to the boot logo:

* Input row 0 - jump to 4000:0000,
* Input row 1 - jump to 4000:0010.

As this override is done before boot ROM lockout, it can be used to dump the boot ROM.

== Keypad arrangement ==

=== WonderSwan ===

==== Layout ====

&lt;pre&gt;
    Y1
 Y4    Y2
    Y3


    X1
 X4    X2                              A
    X3       Sound Start Power      B
                    (St)
&lt;/pre&gt;

Sound and Power buttons are not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Y4 - Y3 - Y2 - Y1 -
      |    |    |    |
5--- X4 - X3 - X2 - X1 -
      |    |    |    |
6---  B -  A - St ---+--
      |    |    |    |

&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... yyyy  xxxx bas.
      ||||  |||| |||
      ||||  |||| ||+- Start
      ||||  |||| |+-- A
      ||||  |||| +--- B
      ||||  ++++----- X4, X3, X2, X1
      ++++----------- Y4, Y3, Y2, Y1      
&lt;/pre&gt;

=== Pocket Challenge V2 ===

==== Layout ====

&lt;pre&gt;
  Power


     Esc
                                 View
   Up                                  Clear
                                       (Clr)
 Lft Rgh                           Circle
                                    (Crc)
   Dwn                           Pass
                                (Pas)
&lt;/pre&gt;

The Power switch is not exposed directly to software.

==== Matrix ====

&lt;pre&gt;
Bit O 3    2    1    0
I     |    |    |    |
      |    |    |    |
4--- Pas  Crc --+-- Clr -
      |    |    |    |
5--- Rgh  Esc --+- View -
      |    |    |    |
6--- Up - Dwn --+-- Lft -
      |    |    |    |
               [1]
&lt;/pre&gt;

==== Bit mask ====

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... pc1C  re1v ud1l
      || |  || | || |
      || |  || | || +- Left
      || |  || | |+--- Down
      || |  || | +---- Up
      || |  || +------ View
      || |  |+-------- Esc
      || |  +--------- Right
      || +----------- Clear
      |+------------- Circle
      +-------------- Pass
&lt;/pre&gt;</text>
    <sha1>5a5167d16ae0e6b42ad821dfc6c256673ed97b3a</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Accessory port pinout</title>
  <ns>0</ns>
  <id>43</id>
  <revision>
    <id>184</id>
    <timestamp>2023-08-25T09:29:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.  == Pinout ==  (Female 8-pin port on peripheral)  &lt;pre&gt;        MISO_          _MOSI             \        /       +3V_   \      /   _GND     ______\ __\ __ /__ /______    |      04__03__02__01      |    |   __|""  ""  ""  ""|__   |    |  |__                __|  |    '.    |..__..__..__..|    .'      \____05__06__07__08____/          _/   /    \   \_      BCLK    /..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1929" xml:space="preserve">The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Thanks to luck, it turns out that female HDMI connectors are - to some extent - electrically compatible with male EXT port connectors:

* Using an HDMI plug may cause increased wear on the connector.
* A typical HDMI cable port lacks the plastic sleeve around the connector, leading to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Nonetheless, due to the lack of availability of new EXT port connectors, this is a popular solution for DIY users and lower-end aftermarket accessories. The HDMI pinout maps as follows:

{| class="wikitable"
|-
! EXT !! HDMI
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>2ee56876eb167b3254a5a77eea85d9a5c3abd0b7</sha1>
  </revision>
  <revision>
    <id>185</id>
    <parentid>184</parentid>
    <timestamp>2023-08-25T09:29:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1932" xml:space="preserve">The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Thanks to luck, it turns out that female HDMI connectors are - to some extent - electrically compatible with male EXT port connectors:

* Using an HDMI plug may cause increased wear on the connector.
* A typical HDMI cable port lacks the plastic sleeve around the connector, leading to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Nonetheless, due to the lack of availability of new EXT port connectors, this is a popular solution for DIY users and lower-end aftermarket accessories. The HDMI pinout maps as follows:

{| class="wikitable"
|-
! EXT !! HDMI
|-
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>aad8020be70496cdd6062f70b51f4cbe3760fb8a</sha1>
  </revision>
  <revision>
    <id>186</id>
    <parentid>185</parentid>
    <timestamp>2023-08-25T09:29:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1932" xml:space="preserve">The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; Accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Thanks to luck, it turns out that female HDMI connectors are - to some extent - electrically compatible with male EXT port connectors:

* Using an HDMI plug may cause increased wear on the connector.
* A typical HDMI cable port lacks the plastic sleeve around the connector, leading to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Nonetheless, due to the lack of availability of new EXT port connectors, this is a popular solution for DIY users and lower-end aftermarket accessories. The HDMI pinout maps as follows:

{| class="wikitable"
|-
! EXT !! HDMI
|-
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>a124e4b736c4fbafb198de8a02f7183a1eda27dc</sha1>
  </revision>
  <revision>
    <id>187</id>
    <parentid>186</parentid>
    <timestamp>2023-08-25T09:30:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1930" xml:space="preserve">The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; Accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Thanks to luck, it turns out that male HDMI connectors are - to some extent - electrically compatible with male EXT port connectors:

* Using an HDMI plug may cause increased wear on the connector.
* A typical HDMI cable port lacks the plastic sleeve around the connector, leading to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Nonetheless, due to the lack of availability of new EXT port connectors, this is a popular solution for DIY users and lower-end aftermarket accessories. The HDMI pinout maps as follows:

{| class="wikitable"
|-
! EXT !! HDMI
|-
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>bc4a9cc028166091263245c1f6738c2046e600e0</sha1>
  </revision>
  <revision>
    <id>188</id>
    <parentid>187</parentid>
    <timestamp>2023-08-25T09:30:21Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2001" xml:space="preserve">The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; Accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Thanks to luck, it turns out that male HDMI connectors are - to some extent - electrically compatible with male EXT port connectors, allowing to use them as a replacement for a female EXT port connector:

* Using an HDMI plug may cause increased wear on the connector.
* A typical HDMI cable port lacks the plastic sleeve around the connector, leading to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Nonetheless, due to the lack of availability of new EXT port connectors, this is a popular solution for DIY users and lower-end aftermarket accessories. The HDMI pinout maps as follows:

{| class="wikitable"
|-
! EXT !! HDMI
|-
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>887631e64eb2c77ee97559a4e8054bc517419d86</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Cartridge connector</title>
  <ns>0</ns>
  <id>44</id>
  <revision>
    <id>190</id>
    <timestamp>2023-08-25T16:44:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with " == Pinout ==  &lt;pre&gt; Cartridge              Console (label side)            (back) ____________        |====| ____   |--01| -- GND ... \  | -02| &lt;- CPU A15 ... |  | -03| &lt;- CPU A10 ... |  | -04| &lt;- CPU A11 ... |  | -05| &lt;- CPU A9 ... |  | -06| &lt;- CPU A8 ... |  | -07| &lt;- CPU A13 ... |  | -08| &lt;- CPU A14 ... |  | -09| &lt;- CPU A12 ... |  | -10| &lt;- CPU A7 ... |  | -11| &lt;- CPU A6 ... |  | -12| &lt;- CPU A5 ... |  | -13| &lt;- CPU A4 ... |  | -14| &lt;&gt; D15 ... |  | -15| &lt;&gt; D14 ... |  |..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1371" xml:space="preserve">
== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /Reset
... |  | -41| &lt;- /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
... |  | -47| &lt;- CLK  (384 KHz clock)
... |  |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;</text>
    <sha1>2cbbd3d1bfa1bef4af87b44d1999c031d1930169</sha1>
  </revision>
  <revision>
    <id>191</id>
    <parentid>190</parentid>
    <timestamp>2023-08-25T16:45:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Pinout */ art tweaks</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1371" xml:space="preserve">
== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /Reset
... |  | -41| &lt;- /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK  (384 KHz clock)
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;</text>
    <sha1>c0cc59ff44f9af3c33ac1388a1fb2c4f30dcae71</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>Cartridge</title>
  <ns>0</ns>
  <id>45</id>
  <revision>
    <id>192</id>
    <timestamp>2023-08-25T16:48:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Cartridge bus ==  The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF).  To facilitate this, the Memory/IO pin is used:  * When Memory/IO is asserted '''high''', all bus address pins specify the 20-bit linear memory address. * When Memory/IO is asserted '''low''', bus address pins 0-7 specify the port address bits 0-7, bus address pins 8-15 are low, bus address pins 16-19 specify the port address bits 4-..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="594" xml:space="preserve">== Cartridge bus ==

The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF).

To facilitate this, the Memory/IO pin is used:

* When Memory/IO is asserted '''high''', all bus address pins specify the 20-bit linear memory address.
* When Memory/IO is asserted '''low''', bus address pins 0-7 specify the port address bits 0-7, bus address pins 8-15 are low, bus address pins 16-19 specify the port address bits 4-7.

== Interrupts ==

The cartridge bus provides an /IRQ pin which can be used by the cartridge to assert an interrupt.</text>
    <sha1>a4b2b9b9463bc4b4924369abb1f2d0b578e1de43</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>SoC</title>
  <ns>0</ns>
  <id>46</id>
  <revision>
    <id>195</id>
    <timestamp>2023-08-25T16:55:56Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.  There exist three variants of the SoC:  * ASWAN, used in the WonderSwan, * SPHINX, used in the WonderSwan Color, * SPHINX2, used in the SwanCrystal.  A fourth variant, CAIRO, was planned. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commer..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1407" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge bus width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge bus speed; 0 = 3 cycles, 1 = 1 cycle
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. ?.??
|||
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}
=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;</text>
    <sha1>0ef957dff9fde2df44c7522d6cb571a31fadf3f5</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>WonderGate</title>
  <ns>0</ns>
  <id>14</id>
  <revision>
    <id>196</id>
    <parentid>47</parentid>
    <timestamp>2023-08-25T17:04:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1487" xml:space="preserve">The WonderGate is a PPP Internet adapter for the WonderSwan, utilizing a PDC-standard mobile phone as a modem.

== Commands ==

All command communication uses the following format over 9,600 baud [[UART]]:

{| class="wikitable"
|-
! Offset !! Length !! Description
|-
| $00 || 1 || Command type
|-
| $01 || 1 || Zero?
|-
| $02 || 1 || Remaining length (from $03 onwards)
|-
| $03 || 1 || Command
|-
| $04 || ... || Parameters
|}

The following command IDs will be provided in the &lt;code&gt;Type:Command&lt;/code&gt; format.

=== Check PDC status ($01:$00) ===

=== Initialize adapter ($01:$02) ===

=== Dial phone number ($01:$08) ===

=== Hang up ($01:$0A) ===

=== Set PPP login/password ($01:$10) ===

=== Set DNS servers ($01:$11) ===

=== Get adapter status ($02:$01) ===

=== Deinitialize adapter ($0F:$FF) ===

=== Create socket ($11:$01) ===

=== Connect to socket ($11:$03) ===

=== Close socket ($11:$07) ===

=== Get host name/IP address ($11:$08) ===

=== Read line from socket ($11:$0D) ===

=== Write bytes to socket ($11:$0E) ===

=== Read bytes from socket ($11:$0F) ===

== Servers ==

{| class="wikitable"
|-
! Software !! Hostname
|-
| rowspan="2" | MobileWonderGate (web browser)
| [[WonderGate/bplXX.mopera.ne.jp|bpl01.mopera.ne.jp]]
|-
| [[WonderGate/bplXX.mopera.ne.jp|bpl02.mopera.ne.jp]]
|-
| Pocket Fighter
|
|-
| Rainbow Islands - Putty's Party
|
|-
| Star Hearts
|
|-
| Terrors 2
| [[WonderGate/terrors2.wgg.channel.or.jp|terrors2.wgg.channel.or.jp]]
|-
| Wizardry
|
|}</text>
    <sha1>560a299a9e7c105b89960e231614a3dc17ec20c8</sha1>
  </revision>
</page>
<page arvcontinue="20230822164322|151">
  <title>WonderBeat 9480</title>
  <ns>0</ns>
  <id>47</id>
  <revision>
    <id>197</id>
    <timestamp>2023-08-27T07:44:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>stub</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="191" xml:space="preserve">The WonderBeat 9480 is the official WonderSwan headphone digital/analog converter.

== Links ==

* [http://perfectkiosk.net/stsws.html#sound_output_procedure STSWS - Sound - Output Procedure]</text>
    <sha1>41fa99cceb6b7a1da508f77d384676ebae5f8fb6</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>201</id>
    <parentid>193</parentid>
    <timestamp>2023-08-27T10:52:54Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1483" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>9d67876bf68dc4ff2486b2337155cdbfda28d8bb</sha1>
  </revision>
  <revision>
    <id>250</id>
    <parentid>201</parentid>
    <timestamp>2024-02-19T19:55:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1520" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>2348041c9592ef58865c9d69d5c918390e352085</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>202</id>
    <parentid>199</parentid>
    <timestamp>2023-08-27T10:57:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7556" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original/"mono" WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data. This has been fixed on the WonderSwan Color, even for "mono" compatibility mode.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 | Last booted cartridge developer/publisher ID
|-
| $77 || 1 | Last booted cartridge game ID
|-
| $78 || 1 | Last booted cartridge game version
|-
| $7C || 1 | Stored cartridge ID/version change counter
|-
| $7D || 1 | Owner name change counter
|-
| $7E || 2 | System startup counter
|-
| $83 || 1 | Color console configuration
|-
| $84 || ? | [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>b1b997dbd577c755b9dfda49f2965e22e306bfd2</sha1>
  </revision>
  <revision>
    <id>203</id>
    <parentid>202</parentid>
    <timestamp>2023-08-27T10:58:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Layout */  fix table</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7564" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

Note that on the original/"mono" WonderSwan, the data and command registers can ''only'' be accessed word-wide via even addresses: access to odd addresses whether byte or word-wide don't provide valid data. This has been fixed on the WonderSwan Color, even for "mono" compatibility mode.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>c8355281f5dbc89e876cf65bb7f8024b34062cb0</sha1>
  </revision>
  <revision>
    <id>210</id>
    <parentid>203</parentid>
    <timestamp>2023-08-27T19:24:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7417" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....     (1 Kbit - M93LC46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}
=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>3cb6f0ac40ab2536f4dde79286c964fc9606b757</sha1>
  </revision>
  <revision>
    <id>211</id>
    <parentid>210</parentid>
    <timestamp>2023-08-28T18:23:22Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>/* Internal EEPROM Command ($BC, $BD) */ if i mention 93'06 once I should be consistent</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7422" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>4af9c8ee1901b872f2c4da118fb036cb0da42c2d</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>SoC</title>
  <ns>0</ns>
  <id>46</id>
  <revision>
    <id>204</id>
    <parentid>195</parentid>
    <timestamp>2023-08-27T11:04:10Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add CAIRO reference</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1610" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge bus width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge bus speed; 0 = 3 cycles, 1 = 1 cycle
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. ?.??
|||
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}
=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>8586f9f9316ce59d5a0c9d0c9f3033a4b39ca8ec</sha1>
  </revision>
  <revision>
    <id>221</id>
    <parentid>204</parentid>
    <timestamp>2023-08-29T21:42:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>un-swap cartridge bus speed</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1610" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge bus width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge bus speed: 0 = 1 cycle, 1 = 3 cycles
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. ?.??
|||
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}
=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>be4eab6a52548138e3c92b2d8c694e872f9f4578</sha1>
  </revision>
  <revision>
    <id>222</id>
    <parentid>221</parentid>
    <timestamp>2023-08-29T21:52:10Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document port $60 bit 1</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1676" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +2
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. ?.s?
|||    |
|||    +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}
=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>170a8a82cf8d2101d8197568923e5207f538ca01</sha1>
  </revision>
  <revision>
    <id>226</id>
    <parentid>222</parentid>
    <timestamp>2023-08-30T18:42:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* System Control 2 ($60, color) */ document bit 3</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1736" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +2
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?s?
|||  | |
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>ec56fa08192da5f9612392e358a8d0371bd13541</sha1>
  </revision>
  <revision>
    <id>233</id>
    <parentid>226</parentid>
    <timestamp>2023-09-01T14:16:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>hint at $60 bit 0</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1771" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +2
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>3de6f6d1cfab0fc08ba09e39ae12a55f3e2e08ee</sha1>
  </revision>
  <revision>
    <id>244</id>
    <parentid>233</parentid>
    <timestamp>2023-12-22T12:03:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1771" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>742a10368ba5e0b93955a5fbee4185f942b0acbf</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>205</id>
    <parentid>121</parentid>
    <timestamp>2023-08-27T11:11:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>clarify sprites, priority</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11132" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}
=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== LCD Timing Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>26225b25b1ed95f35aec585f66ee9f035ec34d01</sha1>
  </revision>
  <revision>
    <id>206</id>
    <parentid>205</parentid>
    <timestamp>2023-08-27T18:54:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add missing ports</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="12338" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 pxl 1,0      pxl 2,3      pxl 5,4      pxl 7,6
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}
=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>e635deb6c68a54dc967c674b01a43e3814350254</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>NEC V30MZ</title>
  <ns>0</ns>
  <id>39</id>
  <revision>
    <id>207</id>
    <parentid>173</parentid>
    <timestamp>2023-08-27T18:55:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add STSWS link for now</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="790" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki has standardized on.

== Sections ==

* [[NEC V30MZ/Undocumented|CPU undocumented behavior]]

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
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  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>Sound</title>
  <ns>0</ns>
  <id>27</id>
  <revision>
    <id>208</id>
    <parentid>147</parentid>
    <timestamp>2023-08-27T18:56:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8837" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+------|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+----|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16---|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16---|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Channel Output Right}}
=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>befcfbb2d9dcf9dd74a1fa4044a63c52b0eb9da5</sha1>
  </revision>
  <revision>
    <id>209</id>
    <parentid>208</parentid>
    <timestamp>2023-08-27T18:56:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Mixing diagram */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8837" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Channel Output Right}}
=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>14bc5225f45fb299feb64dc59c548aee4adf01a2</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>Hyper Voice</title>
  <ns>0</ns>
  <id>30</id>
  <revision>
    <id>212</id>
    <parentid>131</parentid>
    <timestamp>2023-08-29T13:00:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>Fix formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2256" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65) ===

=== Hyper Voice Right Output ($66, $67) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68) ===

=== Hyper Voice Right Input ($69) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ....  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Input channel: 0 = left, 1 = right
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>36bfe25bb5c05c306501670681bb1124c7ba916f</sha1>
  </revision>
  <revision>
    <id>214</id>
    <parentid>212</parentid>
    <timestamp>2023-08-29T14:08:32Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix Control register</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2252" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65) ===

=== Hyper Voice Right Output ($66, $67) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68) ===

=== Hyper Voice Right Input ($69) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Write 1 to reset input channel
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>008e952c7c184a0555969fc784c9d9bd0b6d66ac</sha1>
  </revision>
  <revision>
    <id>216</id>
    <parentid>214</parentid>
    <timestamp>2023-08-29T14:09:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Hyper Voice Control ($6A, $6B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2264" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65) ===

=== Hyper Voice Right Output ($66, $67) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68) ===

=== Hyper Voice Right Input ($69) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Write 1 to reset DMA input channel to left
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>72a8611dd07235efcfba7fadcf68dbda4de2f77f</sha1>
  </revision>
  <revision>
    <id>218</id>
    <parentid>216</parentid>
    <timestamp>2023-08-29T14:20:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2288" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68 write) ===

=== Hyper Voice Right Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Input sample mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negate
  |||       ||||         2 = Signed
  |||       ||||         3 = Signed, ignore Shift/Volume
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Write 1 to reset DMA input channel to left
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;</text>
    <sha1>026723482ae0e63e5c26ed68ac8a4e7342433738</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>213</id>
    <parentid>200</parentid>
    <timestamp>2023-08-29T13:01:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>add hyperlinks for Hyper Voice ports</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="20785" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| 8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc .... errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>811ca6c7bebfcc0cf1870ccd001beace6a5c7e96</sha1>
  </revision>
  <revision>
    <id>215</id>
    <parentid>213</parentid>
    <timestamp>2023-08-29T14:09:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix Hyper Voice ports</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="20793" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>b2fb5d5e6f07ac069bae8c9fe2c9bb64d76f43ff</sha1>
  </revision>
  <revision>
    <id>217</id>
    <parentid>215</parentid>
    <timestamp>2023-08-29T14:18:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add mystery port at $AC</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="20909" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! [[Interrupts]]
! $B0
| [[Interrupts#Interrupt Vector|Interrupt Vector]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| RW8
| Vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>026be14a9d45a27822e2a28fb7296b5dfeef5a8e</sha1>
  </revision>
  <revision>
    <id>219</id>
    <parentid>217</parentid>
    <timestamp>2023-08-29T21:05:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>improve $B0 documentation</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21132" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.??&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM speed (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>89474dbf48c06718c6d84d0c2119f652dd3376af</sha1>
  </revision>
  <revision>
    <id>223</id>
    <parentid>219</parentid>
    <timestamp>2023-08-29T21:52:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document port $60 bit 1</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21162" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.s?&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)&lt;br/&gt;
SRAM wait state (s)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| R8
| ?
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>814477d25b1aa209869e3842c8a10893f70ce09e</sha1>
  </revision>
  <revision>
    <id>224</id>
    <parentid>223</parentid>
    <timestamp>2023-08-29T22:05:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>update $9E</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21179" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. ?.s?&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)&lt;br/&gt;
SRAM wait state (s)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>acbe4a04540381351636033517ccc736afe03d16</sha1>
  </revision>
  <revision>
    <id>227</id>
    <parentid>224</parentid>
    <timestamp>2023-08-30T18:43:00Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document port $60 bit 3</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21199" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width
|-
| $00 || $B7 || WonderSwan SoC || 8/16-bit
|-
| $B8 || $BF || Internal EEPROM control || 16-bit
|-
| $C0 || $FF || Cartridge bus || 8-bit
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?s?&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)&lt;br/&gt;
I/O wait state (i), SRAM wait state (s)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>1ff6d7864fdc7a6652746bc1840fe01edbc14fff</sha1>
  </revision>
  <revision>
    <id>228</id>
    <parentid>227</parentid>
    <timestamp>2023-08-30T18:45:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21275" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaaa&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbbb&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?s?&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)&lt;br/&gt;
I/O wait state (i), SRAM wait state (s)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>ddc304c397ddd81ae7a23270104150c941efb010</sha1>
  </revision>
  <revision>
    <id>230</id>
    <parentid>228</parentid>
    <timestamp>2023-08-30T20:39:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>adjust GDMA ports</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21275" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t r?ff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?s?&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C)&lt;br/&gt;
I/O wait state (i), SRAM wait state (s)
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>24ccfa4b5e117db1474ab67659fcaa26e66ebf62</sha1>
  </revision>
  <revision>
    <id>232</id>
    <parentid>230</parentid>
    <timestamp>2023-09-01T14:16:10Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>update port $52, $60</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21319" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| R8?
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>bf7ea2e16ea78b9b74b3414cecb83ae09b05ad65</sha1>
  </revision>
  <revision>
    <id>234</id>
    <parentid>232</parentid>
    <timestamp>2023-09-01T14:18:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix port $B6</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21318" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| iiii iiii
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| iiii iiii
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| iiii iiii
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>3ebfc6c9b834d075944bad053ae17ec1774f349f</sha1>
  </revision>
  <revision>
    <id>245</id>
    <parentid>234</parentid>
    <timestamp>2024-02-08T22:16:48Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>/* I/O port map */ Formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21522" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $68
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Left Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>c253ae2d2f246460b468c130b35326a7253b2f26</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>Interrupts</title>
  <ns>0</ns>
  <id>22</id>
  <revision>
    <id>220</id>
    <parentid>116</parentid>
    <timestamp>2023-08-29T21:07:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2853" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector Offset}}
=== Interrupt Vector Offset ($B0 write) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Vector Request}}
=== Interrupt Vector Request ($B0 read) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.
&lt;/pre&gt;

* Bits &lt;code&gt;3 .. 7&lt;/code&gt; of this will always equal the user-provided vector offset.
* Bits &lt;code&gt;0 .. 2&lt;/code&gt; of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal &lt;code&gt;0&lt;/code&gt;.

{{Anchor|Interrupt Enable}}
=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

{{Anchor|Interrupt Status}}
=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>20815c76159f41c73341fb4cd2b5dbb9d96a50b7</sha1>
  </revision>
  <revision>
    <id>246</id>
    <parentid>220</parentid>
    <timestamp>2024-02-08T22:18:17Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>/* Interrupt Vector Offset ($B0 write) */ Formatting.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2851" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector Offset}}
=== Interrupt Vector Offset ($B0 write) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| |
++++-+---- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Vector Request}}

=== Interrupt Vector Request ($B0 read) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.
&lt;/pre&gt;

* Bits &lt;code&gt;3 .. 7&lt;/code&gt; of this will always equal the user-provided vector offset.
* Bits &lt;code&gt;0 .. 2&lt;/code&gt; of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal &lt;code&gt;0&lt;/code&gt;.

{{Anchor|Interrupt Enable}}
=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

{{Anchor|Interrupt Status}}
=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>aa800009ef2735c9fddcb46077a282361de2c48a</sha1>
  </revision>
  <revision>
    <id>247</id>
    <parentid>246</parentid>
    <timestamp>2024-02-08T22:19:42Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <minor/>
    <comment>/* Interrupt Vector Request ($B0 read) */ Bit direction (high to low).</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2852" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
** Edge - will only be requested when the prerequisite condition ''becomes'' true; acknowledging the interrupt prevents further interruption.

The user can additionally define and use any of the 256 interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector Offset}}
=== Interrupt Vector Offset ($B0 write) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| |
++++-+---- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Vector Request}}

=== Interrupt Vector Request ($B0 read) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.
&lt;/pre&gt;

* Bits &lt;code&gt;7 .. 3&lt;/code&gt; of this will always equal the user-provided vector offset.
* Bits &lt;code&gt;2 .. 0&lt;/code&gt; of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal &lt;code&gt;0&lt;/code&gt;.

{{Anchor|Interrupt Enable}}

=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

{{Anchor|Interrupt Status}}
=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>531e6603789f1b5d9b5d1b32d3e29e2d820b5fe1</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>Memory map</title>
  <ns>0</ns>
  <id>25</id>
  <revision>
    <id>225</id>
    <parentid>93</parentid>
    <timestamp>2023-08-30T17:33:44Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3654" xml:space="preserve">The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
! rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

Remember that just because an element exists in memory, it doesn't have to be fully utilized; for example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space.

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>54e83a69cd08da7c36b7aa1d01f5bb22266a4b79</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>DMA</title>
  <ns>0</ns>
  <id>31</id>
  <revision>
    <id>229</id>
    <parentid>145</parentid>
    <timestamp>2023-08-30T20:38:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3464" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of a transfer.

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t r?ff
|| | | ||
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>f7213bdf3e3bc506340f6c8578ba016cf0aece96</sha1>
  </revision>
  <revision>
    <id>231</id>
    <parentid>229</parentid>
    <timestamp>2023-09-01T14:14:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document SDMA hold and bus behaviour</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3937" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of a transfer.

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

== Sound DMA ==

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

Sound DMA supports ''holding'' - if enabled, the offset/length counters will be paused, allowing for resuming without losing auto-repeat state. The DMA cycles still occur, but they write &lt;code&gt;$00&lt;/code&gt; to the target port instead of the in-memory value.

While General DMA uses word access, Sound DMA uses byte access. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens Sound DMA by the difference.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>1c976f5961ec78bdd2d5e5f18c693cc5781aa3f1</sha1>
  </revision>
  <revision>
    <id>235</id>
    <parentid>231</parentid>
    <timestamp>2023-09-02T13:20:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4008" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of a transfer.

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

== Sound DMA ==

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

Sound DMA supports ''holding'' - if enabled, the offset/length counters will be paused, allowing for resuming without losing auto-repeat state. The DMA cycles still occur, but they write &lt;code&gt;$00&lt;/code&gt; to the target port instead of the in-memory value.

Sound DMA support ''repeat'' - if enabled, the offset/length counter will have their last written values restored upon the length counter reaching 0. The offset/length counters are copied when their respective ports are written to.

While General DMA uses word access, Sound DMA uses byte access. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens Sound DMA by the difference.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>f4b79c22e2b9f96e40fe2245bdee91ebe14d1f2f</sha1>
  </revision>
  <revision>
    <id>236</id>
    <parentid>235</parentid>
    <timestamp>2023-09-02T13:30:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4195" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of a transfer.

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

== Sound DMA ==

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

Sound DMA supports ''holding'' - if enabled, the offset/length counters will be paused, allowing for resuming without losing auto-repeat state. The DMA cycles still occur, but they write &lt;code&gt;$00&lt;/code&gt; to the target port instead of the in-memory value.

Sound DMA supports ''repeat'' - if enabled, the offset/length counter will have their last written values restored upon the length counter reaching 0. The offset/length counters are copied when their respective ports are written to.

While General DMA uses word access, Sound DMA uses byte access. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens Sound DMA by the difference.

Sound DMA updates offset/length counters live; the changed values are accessible through the respective I/O ports, and written changes are immediately reflected in the DMA's behaviour.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>33b28c32db8eb9d48009d2e6c1b46df5e51484f6</sha1>
  </revision>
  <revision>
    <id>237</id>
    <parentid>236</parentid>
    <timestamp>2023-09-02T15:27:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4401" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of a transfer.

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

== Sound DMA ==

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles &lt;code&gt;{117, 118, 119, 120, 121, 122, 123} mod 128&lt;/code&gt;.

Sound DMA supports ''holding'' - if enabled, the offset/length counters will be paused, allowing for resuming without losing auto-repeat state. The DMA cycles still occur, but they write &lt;code&gt;$00&lt;/code&gt; to the target port instead of the in-memory value.

Sound DMA supports ''repeat'' - if enabled, the offset/length counter will have their last written values restored upon the length counter reaching 0. The offset/length counters are copied when their respective ports are written to.

While General DMA uses word access, Sound DMA uses byte access. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens Sound DMA by the difference.

Sound DMA updates offset/length counters live; the changed values are accessible through the respective I/O ports, and written changes are immediately reflected in the DMA's behaviour.

The enable/disable bit of Sound DMA does not affect the offset/length counters in any way; for example, if a sample is stopped mid-playthrough, then started again, it will pick up right where it left off.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>ba578dcd1b3ccf3488aec9caa3052ca65e22f411</sha1>
  </revision>
  <revision>
    <id>238</id>
    <parentid>237</parentid>
    <timestamp>2023-09-02T15:34:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4998" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of a transfer.

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

The CPU is stalled immediately after General DMA is enabled. General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

== Sound DMA ==

Sound DMA allows copying sample data to either Channel 2 or Hyper Voice automatically while incurring a much lower cost than that of a CPU interrupt.

Features:

* 4000, 6000, 12000, 24000 Hz sample rates.
* '''Auto-repeat''': If enabled, every time the length counter reaches 0, a shadowed copy of the offset and length as written to the I/O ports will be restored. If disabled, bit 7 will automatically clear on transfer completion, same as with General DMA.
* '''Holding''': If enabled, the offset/length counters will be paused, and $00 will be written on every Sound DMA tick as opposed to the value in memory. This does not impact the timing of Sound DMA.

When playing back sound, the visible ports ($4A-$4C, $4E-$50) are the ones updated live; any edits to them are reflected immediately, as well as written to the shadow copy used for auto-repeat.

The enable/disable bit of Sound DMA does not affect the offset/length counters in any way; for example, if a sample is stopped mid-playthrough, then started again, it will pick up right where it left off.

Unlike General DMA, Sound DMA copies data per byte. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens the duration of Sound DMA. Due to its need to access the external cartridge bus, Sound DMA must use cycles normally reserved for the CPU; it uses &lt;code&gt;6 + N&lt;/code&gt; cycles every 128 cycles, always starting from cycle &lt;code&gt;117 mod 128&lt;/code&gt;. &lt;code&gt;N&lt;/code&gt; refers to the access time of the area from which audio is being streamed from, and is typically 1 cycle.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>3053a97e9d2b0b92388d4b96ecef0b55c88ead08</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>WonderWitch/FreyaBIOS</title>
  <ns>0</ns>
  <id>42</id>
  <revision>
    <id>239</id>
    <parentid>182</parentid>
    <timestamp>2023-09-09T06:07:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add Fonts section</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1398" xml:space="preserve">FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.

It provides the following functionality:

* bring-up code,
* interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware,
* 8x8 ASCII and kanji fonts,
* a monitor program, allowing FreyaOS recovery and updates via XMODEM.

Other functionality (like file system access) is instead included as part of [[WonderWitch/FreyaOS|FreyaOS]]' system libraries; some other functionality (like WonderSwan Color support is implemented as part of the development tooling.

== Revisions ==

TODO

== Fonts ==

As part of its ROM image, FreyaBIOS provides two fonts:

* an 8x8 ASCII font,
* an 8x8 Shift-JIS kanji font - [http://hp.vector.co.jp/authors/VA002310/original.html ELISA FONT].

== Interrupts ==

* [[WonderWitch/FreyaBIOS/Exit|Exit]] (INT $10)
* [[WonderWitch/FreyaBIOS/Key|Key]] (INT $11)
* [[WonderWitch/FreyaBIOS/Display|Display]] (INT $12)
* [[WonderWitch/FreyaBIOS/Text|Text]] (INT $13)
* [[WonderWitch/FreyaBIOS/Communication|Communication]] (INT $14)
* [[WonderWitch/FreyaBIOS/Sound|Sound]] (INT $15)
* [[WonderWitch/FreyaBIOS/Timer|Timer]] (INT $16)
* [[WonderWitch/FreyaBIOS/System|System]] (INT $17)
* [[WonderWitch/FreyaBIOS/Bank|Bank]] (INT $18)

== Freya Monitor ==

TODO</text>
    <sha1>296072457def02e62380fd6d12d7ed5390a700bf</sha1>
  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>WonderWitch .fx files</title>
  <ns>0</ns>
  <id>6</id>
  <revision>
    <id>240</id>
    <parentid>16</parentid>
    <timestamp>2023-09-09T06:15:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>fix formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1426" xml:space="preserve">[[FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.

== Format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;code&gt;#!ws&lt;/code&gt;
|-
| $04 || 60 || Padding; typically 0xFF.
|-
| $40 || 16 || File name; zero-terminated Shift-JIS string.
|-
| $50 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| $68 || 4 || ?
|-
| $6C || 4 || Total file size, in bytes, excluding the header.
|-
| $70 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| $72 || 2 || File mode
|-
| $74 || 4 || Modification time - seconds since January 1st, 2000.
|-
| $78 || 4 || ?
|-
| $7C || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== File mode ===
----
&lt;pre&gt;

15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  ??i? ?rwx
              |   |||
              |   ||+- Execute
              |   |+-- Write
              |   +--- Read
              +------- Intermediate library
&lt;/pre&gt;</text>
    <sha1>70db9f39d629134f64dabbb28838e102b2f6fb7f</sha1>
  </revision>
  <revision>
    <id>241</id>
    <parentid>240</parentid>
    <timestamp>2023-09-09T06:15:44Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1425" xml:space="preserve">[[FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.

== Format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;code&gt;#!ws&lt;/code&gt;
|-
| $04 || 60 || Padding; typically 0xFF.
|-
| $40 || 16 || File name; zero-terminated Shift-JIS string.
|-
| $50 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| $68 || 4 || ?
|-
| $6C || 4 || Total file size, in bytes, excluding the header.
|-
| $70 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| $72 || 2 || File mode
|-
| $74 || 4 || Modification time - seconds since January 1st, 2000.
|-
| $78 || 4 || ?
|-
| $7C || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== File mode ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  ??i? ?rwx
              |   |||
              |   ||+- Execute
              |   |+-- Write
              |   +--- Read
              +------- Intermediate library
&lt;/pre&gt;</text>
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  </revision>
</page>
<page arvcontinue="20230827105254|201">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>242</id>
    <parentid>122</parentid>
    <timestamp>2023-09-23T15:22:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4877" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || ?
|-
| $2F || HTR || ?
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || 64 Kbit (8 KiB)
|-
| $02 || 256 Kbit (32 KiB)
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
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  <title>Cartridge connector</title>
  <ns>0</ns>
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    <id>243</id>
    <parentid>191</parentid>
    <timestamp>2023-10-10T19:58:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix typo</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1371" xml:space="preserve">
== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /Reset
... |  | -41| -&gt; /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK  (384 KHz clock)
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;</text>
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    <id>248</id>
    <parentid>243</parentid>
    <timestamp>2024-02-19T19:55:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>Asie moved page [[Cartridge pinout]] to [[Cartridge connector]]: Unify with NESdev/SNESdev Wiki standards</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1371" xml:space="preserve">
== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /Reset
... |  | -41| -&gt; /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK  (384 KHz clock)
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;</text>
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  <title>Cartridge pinout</title>
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    <id>249</id>
    <timestamp>2024-02-19T19:55:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Asie moved page [[Cartridge pinout]] to [[Cartridge connector]]: Unify with NESdev/SNESdev Wiki standards</comment>
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    <text bytes="33" xml:space="preserve">#REDIRECT [[Cartridge connector]]</text>
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  <title>Cartridge connector</title>
  <ns>0</ns>
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    <id>251</id>
    <parentid>248</parentid>
    <timestamp>2024-02-19T20:21:49Z</timestamp>
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      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>expanded with RSDuck's notes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4732" xml:space="preserve">== Memory access ==

Both the ROM and the SRAM chip use a standard asynchronous memory interface.

It is presumed that:

* the CPU sets the address lines after the rising edge of '''/OE''' while '''/OE''' is high,
* the CPU sets the data lines after the falling edge of '''/OE''', while '''/OE''' is low (TODO: only confirmed for I/O writes),
* the CPU latches the data lines on the subsequent rising edge of '''/OE'''.

Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.

Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.

== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /RESET
... |  | -41| -&gt; /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;

== Mechanical details ==

{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}

== Signal descriptions ==

* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.

== Timing requirements ==

The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.

TODO: Verify how using ROM/SRAM wait states affects this.

== Authentication handshake ==

Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:

* '''/MBC''' is held high.
* On the rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: &lt;code&gt;1000101000101000000111&lt;/code&gt;.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.

On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.

An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].</text>
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  </revision>
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    <id>252</id>
    <parentid>251</parentid>
    <timestamp>2024-02-19T20:25:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4803" xml:space="preserve">== Memory access ==

Both the ROM and the SRAM chip use a standard asynchronous memory interface.

It is presumed that:

* the CPU sets the address lines after the rising edge of '''/OE''' while '''/OE''' is high,
* the CPU sets the data lines after the falling edge of '''/OE''', while '''/OE''' is low (TODO: only confirmed for I/O writes),
* the CPU latches the data lines on the subsequent rising edge of '''/OE'''.

Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.

Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.

== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /RESET
... |  | -41| -&gt; /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;

== Mechanical details ==

{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}

== Signal descriptions ==

* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.

== Timing requirements ==

The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.

TODO: Verify how using ROM/SRAM wait states affects this.

== Authentication handshake ==

Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:

* '''/MBC''' is held high. '''A0'''-'''A3''' are set to 0xA and '''A16'''-'''A19''' are set to 0x5.
* On a rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: &lt;code&gt;1000101000101000000111&lt;/code&gt;.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.

On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.

An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].</text>
    <sha1>423f6189b4f995d2da11047d47223398549307c8</sha1>
  </revision>
  <revision>
    <id>254</id>
    <parentid>252</parentid>
    <timestamp>2024-02-20T08:51:05Z</timestamp>
    <contributor>
      <username>Generic</username>
      <id>362</id>
    </contributor>
    <comment>clarify when which signals change</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4823" xml:space="preserve">== Memory access ==

Both the ROM and the SRAM chip use a standard asynchronous memory interface.

It is presumed that:

* the CPU sets the address lines before each memory access while '''/OE''' or '''/WE''' respectively are still high,
* for writes the CPU sets the data lines with the falling edge of '''/WE''' (TODO: only confirmed for I/O writes),
* for reads the CPU latches the data lines on the subsequent rising edge of '''/OE'''.

Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.

Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.

== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /RESET
... |  | -41| -&gt; /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;

== Mechanical details ==

{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}

== Signal descriptions ==

* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.

== Timing requirements ==

The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.

TODO: Verify how using ROM/SRAM wait states affects this.

== Authentication handshake ==

Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:

* '''/MBC''' is held high. '''A0'''-'''A3''' are set to 0xA and '''A16'''-'''A19''' are set to 0x5.
* On a rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: &lt;code&gt;1000101000101000000111&lt;/code&gt;.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.

On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.

An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].</text>
    <sha1>9fb3c63065f63e54a75118ad50edcddb9cc1dffe</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>Bandai 2003</title>
  <ns>0</ns>
  <id>13</id>
  <revision>
    <id>253</id>
    <parentid>170</parentid>
    <timestamp>2024-02-19T20:27:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4412" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessible at segment 0x1000;
0 = RAM instead.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.
|}

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.

== 2003 RTC interface ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

(Put logic analyzer traces here)

Values are as follows:

=== $00-$0F, $1C-$1F ===
Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

=== $10, $11 ===
Send command byte ($60 or $61 respectively) and stop.

=== $12 ===
Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

=== $13 ===
Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

=== $14 ===
Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the ''first'' byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

=== $15 ===
Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

=== $16 ===
Send command byte ($66), then send three bytes of payload, then stop.

=== $17 ===
Send command byte ($67), then receive three bytes of payload, then stop.

=== $18, $1A ===
Send command byte ($68 or $6A), then send two bytes of payload, then stop.

=== $19, $1B ===
Send command byte ($69 or $6B), then receive two bytes of payload, then stop.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>1cecca796fa1e97a8801d1c17f659a04a6a68714</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>255</id>
    <parentid>206</parentid>
    <timestamp>2024-03-15T17:32:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Tiles */ Fix chunky/packed mode documentation</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="12348" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky (packed) mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 byte N       byte N+1     byte N+2     byte N+3
pxl0 pxl1    pxl2 pxl3    pxl4 pxl5    pxl6 pxl7
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.42. .421    .4.. .4.1    ..2. ..21    .... ...1  --\  7654321.
8..1 8...    8.21 8.2.    84.1 84..    8421 842.  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}
=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>1d1d01156c67d9d5053ae21e2a843fa6809cd57b</sha1>
  </revision>
  <revision>
    <id>256</id>
    <parentid>255</parentid>
    <timestamp>2024-03-15T17:33:40Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="12348" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky (packed) mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 byte N       byte N+1     byte N+2     byte N+3
pxl0 pxl1    pxl2 pxl3    pxl4 pxl5    pxl6 pxl7
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.421 .42.    .4.1 .4..    ..21 ..2.    ...1 ....  --\  7654321.
8... 8..1    8.2. 8.21    84.. 84.1    842. 8421  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart. By default, this should be set to 158.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}
=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>fdb999a44a5a9735973b72157c6dd0969878069e</sha1>
  </revision>
  <revision>
    <id>296</id>
    <parentid>256</parentid>
    <timestamp>2024-07-10T18:45:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* LCD Final Line ($16) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="12418" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky (packed) mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 byte N       byte N+1     byte N+2     byte N+3
pxl0 pxl1    pxl2 pxl3    pxl4 pxl5    pxl6 pxl7
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.421 .42.    .4.1 .4..    ..21 ..2.    ...1 ....  --\  7654321.
8... 8..1    8.2. 8.21    84.. 84.1    842. 8421  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>79df6403eb2df6d3c14148ede560698806c76d63</sha1>
  </revision>
  <revision>
    <id>297</id>
    <parentid>296</parentid>
    <timestamp>2024-07-10T18:47:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal I/O ports */ fix references</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="12418" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The "mono" WonderSwan can display up to 512 tiles stored in a planar format, with two bits total per pixel.

The planes are interleaved with each other; that is, two consecutive bytes form a full 8x1 row of the tile:

&lt;pre&gt;
 plane 0      plane 1
 byte N       byte N+1
7  bit  0    7  bit  0      full tile
---- ----    ---- ----
.... ...1    .222 22..       .22222.1
.... ...1    2222 22..       222222.1
.... ....    22.. ....       22......
...1 1...    22.2 2...  --\  22.33...
...1 1...    22.2 2...  --/  22.33...
.... ....    22.. ....       22......
.... ....    .... ....       ........
11.. ....    .... ....       11......
&lt;/pre&gt;

The WonderSwan Color extends this with an additional 512 tiles (available for screens only, not sprites) and support for three new modes.

* The first new mode is another two bit per pixel mode, but using color palettes instead of monochrome shades.

The latter two modes extend tiles to four bits per pixel.

* The first among them is the planar mode, which works similarly to the two bit per pixel mode:

&lt;pre&gt;
 plane 0      plane 1      plane 2      plane 3
 byte N       byte N+1     byte N+2     byte N+3
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
1.1. 1.1.    22.. 22..    4444 ....    .... ....  --\  7654321.
.1.1 .1.1    ..22 ..22    .... 4444    8888 8888  --/  89ABCDEF
&lt;/pre&gt;

* The second is the chunky (packed) mode, which instead stores each plane as consecutive bits, with each byte responsible for two of the eight pixels:

&lt;pre&gt;
 byte N       byte N+1     byte N+2     byte N+3
pxl0 pxl1    pxl2 pxl3    pxl4 pxl5    pxl6 pxl7
7  bit  0    7  bit  0    7  bit  0    7  bit  0      full rows
---- ----    ---- ----    ---- ----    ---- ----
.421 .42.    .4.1 .4..    ..21 ..2.    ...1 ....  --\  7654321.
8... 8..1    8.2. 8.21    84.. 84.1    842. 8421  --/  89ABCDEF
&lt;/pre&gt;

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>704d2dfb34790d97ae068ee8ff03e8e6d9743044</sha1>
  </revision>
  <revision>
    <id>298</id>
    <parentid>297</parentid>
    <timestamp>2024-07-12T19:25:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Tiles */ rewrite the whole thing to be more clear</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="14584" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248.
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448..
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Colors, Shades ===

The "mono" WonderSwan uses eight value indices, which are converted by a global look-up table to eight of the sixteen shades the LCD can display:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Tile pixel      Value                        Displayed shade
&lt;/pre&gt;

In "color" mode, the WonderSwan instead loads RGB444 color values from a table in the console's internal RAM:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

No further processing or look-up tables are applied.

=== Palettes ===

The WonderSwan provides sixteen different palettes. All sixteen can be used for screens only, while the latter eight can be used for screens and sprites. In addition, the background color (for areas where no opaque pixel is drawn) can be selected arbitrarily from the color palette or from the shade LUT.

In two bit per pixel modes, palettes 0 - 3 and 8 - 11 are ''opaque'' (color zero is opaque, four distinct colors are usable), while palettes 4 - 7 and 12 - 15 are ''translucent'' (color zero is transparent, three distinct colors are usable). This applies in both mono and color modes.

In four bit per pixel modes, every palette is ''translucent'' (color zero is transparent, fifteen distinct colors are usable). The first entry of each palette can be used only for the background color.

Palettes 8-15 are also referred to as sprite palettes 0-7.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

Finally, the WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>9690497871a4cbee439f89ae7b116726a6384a12</sha1>
  </revision>
  <revision>
    <id>299</id>
    <parentid>298</parentid>
    <timestamp>2024-07-12T19:37:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Components */ rewrite the palette section too</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15261" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248.
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448..
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The WonderSwan provides sixteen different palettes. Palettes 0-7 can be used for the two screens only, while palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++- Index in palette (0-15)
         +--+++------ Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

- Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
- Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

- In mono modes, it is set to an entry in the shade lookup table (0-7),
- In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>a87d911b2933cc02d657ffe56a0575202f1450b3</sha1>
  </revision>
  <revision>
    <id>300</id>
    <parentid>299</parentid>
    <timestamp>2024-07-12T19:38:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15393" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The WonderSwan provides sixteen different palettes. Palettes 0-7 can be used for the two screens only, while palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++- Index in palette (0-15)
         +--+++------ Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

- Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
- Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

- In mono modes, it is set to an entry in the shade lookup table (0-7),
- In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>8d6668a9c78f70d4093ea0b83291a52468d370a4</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>WonderWitch/FreyaOS</title>
  <ns>0</ns>
  <id>49</id>
  <revision>
    <id>257</id>
    <timestamp>2024-03-17T05:54:09Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "FreyaOS is an operating system and library set for [[WonderWitch]], present in the second-to-last 64 KB of any WonderWitch cartridge.  It provides the following library functionality:  * process management, * file system access, * [[WonderWitch/IL|IL]] library management.  It additionally provides an user interface, which allows launching programs and performing file management/transfer operations.  == Revisions ==  * FreyaOS 1.0.0 * FreyaOS 1.0.2 (September 2nd, 2000 &lt;r..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1912" xml:space="preserve">FreyaOS is an operating system and library set for [[WonderWitch]], present in the second-to-last 64 KB of any WonderWitch cartridge.

It provides the following library functionality:

* process management,
* file system access,
* [[WonderWitch/IL|IL]] library management.

It additionally provides an user interface, which allows launching programs and performing file management/transfer operations.

== Revisions ==

* FreyaOS 1.0.0
* FreyaOS 1.0.2 (September 2nd, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00001.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.0.3 (November 1st, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00004.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.1.0 (December 24th, 2000 &lt;ref name="history2001"&gt;[http://wonderwitch.qute.co.jp/history200107.htm WonderWitch これまでの歩み]&lt;/ref&gt;)
* FreyaOS 1.1.1 (February 7th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.2 (June 20th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.3 (June 26th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.4 (September 27th, 2001 &lt;ref name="history2002"&gt;[http://wonderwitch.qute.co.jp/history200207.htm WonderWitch これまでの歩み 2002]&lt;/ref&gt;)
* FreyaOS 1.1.5 (March 5th, 2002 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.6 beta1 (April 30th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00321.html FreyaOS βバージョン提供のお知らせ]&lt;/ref&gt;)
** Fixed IRAM corruption when calling ''open()''/''stat()'' after initializing SoundIL.
* FreyaOS 1.2.0 (July 13th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/index_wwp.html WonderWitchプレーヤー サポートページ]&lt;/ref&gt;)
** Validated for SwanCrystal consoles.
* FreyaOS 1.2.0S
** Special, stripped-down version of FreyaOS 1.2.0 used on pre-programmed Judgement Silversword and Dicing Knight cartridges.

== Notes ==

&lt;references /&gt;</text>
    <sha1>299619a0c8ce55fa1b91f2feaf339fc18cab3928</sha1>
  </revision>
  <revision>
    <id>258</id>
    <parentid>257</parentid>
    <timestamp>2024-03-17T05:54:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1912" xml:space="preserve">FreyaOS is an operating system and library set for [[WonderWitch]], present in the second-to-last 64 KB of any WonderWitch cartridge.

It provides the following library functionality:

* process management,
* file system access,
* [[WonderWitch/IL|IL]] library management.

It additionally provides an user interface, which allows launching programs and performing file management/transfer operations.

== Revisions ==

* FreyaOS 1.0.0
* FreyaOS 1.0.2 (September 2nd, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00001.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.0.3 (November 1st, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00004.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.1.0 (December 24th, 2000 &lt;ref name="history2001"&gt;[http://wonderwitch.qute.co.jp/history200107.htm WonderWitch これまでの歩み]&lt;/ref&gt;)
* FreyaOS 1.1.1 (February 7th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.2 (June 20th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.3 (June 26th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.4 (September 27th, 2001 &lt;ref name="history2002"&gt;[http://wonderwitch.qute.co.jp/history200207.htm WonderWitch これまでの歩み 2002]&lt;/ref&gt;)
* FreyaOS 1.1.5 (March 5th, 2002 &lt;ref name="history2002"/&gt;)
* FreyaOS 1.1.6 beta1 (April 30th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00321.html FreyaOS βバージョン提供のお知らせ]&lt;/ref&gt;)
** Fixed IRAM corruption when calling ''open()''/''stat()'' after initializing SoundIL.
* FreyaOS 1.2.0 (July 13th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/index_wwp.html WonderWitchプレーヤー サポートページ]&lt;/ref&gt;)
** Validated for SwanCrystal consoles.
* FreyaOS 1.2.0S
** Special, stripped-down version of FreyaOS 1.2.0 used on pre-programmed Judgement Silversword and Dicing Knight cartridges.

== Notes ==

&lt;references /&gt;</text>
    <sha1>38907a0014bd1d47b10ef1d878ebd333d1bcd0a8</sha1>
  </revision>
  <revision>
    <id>260</id>
    <parentid>258</parentid>
    <timestamp>2024-03-17T05:59:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1978" xml:space="preserve">FreyaOS is an operating system and library set for [[WonderWitch]], present in the second-to-last 64 KB of any WonderWitch cartridge.

It provides the following library functionality:

* process management,
* file system access,
* [[WonderWitch/IL|IL]] library management.

It additionally provides an user interface, which allows launching programs and performing file management/transfer operations.

== Revisions ==

* FreyaOS 1.0.0
* FreyaOS 1.0.2 (September 2nd, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00001.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.0.3 (November 1st, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00004.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.1.0 (December 24th, 2000 &lt;ref name="history2001"&gt;[http://wonderwitch.qute.co.jp/history200107.htm WonderWitch これまでの歩み]&lt;/ref&gt;)
* FreyaOS 1.1.1 (February 7th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.2 (June 20th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.3 (June 26th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.4 (September 27th, 2001 &lt;ref name="history2002"&gt;[http://wonderwitch.qute.co.jp/history200207.htm WonderWitch これまでの歩み 2002]&lt;/ref&gt;)
* FreyaOS 1.1.5 (March 5th, 2002 &lt;ref name="history2002"/&gt;)
* FreyaOS 1.1.6 beta1 (April 30th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00321.html FreyaOS βバージョン提供のお知らせ]&lt;/ref&gt;)
** Fixed IRAM corruption when calling ''open()''/''stat()'' after initializing SoundIL.
* FreyaOS 1.2.0 (July 13th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/index_wwp.html WonderWitchプレーヤー サポートページ]&lt;/ref&gt;)
** Validated for SwanCrystal consoles.
* FreyaOS 1.2.0S
** Special, stripped-down version of FreyaOS 1.2.0 used on pre-programmed Judgement Silversword and Dicing Knight cartridges.

== Documentation ==

* [[WonderWitch .fx files|.fx file format]]

== Notes ==

&lt;references /&gt;</text>
    <sha1>b43f4b45d5f03774a8eea8a1634aabfe410421e0</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>WonderWitch .fx files</title>
  <ns>0</ns>
  <id>6</id>
  <revision>
    <id>259</id>
    <parentid>241</parentid>
    <timestamp>2024-03-17T05:59:09Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1445" xml:space="preserve">[[WonderWitch/FreyaOS|FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.

== Format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;code&gt;#!ws&lt;/code&gt;
|-
| $04 || 60 || Padding; typically 0xFF.
|-
| $40 || 16 || File name; zero-terminated Shift-JIS string.
|-
| $50 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| $68 || 4 || ?
|-
| $6C || 4 || Total file size, in bytes, excluding the header.
|-
| $70 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| $72 || 2 || File mode
|-
| $74 || 4 || Modification time - seconds since January 1st, 2000.
|-
| $78 || 4 || ?
|-
| $7C || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== File mode ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  ??i? ?rwx
              |   |||
              |   ||+- Execute
              |   |+-- Write
              |   +--- Read
              +------- Intermediate library
&lt;/pre&gt;</text>
    <sha1>29cc8fb61f943a9cd919df2e7bf3d3e117f8104f</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>WonderWitch</title>
  <ns>0</ns>
  <id>41</id>
  <revision>
    <id>261</id>
    <parentid>180</parentid>
    <timestamp>2024-03-17T06:05:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1821" xml:space="preserve">The WonderWitch is an official homebrew development kit released by Qute Corporation on July 18th, 2000.

== Hardware ==

The WonderWitch cartridge is based on the [[Bandai 2003]] mapper. It provides an RTC, as well as NOR self-flashing functionality using the Fujitsu MBM29DL400TC chip.

There were three ways available to acquire WonderWitch cartridges:

* '''WonderWitch''', a software development kit containing a reflashable cartridge, a WonderSwan&lt;-&gt;RS-232 adapter, a development manual and a development tool CD;
* '''WonderWitch Player''', a priced-down user-only version omitting the development manual and tooling;
* The VAR program, allowing independent creators to buy reflashable cartridges in bulk, in units of 20 or 100.

== Software ==

=== Interrupt vectors ===

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|-
| 0x19
| 0x27
|
|-
| 0x28
| 0x2F
| SoC interrupts
|-
| 0x30
| 0x32
| [[WonderWitch/FreyaOS|FreyaOS]] interrupts
|}

=== Memory layout ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/File system|File system]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}

Internal console RAM is generally managed by [[WonderWitch/FreyaBIOS|FreyaBIOS]], while SRAM is managed by [[WonderWitch/FreyaOS|FreyaOS]].

== Development Tools ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Fujitsu MBM29DL400TC datasheet]</text>
    <sha1>acc5c0ac8e8da6f06edfa2a58dbdc08759bf56fa</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>Hyper Voice</title>
  <ns>0</ns>
  <id>30</id>
  <revision>
    <id>262</id>
    <parentid>218</parentid>
    <timestamp>2024-03-24T06:36:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document volume/mode interplay</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2768" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68 write) ===

=== Hyper Voice Right Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Volume scaling algorithm:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Write 1 to reset DMA input channel to left
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

{| class="wikitable"
|+ Volume scaling algorithms - resulting sample ranges
! Algorithm/Volume
! 100%
! 50%
! 25%
! 12.5%
|-
| Unsigned
| 0x0000 .. 0xFFFF
| 0x8000 .. 0xFFFF
| 0x8000 .. 0xBFFF
| 0x8000 .. 0x9FFF
|-
| Unsigned, negated
| 0x0000 .. 0xFFFF
| 0x0000 .. 0x7FFF
| 0x4000 .. 0x7FFF
| 0x6000 .. 0x7FFF
|-
| Signed
| 0x0000 .. 0xFFFF
| 0x4000 .. 0xBFFF
| 0x6000 .. 0x9FFF
| 0x7000 .. 0x8FFF
|-
| Ignored
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
|}</text>
    <sha1>839e753360d79e723480b8cf3712cb5ddbe56556</sha1>
  </revision>
  <revision>
    <id>263</id>
    <parentid>262</parentid>
    <timestamp>2024-03-24T06:37:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Hyper Voice Control ($6A, $6B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2841" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68 write) ===

=== Hyper Voice Right Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Volume scaling algorithm:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
                              will be used for the left channel.
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

{| class="wikitable"
|+ Volume scaling algorithms - resulting sample ranges
! Algorithm/Volume
! 100%
! 50%
! 25%
! 12.5%
|-
| Unsigned
| 0x0000 .. 0xFFFF
| 0x8000 .. 0xFFFF
| 0x8000 .. 0xBFFF
| 0x8000 .. 0x9FFF
|-
| Unsigned, negated
| 0x0000 .. 0xFFFF
| 0x0000 .. 0x7FFF
| 0x4000 .. 0x7FFF
| 0x6000 .. 0x7FFF
|-
| Signed
| 0x0000 .. 0xFFFF
| 0x4000 .. 0xBFFF
| 0x6000 .. 0x9FFF
| 0x7000 .. 0x8FFF
|-
| Ignored
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
|}</text>
    <sha1>449ec68ecb8b401b14cc64627d454771d454567e</sha1>
  </revision>
  <revision>
    <id>264</id>
    <parentid>263</parentid>
    <timestamp>2024-03-24T06:37:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Hyper Voice Control ($6A, $6B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2841" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68 write) ===

=== Hyper Voice Right Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Volume scaling algorithm:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
  ||                          will be used for the left channel.
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

{| class="wikitable"
|+ Volume scaling algorithms - resulting sample ranges
! Algorithm/Volume
! 100%
! 50%
! 25%
! 12.5%
|-
| Unsigned
| 0x0000 .. 0xFFFF
| 0x8000 .. 0xFFFF
| 0x8000 .. 0xBFFF
| 0x8000 .. 0x9FFF
|-
| Unsigned, negated
| 0x0000 .. 0xFFFF
| 0x0000 .. 0x7FFF
| 0x4000 .. 0x7FFF
| 0x6000 .. 0x7FFF
|-
| Signed
| 0x0000 .. 0xFFFF
| 0x4000 .. 0xBFFF
| 0x6000 .. 0x9FFF
| 0x7000 .. 0x8FFF
|-
| Ignored
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
|}</text>
    <sha1>7e08f2874cfda2a5a7952faba7e9df2dd8d6f845</sha1>
  </revision>
  <revision>
    <id>265</id>
    <parentid>264</parentid>
    <timestamp>2024-03-24T12:52:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3034" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Left Input ($68 write) ===

=== Hyper Voice Right Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- 8-bit sample.
&lt;/pre&gt;

These are typically written to by [[DMA|Sound DMA]], but can also be written to manually by the user.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Sample scaling mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
  ||                          will be used for the left channel.
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

Input samples are treated as signed 8-bit values. If volume is not 100% and sample scaling mode is not ignored, they may instead be treated as unsigned and/or be rescaled to the following value ranges:

{| class="wikitable"
|+ Sample scaling modes - resulting sample ranges
! Algorithm/Volume
! 100%
! 50%
! 25%
! 12.5%
|-
| Unsigned
| 0x0000 .. 0xFFFF
| 0x8000 .. 0xFFFF
| 0x8000 .. 0xBFFF
| 0x8000 .. 0x9FFF
|-
| Unsigned, negated
| 0x0000 .. 0xFFFF
| 0x0000 .. 0x7FFF
| 0x4000 .. 0x7FFF
| 0x6000 .. 0x7FFF
|-
| Signed
| 0x0000 .. 0xFFFF
| 0x4000 .. 0xBFFF
| 0x6000 .. 0x9FFF
| 0x7000 .. 0x8FFF
|-
| Ignored
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
|}</text>
    <sha1>cfe5292c8884f73d041673cb37934ef75a4633a7</sha1>
  </revision>
  <revision>
    <id>266</id>
    <parentid>265</parentid>
    <timestamp>2024-03-24T13:50:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3158" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Signed 8-bit sample.
&lt;/pre&gt;

Hyper Voice samples are typically written by [[DMA|Sound DMA]], but can also be written manually by the user. In the latter case, the "channel mode" setting is ignored - it always behaves as if it were in "stereo" mode, writing one channel after the other in sequence.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Sample scaling mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
  ||                          will be used for the left channel.
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

Input samples are treated as signed 8-bit values. If volume is not 100% and sample scaling mode is not ignored, they may instead be treated as unsigned and/or be rescaled to the following value ranges:

{| class="wikitable"
|+ Sample scaling modes - resulting sample ranges
! Algorithm/Volume
! 100%
! 50%
! 25%
! 12.5%
|-
| Unsigned
| 0x0000 .. 0xFFFF
| 0x8000 .. 0xFFFF
| 0x8000 .. 0xBFFF
| 0x8000 .. 0x9FFF
|-
| Unsigned, negated
| 0x0000 .. 0xFFFF
| 0x0000 .. 0x7FFF
| 0x4000 .. 0x7FFF
| 0x6000 .. 0x7FFF
|-
| Signed
| 0x0000 .. 0xFFFF
| 0x4000 .. 0xBFFF
| 0x6000 .. 0x9FFF
| 0x7000 .. 0x8FFF
|-
| Ignored
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
| 0x0000 .. 0xFFFF
|}</text>
    <sha1>d7ce4578dfd2acba817e8e14e30c222236da97c3</sha1>
  </revision>
  <revision>
    <id>271</id>
    <parentid>266</parentid>
    <timestamp>2024-03-29T14:52:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Hyper Voice Control ($6A, $6B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3176" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Signed 8-bit sample.
&lt;/pre&gt;

Hyper Voice samples are typically written by [[DMA|Sound DMA]], but can also be written manually by the user. In the latter case, the "channel mode" setting is ignored - it always behaves as if it were in "stereo" mode, writing one channel after the other in sequence.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Sample scaling mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
  ||                          will be used for the left channel.
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

Internally, 8-bit values of the form &lt;tt style="white-space: nowrap"&gt;Vvvv vvvv&lt;/tt&gt; are transformed to signed 16-bit samples based on the scaling mode as follows:

{| class="wikitable"
! Sample scaling mode
! Bit representation
|-
| Unsigned
| &lt;tt style="white-space: nowrap"&gt;000 Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Unsigned, negated
| &lt;tt style="white-space: nowrap"&gt;111 Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Signed
| &lt;tt style="white-space: nowrap"&gt;VVV Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Ignored
| &lt;tt style="white-space: nowrap"&gt;___ Vvvv vvvv 0000 0000&lt;/tt&gt;
|}

With the exception of the Ignored mode, the resulting value is shifted right by &lt;code&gt;Shift&lt;/code&gt; bits, and the result's bottom 16 bits are used as the sample.</text>
    <sha1>e9e367ea2972c2bdd3775be6343aa72346201b98</sha1>
  </revision>
  <revision>
    <id>272</id>
    <parentid>271</parentid>
    <timestamp>2024-03-29T14:53:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3249" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Signed 8-bit sample.
&lt;/pre&gt;

Hyper Voice samples are typically written by [[DMA|Sound DMA]], but can also be written manually by the user. In the latter case, the "channel mode" setting is ignored - it always behaves as if it were in "stereo" mode, writing one channel after the other in sequence.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .mmc ????  errr ffss
  |||       |||| ||||
  |||       |||| ||++- Shift/Volume:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Sample scaling mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
  ||                          will be used for the left channel.
  ++------------------ Channel mode:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

Internally, 8-bit values of the form &lt;tt style="white-space: nowrap"&gt;Vvvv vvvv&lt;/tt&gt; are transformed to signed 16-bit samples based on the scaling mode as follows, where &lt;code&gt;V&lt;/code&gt; represents the highest, 7th bit of the input value:

{| class="wikitable"
! Sample scaling mode
! Bit representation
|-
| Unsigned
| &lt;tt style="white-space: nowrap"&gt;000 Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Unsigned, negated
| &lt;tt style="white-space: nowrap"&gt;111 Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Signed
| &lt;tt style="white-space: nowrap"&gt;VVV Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Ignored
| &lt;tt style="white-space: nowrap"&gt;___ Vvvv vvvv 0000 0000&lt;/tt&gt;
|}

With the exception of the Ignored mode, the resulting value is shifted right by &lt;code&gt;Shift&lt;/code&gt; bits, and the result's bottom 16 bits are used as the sample.</text>
    <sha1>54c33a7b427322ee727dffa222dedf8d631e5154</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>267</id>
    <parentid>245</parentid>
    <timestamp>2024-03-24T13:51:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21487" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="5" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="21" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Master Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Master volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>6bf63392834634fecf72c1190ae345e0fc8442f0</sha1>
  </revision>
  <revision>
    <id>268</id>
    <parentid>267</parentid>
    <timestamp>2024-03-24T13:52:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21483" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..ow Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Main Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>99731c1f55ad1d1f4f7212628a781d130350fdfb</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>Sound</title>
  <ns>0</ns>
  <id>27</id>
  <revision>
    <id>269</id>
    <parentid>209</parentid>
    <timestamp>2024-03-24T13:54:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9096" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
425? ???h
|||     |
|||     +- Hold Ch1-4 output updates
||+------- Force L10/R10 outputs to 0x55
|+-------- Force Ch1-4 outputs to 0x02
+--------- Force Ch1-4 outputs to 0x044
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}
=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>17ccfd4bbc171ffdb0b9b44207716c1c8152277a</sha1>
  </revision>
  <revision>
    <id>270</id>
    <parentid>269</parentid>
    <timestamp>2024-03-24T13:54:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Test ($95) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9096" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift right value
|    +---- Headphone output enable
+--------- Headphones connected: 1 if true
&lt;/pre&gt;

It is a good idea to set the internal speaker shift right value correctly. If the value is too low, multi-channel music will clip; if the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}
=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
425? ???h
|||     |
|||     +- Hold Ch1-4 output updates
||+------- Force L10/R10 outputs to 0x55
|+-------- Force Ch1-4 outputs to 0x02
+--------- Force Ch1-4 outputs to 0x04
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>7bfa225ec5268c76098d51426e8de0704567eb35</sha1>
  </revision>
  <revision>
    <id>275</id>
    <parentid>270</parentid>
    <timestamp>2024-04-03T16:18:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Output Control ($91) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9282" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
425? ???h
|||     |
|||     +- Hold Ch1-4 output updates
||+------- Force L10/R10 outputs to 0x55
|+-------- Force Ch1-4 outputs to 0x02
+--------- Force Ch1-4 outputs to 0x04
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>a7c78b145a8ea8b8c9116407d5812cbf857c4d9b</sha1>
  </revision>
  <revision>
    <id>276</id>
    <parentid>275</parentid>
    <timestamp>2024-04-03T16:44:09Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Test ($95) */ document bits 1, 2, 3</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9435" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by XORing bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}
=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
425? llsh
|||  ||||
|||  |||+- Hold Ch1-4 output updates
|||  ||+-- Use 3072000 Hz CPU clock for sweep
|||  ++--- Hold noise LFSR output
|||        (Differences between bit 2/3
|||        behavior are unknown)
||+------- Force L10/R10 outputs to 0x55
|+-------- Force Ch1-4 outputs to 0x02
+--------- Force Ch1-4 outputs to 0x04
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>290e51dae8167425aa57272b09878ca69cfd6b87</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>273</id>
    <parentid>242</parentid>
    <timestamp>2024-04-02T18:30:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Save type/size ($B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5049" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || ?
|-
| $2F || HTR || ?
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID ''$01'' is commonly documented as ''64 Kbit'', all known cartridges using that value come with ''256 Kbit'' SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>c498482d4f203bd7ccbacdb203ca7261033e6c20</sha1>
  </revision>
  <revision>
    <id>274</id>
    <parentid>273</parentid>
    <timestamp>2024-04-02T18:30:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Save type/size ($B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5076" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || ?
|-
| $2F || HTR || ?
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>bdf0f8593c07d92b4051121648b8be9e058ebaf7</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>277</id>
    <parentid>211</parentid>
    <timestamp>2024-05-28T14:02:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Command ($BC, $BD) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7514" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 1 if a READ command has completed.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>ca05e8797987c8434aa8afae74791e395fa03d10</sha1>
  </revision>
  <revision>
    <id>278</id>
    <parentid>277</parentid>
    <timestamp>2024-05-28T14:06:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Status ($BE, $BF read) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7634" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}
=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>2f428cc2c380f6fc2ef9fe547b285b6bcce828ee</sha1>
  </revision>
  <revision>
    <id>279</id>
    <parentid>278</parentid>
    <timestamp>2024-05-28T14:07:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Control ($BE, $BF write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7635" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..RD
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>d61d9c9a699558cabcb856b37b6f2cd589feb1dd</sha1>
  </revision>
  <revision>
    <id>280</id>
    <parentid>279</parentid>
    <timestamp>2024-05-28T14:07:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Status ($BE, $BF read) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7635" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  pswr ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>2a973f19a21d1071367a2ccf3b4187e7c30fdcf9</sha1>
  </revision>
  <revision>
    <id>281</id>
    <parentid>280</parentid>
    <timestamp>2024-05-28T14:07:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Control ($BE, $BF write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7635" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  p... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>f25d5c847c04df893df4e5b637de7743f7cb6a8f</sha1>
  </revision>
  <revision>
    <id>282</id>
    <parentid>281</parentid>
    <timestamp>2024-05-28T14:07:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Status ($BE, $BF read) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7635" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>ee90a6c1e840eabd13de13c07b81a3abd072167e</sha1>
  </revision>
  <revision>
    <id>284</id>
    <parentid>282</parentid>
    <timestamp>2024-05-28T14:09:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Control ($BE, $BF write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7794" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
        ||
        ++------------ Sub-Opcode:
                         00 - WDS
                         01 - WRAL
                         01 - ERAL
                         11 - WEN
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

If more than one of the Read, Write, Short bits are set, the command is treated as invalid (all three bits are cleared and no EEPROM operation is performed).

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>74a120ec36518094a940030e31155acd46b9c5f9</sha1>
  </revision>
  <revision>
    <id>285</id>
    <parentid>284</parentid>
    <timestamp>2024-05-28T14:10:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Command ($BC, $BD) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7853" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from/written to the EEPROM.
&lt;/pre&gt;

This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)

{{Anchor|Internal EEPROM Command}}
=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

If more than one of the Read, Write, Short bits are set, the command is treated as invalid (all three bits are cleared and no EEPROM operation is performed).

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>541c3daeab8f723debf3e545d4ab0c03308f31f0</sha1>
  </revision>
  <revision>
    <id>286</id>
    <parentid>285</parentid>
    <timestamp>2024-05-28T14:14:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Data ($BA, $BB) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8118" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

If more than one of the Read, Write, Short bits are set, the command is treated as invalid (all three bits are cleared and no EEPROM operation is performed).

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>29b1f0df6e448075bbab41ea9f274b1dd89e675f</sha1>
  </revision>
  <revision>
    <id>287</id>
    <parentid>286</parentid>
    <timestamp>2024-05-28T14:23:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Data ($BA, $BB write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8261" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

If more than one of the Read, Write, Short bits are set, the command is treated as invalid (all three bits are cleared and no EEPROM operation is performed).

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>da0976b4d7017e9433da446e9a339e839cd4c7f7</sha1>
  </revision>
  <revision>
    <id>288</id>
    <parentid>287</parentid>
    <timestamp>2024-05-28T14:24:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Data ($BA, $BB read) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8335" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read mode:  1 for READ command, 0 otherwise
            ||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- 1 to enable internal EEPROM write protection.
                       Cannot be cleared once set. 
&lt;/pre&gt;

The ''mode'' flags control the behaviour of the EEPROM interface:

* Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
* Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.

If more than one of the Read, Write, Short bits are set, the command is treated as invalid (all three bits are cleared and no EEPROM operation is performed).

Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>d7bb0773281c752048287abf5c75f3fa938dc8f6</sha1>
  </revision>
  <revision>
    <id>289</id>
    <parentid>288</parentid>
    <timestamp>2024-05-28T19:45:32Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Control ($BE, $BF write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8546" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

TODO

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read command:  1 for READ command, 0 otherwise
            ||+------- Write command: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short command: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read command Sends 16 bits from Command, then reads 16 bits to Data.
* Write command: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short command: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the command is treated as invalid (operation bits are cleared and no EEPROM operation is performed). Notably, this means that writing 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>5768ed5d90a0a3af19360de67457cc5a1cabf728</sha1>
  </revision>
  <revision>
    <id>290</id>
    <parentid>289</parentid>
    <timestamp>2024-05-28T19:51:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WDS - Write Disable */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8635" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

TODO

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read command:  1 for READ command, 0 otherwise
            ||+------- Write command: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short command: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read command Sends 16 bits from Command, then reads 16 bits to Data.
* Write command: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short command: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the command is treated as invalid (operation bits are cleared and no EEPROM operation is performed). Notably, this means that writing 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>f123cb1ff2044a1cf6bd97c12bda646fb4380080</sha1>
  </revision>
  <revision>
    <id>291</id>
    <parentid>290</parentid>
    <timestamp>2024-05-28T19:51:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WEN - Write Enable */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8735" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read command:  1 for READ command, 0 otherwise
            ||+------- Write command: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short command: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read command Sends 16 bits from Command, then reads 16 bits to Data.
* Write command: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short command: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the command is treated as invalid (operation bits are cleared and no EEPROM operation is performed). Notably, this means that writing 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>9e417101ebdb7f034ec7fa531371ba653d96c9fe</sha1>
  </revision>
  <revision>
    <id>292</id>
    <parentid>291</parentid>
    <timestamp>2024-05-30T08:42:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Hardware notes */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8901" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 01 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read command:  1 for READ command, 0 otherwise
            ||+------- Write command: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short command: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read command Sends 16 bits from Command, then reads 16 bits to Data.
* Write command: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short command: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the command is treated as invalid (operation bits are cleared and no EEPROM operation is performed). Notably, this means that writing 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>67cca32e7da669aea2366afaeb74cbcf686524d0</sha1>
  </revision>
  <revision>
    <id>293</id>
    <parentid>292</parentid>
    <timestamp>2024-05-30T17:28:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Command ($BC, $BD) */ Fix ERAL typo</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8901" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read command:  1 for READ command, 0 otherwise
            ||+------- Write command: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short command: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read command Sends 16 bits from Command, then reads 16 bits to Data.
* Write command: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short command: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the command is treated as invalid (operation bits are cleared and no EEPROM operation is performed). Notably, this means that writing 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>a1ad0181aaac7bb8f9cd43ffb328c882dce2f600</sha1>
  </revision>
  <revision>
    <id>294</id>
    <parentid>293</parentid>
    <timestamp>2024-05-30T17:33:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Control ($BE, $BF write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8947" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - AB&lt;br/&gt;
4 - 0
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>df6868271b7c8e9144edb52651325fa9afb2b9ad</sha1>
  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>283</id>
    <parentid>169</parentid>
    <timestamp>2024-05-28T14:08:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1627" xml:space="preserve">The Bandai 2001 (LUXSOR) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;&lt;br/&gt;or &lt;tt style="white-space: nowrap"&gt;0000 01CC aaaa aaaa&lt;/tt&gt;&lt;br/&gt; or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ASWR ....&lt;/tt&gt;
| W8
| Abort (A), Short (S), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

== EEPROM ==

The 2001's EEPROM interface is similar to the internal EEPROM interface, as documented on [[EEPROM#I/O_ports|the EEPROM page]]. Differences include:

* Instead of the internal EEPROM interface's P(rotect) bit, the A(bort) bit is provided. When the A bit is set, the transaction immediately stops.
* The EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

(Upload logic analyzer traces here)</text>
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  </revision>
</page>
<page arvcontinue="20240219202149|251">
  <title>2001 Mapper pinout</title>
  <ns>0</ns>
  <id>10</id>
  <revision>
    <id>295</id>
    <parentid>63</parentid>
    <timestamp>2024-06-27T07:37:38Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>ROM A23 (h/t happysoul on the discord)</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2173" xml:space="preserve">                         _____
                        /     \
                 D4 &lt;&gt; / 1  48 \ &lt;&gt; D5
                D3 &lt;&gt; / 2  O 47 \ &lt;&gt; D6
               D2 &lt;&gt; / 3      46 \ &lt;&gt; D7
              D1 &lt;&gt; / 4        45 \ -&gt; SRAM /CS
             D0 &lt;&gt; / 5          44 \ -- Vcc
           Gnd -- / 6            43 \ -&gt; ROM /CS
           A0 -&gt; / 7              42 \ -&gt; ROM A18
          A1 -&gt; / 8                41 \ -&gt; ROM A19
        Vcc -- / 9                  40 \ -- Gnd
        A2 -&gt; / 10                   39 \ -&gt; ROM A21
       A3 -&gt; / 11                     38 \ -&gt; ROM A20        Orientation:
 CPU A19 -&gt; / 12                       37 \ -&gt; ROM A16       ----------------
           /          BANDAI 2001          \                    36      25
           \        Package TQFP-48        /                     |      |
 CPU A18 -&gt; \ 13      0.5mm pitch      36 / -&gt; ROM A17          .--------.
  CPU A17 -&gt; \ 14                     35 / -&gt; ROM A22        37-|BANDAI O|-24
   CPU A16 -&gt; \ 15                   34 / -&gt; ROM A23            |2001    |
        Vcc -- \ 16                 33 / -&gt; Microwire CS     48-|O  914XC|-13
      /Reset ?&gt; \ 17               32 / -&gt; Microwire DI         \--------'
         /MBC &lt;- \ 18             31 / &lt;- Microwire DO           |      |
          M/IO -&gt; \ 19           30 / -- Vcc                    01      12
            /RD -&gt; \ 20         29 / -&gt; Microwire SK
             /WR -&gt; \ 21       28 / ?? Gnd              Legend:
             /SEL -&gt; \ 22     27 / ?? Gnd               ------------------------------------------
               CLK -&gt; \ 23 O 26 / ?? Gnd                --[2001]-- Power, n/a
                Gnd -- \ 24 25 / ?? Gnd                 -&gt;[2001]&lt;- 2001 input
                        \     /                         &lt;-[2001]-&gt; 2001 output
                         \   /                          &lt;&gt;[2001]&lt;&gt; Bidirectional
                          \ /                           ??[2001]?? Unknown
                           V                            ?&gt;[2001]&lt;? Input, unknown if bidirectional
 
 (Note that the corner indicator for pin 1 is subtle
  compared to the other corners as well as other QFPs.)</text>
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</page>
<page arvcontinue="20240712193917|301">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>301</id>
    <parentid>300</parentid>
    <timestamp>2024-07-12T19:39:17Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Color */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15395" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The WonderSwan provides sixteen different palettes. Palettes 0-7 can be used for the two screens only, while palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

- Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
- Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

- In mono modes, it is set to an entry in the shade lookup table (0-7),
- In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>429c593599d64eab3d9eaa8e30bc3e46d20ef30e</sha1>
  </revision>
  <revision>
    <id>302</id>
    <parentid>301</parentid>
    <timestamp>2024-07-12T19:41:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Palettes */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15439" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

- Palettes 0-7 can be used for the two screens only;
- Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

- Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
- Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

- In mono modes, it is set to an entry in the shade lookup table (0-7),
- In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>259f2365f4a68d463033294931a5cd834ecb742d</sha1>
  </revision>
  <revision>
    <id>303</id>
    <parentid>302</parentid>
    <timestamp>2024-07-12T19:41:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Palettes */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15439" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

- Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
- Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

- In mono modes, it is set to an entry in the shade lookup table (0-7),
- In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>eb556e3eff32371927eeaf6ee6e21da5ee4a17ed</sha1>
  </revision>
  <revision>
    <id>304</id>
    <parentid>303</parentid>
    <timestamp>2024-07-12T19:41:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Transparency */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15439" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

- In mono modes, it is set to an entry in the shade lookup table (0-7),
- In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>a8edd709692a7a18c9ae9e67519f2de5c65a3e6c</sha1>
  </revision>
  <revision>
    <id>305</id>
    <parentid>304</parentid>
    <timestamp>2024-07-12T19:41:59Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Background color */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15439" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

The WonderSwan can display up to two distinct 32x32 screens. These consist of 1024 two-byte cells:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>c70a54cfc6327215de923f43be020fdd93d15ebd</sha1>
  </revision>
  <revision>
    <id>306</id>
    <parentid>305</parentid>
    <timestamp>2024-07-12T19:47:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Screens */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15930" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>982b3960b58e1e64d8882404f7335c487af5b79f</sha1>
  </revision>
  <revision>
    <id>307</id>
    <parentid>306</parentid>
    <timestamp>2024-07-12T19:47:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Screens */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16007" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The WonderSwan can display up to 128 sprites at once. These are stored in a sprite table in RAM, which consists of up to 128 four-byte entries:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

For each row, the first 32 sprites for that row will be drawn - including sprites obscured by windows or outside of the visible range; only the Y coordinate determines this. The earlier among those sprites will be on top of the later ones.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>784266dd1a97d80c731f9bd9f916b9aa98fecd5c</sha1>
  </revision>
  <revision>
    <id>308</id>
    <parentid>307</parentid>
    <timestamp>2024-07-12T19:49:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sprites */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16319" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and the sprite layer can optionally be restricted to a specific window.

In addition, one can control if a given element is rendered inside or outside that window. For Screen 2, this is controlled globally; for sprites, this is controlled per-sprite.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>dda21e0aa6d7fb262f302883ae808691822c8f36</sha1>
  </revision>
  <revision>
    <id>309</id>
    <parentid>308</parentid>
    <timestamp>2024-07-12T19:51:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Windows */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16338" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 window location:
           0 = inside, 1 = outside
&lt;/pre&gt;

{{Anchor|Display Background}}
=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>95c85ad18760137af4a3417887d850f70549a1d5</sha1>
  </revision>
  <revision>
    <id>311</id>
    <parentid>309</parentid>
    <timestamp>2024-07-13T06:23:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Display Control ($00) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16385" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 tiles are drawn (if window enabled):
           0 = inside window,
           1 = outside window.
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

{{Anchor|Sprite Window}}
=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>eb26e56888a5a992a8ecce1eea68ed8cc4bb46b1</sha1>
  </revision>
  <revision>
    <id>312</id>
    <parentid>311</parentid>
    <timestamp>2024-07-13T06:25:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Screen 2 Window Bottom ($0B) */ clarify</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16626" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 tiles are drawn (if window enabled):
           0 = inside window,
           1 = outside window.
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

{{Anchor|Screen Scroll}}
=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>3200fa3b81e1c72640f0fcb3ddc13dfc621c8761</sha1>
  </revision>
  <revision>
    <id>313</id>
    <parentid>312</parentid>
    <timestamp>2024-07-13T06:25:40Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sprite Window Bottom ($0F) */ clarify</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16716" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 tiles are drawn (if window enabled):
           0 = inside window,
           1 = outside window.
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===
=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>47e0a45fd4bfc6907c6d40ae7361ed01d82187c5</sha1>
  </revision>
  <revision>
    <id>314</id>
    <parentid>313</parentid>
    <timestamp>2024-07-13T06:26:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Screen 1 Scroll Y ($11) */ clarify</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16925" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 tiles are drawn (if window enabled):
           0 = inside window,
           1 = outside window.
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

{{Anchor|LCD Control}}
=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>0b94516aedc37802b99bd1edeb10556ed57454ff</sha1>
  </revision>
  <revision>
    <id>315</id>
    <parentid>314</parentid>
    <timestamp>2024-07-13T06:26:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Screen 2 Scroll Y ($13) */ clarify</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16981" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..ow Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Enable Screen 2 window
  +------- Screen 2 tiles are drawn (if window enabled):
           0 = inside window,
           1 = outside window.
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>3f6667b0f88686ce4e6f9d89827520440716ebd7</sha1>
  </revision>
  <revision>
    <id>348</id>
    <parentid>315</parentid>
    <timestamp>2024-08-15T08:01:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Display Control ($00) */ fix bit order</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16981" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..w0 Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>7d55bd8c45a4dac8094c433fdc0fc9e67388c631</sha1>
  </revision>
  <revision>
    <id>349</id>
    <parentid>348</parentid>
    <timestamp>2024-08-15T08:01:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Display Control ($00) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16981" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn.

Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate.

Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>f90e70bb05f83c2401223250868ac4b149b0a163</sha1>
  </revision>
  <revision>
    <id>350</id>
    <parentid>349</parentid>
    <timestamp>2024-08-21T14:17:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sprites */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17251" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vv.s
   | || |
   | || +- LCD sleep: 0 = no, 1 = sleep
   | ||
   | ||    Volume segments:
   | |+--- Volume B (medium, high)
   | +---- Volume A (low, high)
   +------ Speaker
&lt;/pre&gt;

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>8666cc7840ebeb9f8806f09823fde519d7ee19b4</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>310</id>
    <parentid>250</parentid>
    <timestamp>2024-07-12T20:29:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Links */ might as well add Wonderful</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1672" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
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</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS/Sound</title>
  <ns>0</ns>
  <id>50</id>
  <revision>
    <id>316</id>
    <timestamp>2024-07-20T08:18:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Sound interrupt provides an abstraction layer for the WonderSwan's [[Sound|sound hardware]].  == Interrupts ==  === INT 15/AH=00h - sound_init ===  * AH = 00h  === INT 15/AH=01h - sound_set_channel ===  * AH = 01h * BL = [[Sound#Sound Channel Control|Channel Control]] value  === INT 15/AH=02h - sound_get_channel ===  * AH = 02h  Return:  * AL = [[Sound#Sound Channel Control|Channel Control]] value  === INT 15/AH=03h - sound_set_output ===  * AH = 03h * BL = Sound#S..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2061" xml:space="preserve">The Sound interrupt provides an abstraction layer for the WonderSwan's [[Sound|sound hardware]].

== Interrupts ==

=== INT 15/AH=00h - sound_init ===

* AH = 00h

=== INT 15/AH=01h - sound_set_channel ===

* AH = 01h
* BL = [[Sound#Sound Channel Control|Channel Control]] value

=== INT 15/AH=02h - sound_get_channel ===

* AH = 02h

Return:

* AL = [[Sound#Sound Channel Control|Channel Control]] value

=== INT 15/AH=03h - sound_set_output ===

* AH = 03h
* BL = [[Sound#Sound Output Control|Output Control]] value

=== INT 15/AH=04h - sound_get_output ===

* AH = 04h

Return:

* AL = [[Sound#Sound Output Control|Output Control]] value

=== INT 15/AH=05h - sound_set_wave ===

* AH = 05h
* AL = Channel (0, 1, 2, 3)
* DS:DX = Pointer to waveform data (16 bytes)

=== INT 15/AH=06h - sound_set_pitch ===

* AH = 06h
* AL = Channel (0, 1, 2, 3)
* BX = Frequency divider (0 - 2047)

=== INT 15/AH=07h - sound_get_pitch ===

* AH = 07h
* AL = Channel (0, 1, 2, 3)

Return:

* AX = Frequency divider (0 - 2047)

=== INT 15/AH=08h - sound_set_volume ===

* AH = 08h
* AL = Channel (0, 1, 2, 3)
* BL = [[Sound#Sound Channel Volume|Channel Volume]] value

=== INT 15/AH=09h - sound_get_volume ===

* AH = 09h
* AL = Channel (0, 1, 2, 3)

Return:

* AL = [[Sound#Sound Channel Volume|Channel Volume]] value

=== INT 15/AH=0Ah - sound_set_sweep ===

* AH = 0Ah
* BL = [[Sound#Sound Channel 3 Sweep Amount|Sweep Amount]]
* CL = [[Sound#Sound Channel 3 Sweep Ticks|Sweep Ticks]]

=== INT 15/AH=0Bh - sound_get_sweep ===

* AH = 0Bh

Return:

* AL = [[Sound#Sound Channel 3 Sweep Amount|Sweep Amount]]
* AH = [[Sound#Sound Channel 3 Sweep Ticks|Sweep Ticks]]

=== INT 15/AH=0Ch - sound_set_noise ===

* AH = 0Ch
* BL = [[Sound#Sound Channel 4 Noise Control|Channel 4 Noise Control]] value

=== INT 15/AH=0Dh - sound_get_noise ===

* AH = 0Dh

Return:

* AL = [[Sound#Sound Channel 4 Noise Control|Channel 4 Noise Control]] value

=== INT 15/AH=0Eh - sound_get_random ===

* AH = 0Eh

Return:

* AX = [[Sound#Sound Channel 4 LFSR Register|Channel 4 LFSR Register]] value</text>
    <sha1>9e4b7048f4dfc23900fa9a2c6e8903df415bb79f</sha1>
  </revision>
  <revision>
    <id>317</id>
    <parentid>316</parentid>
    <timestamp>2024-07-20T08:20:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2076" xml:space="preserve">The Sound interrupt provides an abstraction layer for the WonderSwan's [[Sound|sound hardware]].

== Interrupts ==

=== INT $15/AH=$00 - sound_init ===

* AH = $00

=== INT $15/AH=$01 - sound_set_channel ===

* AH = $01
* BL = [[Sound#Sound Channel Control|Channel Control]] value

=== INT $15/AH=$02 - sound_get_channel ===

* AH = $02

Return:

* AL = [[Sound#Sound Channel Control|Channel Control]] value

=== INT $15/AH=$03 - sound_set_output ===

* AH = $03
* BL = [[Sound#Sound Output Control|Output Control]] value

=== INT $15/AH=$04 - sound_get_output ===

* AH = $04

Return:

* AL = [[Sound#Sound Output Control|Output Control]] value

=== INT $15/AH=$05 - sound_set_wave ===

* AH = $05
* AL = Channel (0, 1, 2, 3)
* DS:DX = Pointer to waveform data (16 bytes)

=== INT $15/AH=$06 - sound_set_pitch ===

* AH = $06
* AL = Channel (0, 1, 2, 3)
* BX = Frequency divider (0 - 2047)

=== INT $15/AH=$07 - sound_get_pitch ===

* AH = $07
* AL = Channel (0, 1, 2, 3)

Return:

* AX = Frequency divider (0 - 2047)

=== INT $15/AH=$08 - sound_set_volume ===

* AH = $08
* AL = Channel (0, 1, 2, 3)
* BL = [[Sound#Sound Channel Volume|Channel Volume]] value

=== INT $15/AH=$09 - sound_get_volume ===

* AH = $09
* AL = Channel (0, 1, 2, 3)

Return:

* AL = [[Sound#Sound Channel Volume|Channel Volume]] value

=== INT $15/AH=$0A - sound_set_sweep ===

* AH = $0A
* BL = [[Sound#Sound Channel 3 Sweep Amount|Sweep Amount]]
* CL = [[Sound#Sound Channel 3 Sweep Ticks|Sweep Ticks]]

=== INT $15/AH=$0B - sound_get_sweep ===

* AH = $0B

Return:

* AL = [[Sound#Sound Channel 3 Sweep Amount|Sweep Amount]]
* AH = [[Sound#Sound Channel 3 Sweep Ticks|Sweep Ticks]]

=== INT $15/AH=$0C - sound_set_noise ===

* AH = $0C
* BL = [[Sound#Sound Channel 4 Noise Control|Channel 4 Noise Control]] value

=== INT $15/AH=$0D - sound_get_noise ===

* AH = $0D

Return:

* AL = [[Sound#Sound Channel 4 Noise Control|Channel 4 Noise Control]] value

=== INT $15/AH=$0E - sound_get_random ===

* AH = $0E

Return:

* AX = [[Sound#Sound Channel 4 LFSR Register|Channel 4 LFSR Register]] value</text>
    <sha1>544f959160185f4723f5954ae5568c73de718c31</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch</title>
  <ns>0</ns>
  <id>41</id>
  <revision>
    <id>318</id>
    <parentid>261</parentid>
    <timestamp>2024-07-23T20:05:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2527" xml:space="preserve">The WonderWitch is an official homebrew development kit released by Qute Corporation on July 18th, 2000.

== Hardware ==

The WonderWitch cartridge is based on the [[Bandai 2003]] mapper. It provides an RTC, as well as NOR self-flashing functionality using the Fujitsu MBM29DL400TC chip.

There were three means of acquiring WonderWitch cartridges:

* '''WonderWitch''', a software development kit containing a reflashable cartridge, a WonderSwan&lt;-&gt;RS-232 adapter, a development manual and a development tool CD;
* '''WonderWitch Player''', a priced-down user-only version omitting the development manual and tooling;
* The VAR program, allowing independent creators to buy reflashable cartridges in bulk, in units of 20 or 100.

== Software ==

The WonderWitch provides an abstraction layer and helper libraries, split into two modules:

* [[WonderWitch/FreyaBIOS|FreyaBIOS]] - providing a hardware abstraction layer and some utility functions,
* [[WonderWitch/FreyaOS|FreyaOS]] - providing helper libraries and higher-level concepts, such as processes and files.

== Memory map ==

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
! From
! To
! Description
|-
| 0x00000
| 0x00???
| Interrupt vectors
|-
| 0x00???
| 0x00???
| ??? 
|-
| 0x00E00
| 0x03FFF
| Space used by user programs (sprite, screen, tile data)
|-
| 0x04000
| 0x0BFFF
| Space used by user programs (color tile data)
|-
| 0x0C000
| 0x0FDFF
| ???
|-
| 0x0FE00
| 0x0FFFF
| Space used by user programs (color palette data)
|-
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/File system|File system]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}

=== Interrupt vectors ===

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|}

Internal console RAM is generally managed by [[WonderWitch/FreyaBIOS|FreyaBIOS]], while SRAM is managed by [[WonderWitch/FreyaOS|FreyaOS]].

== Development tools ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Fujitsu MBM29DL400TC datasheet]</text>
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  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS/Display</title>
  <ns>0</ns>
  <id>51</id>
  <revision>
    <id>319</id>
    <timestamp>2024-07-23T20:27:28Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Display interrupt provides an abstraction layer and helpers for the WonderSwan's [[Display|display hardware]].  Note that features specific to the WonderSwan Color are implemented using [[WonderWitch/Libwwc|libwwc]], which is linked statically with the user program and thus not part of the BIOS call surface.  == Interrupts ==  === INT $12/AH=$00 - display_control ===  * AH = $00 * BX = [[Display#Display Control|Display Control]] value  === INT $12/AH=$01 - display_st..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6743" xml:space="preserve">The Display interrupt provides an abstraction layer and helpers for the WonderSwan's [[Display|display hardware]].

Note that features specific to the WonderSwan Color are implemented using [[WonderWitch/Libwwc|libwwc]], which is linked statically with the user program and thus not part of the BIOS call surface.

== Interrupts ==

=== INT $12/AH=$00 - display_control ===

* AH = $00
* BX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$01 - display_status ===

* AH = $01

Return:

* AX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$02 - font_set_monodata ===

* AH = $02
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;8 x Tile count&lt;/code&gt; bytes)

Stores 1 bit-per-pixel tile data, which is expanded to 2 bits-per-pixel using the configured color.

=== INT $12/AH=$03 - font_set_colordata ===

* AH = $03
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Stores 2 bit-per-pixel tile data.

=== INT $12/AH=$04 - font_get_data ===

* AH = $04
* BX = Starting tile
* CX = Tile count
* DS:DX = Output data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Retrieves 2 bit-per-pixel tile data.

=== INT $12/AH=$05 - font_set_color ===

* AH = $05
* BX = Color

&lt;code&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... bbff
                 ||||
                 ||++- Foreground color (0-3)
                 ++--- Background color (0-3)
&lt;/code&gt;

Used by &lt;code&gt;font_set_monodata&lt;/code&gt;.

=== INT $12/AH=$06 - font_get_color ===

* AH = $05

Return:

* AX = Color

=== INT $12/AH=$07 - screen_set_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Input tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Places a rectangular tilemap on the specified screen.

=== INT $12/AH=$08 - screen_get_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Output tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Retrieves a rectangular tilemap from the specified screen.

Special case: If CL/CH are equal to 0, &lt;code&gt;DS:DX&lt;/code&gt; is ignored and instead &lt;code&gt;AX&lt;/code&gt; is set to the tile at coordinates &lt;code&gt;(BL, BH)&lt;/code&gt;. 

=== INT $12/AH=$09 - screen_fill_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile attribute

Fills a rectangular area with the specified tile attribute.

=== INT $12/AH=$0A - screen_fill_attr ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile data
* SI = Tile mask

Modifies each tile in the specified rectangular area as follows: &lt;code&gt;tile = ((tile &amp; SI) | DX)&lt;/code&gt;.

=== INT $12/AH=$0B - sprite_set_range ===

* AH = $0B
* BX = [[Display#Sprite Table First|Sprite Table First]]
* CX = [[Display#Sprite Table Count|Sprite Table Count]]

=== INT $12/AH=$0C - sprite_set_char ===

* AH = $0C
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute

=== INT $12/AH=$0D - sprite_get_char ===

* AH = $0D
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute

=== INT $12/AH=$0E - sprite_set_location ===

* AH = $0E
* BX = Sprite ID in table (0 - 127)
* DL = X coordinate
* DH = Y coordinate

Note that DL/DH are swapped relative to the order in which the sprite coordinate bytes are stored in memory.

=== INT $12/AH=$0F - sprite_get_location ===

* AH = $0F
* BX = Sprite ID in table (0 - 127)

Return:

* AL = X coordinate
* AH = Y coordinate

=== INT $12/AH=$10 - sprite_set_char_location ===

* AH = $10
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$11 - sprite_get_char_location ===

* AH = $11
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$12 - sprite_set_data ===

* AH = $12
* BX = Initial sprite ID in table (0 - 127)
* CX = Sprite count
* DS:DX = Input data buffer (&lt;code&gt;4 x Sprite count&lt;/code&gt; bytes)

=== INT $12/AH=$13 - screen_set_scroll ===

* AH = $13
* AL = Screen (0, 1)
* BL = [[Display#Screen Scroll|Screen Scroll X]] value
* BH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$14 - screen_get_scroll ===

* AH = $14
* AL = Screen (0, 1)

Return:

* AL = [[Display#Screen Scroll|Screen Scroll X]] value
* AH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$15 - screen2_set_window ===

* AH = $15
* BL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* BH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$16 - screen2_get_window ===

* AH = $15

Return:

* AL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* AH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$17 - sprite_set_window ===

* AH = $17
* BL = [[Display#Sprite Window|Sprite Window Left]] value
* BH = [[Display#Sprite Window|Sprite Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$18 - sprite_get_window ===

* AH = $18

Return:

* AL = [[Display#Sprite Window|Sprite Window Left]] value
* AH = [[Display#Sprite Window|Sprite Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$19 - palette_set_color ===

* AH = $19
* BX = Palette index (0 - 15)
* CX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1A - palette_get_color ===

* AH = $1A
* BX = Palette index (0 - 15)

Return:

* AX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1B - lcd_set_color ===

* AH = $1B
* CX:BX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1C - lcd_get_color ===

* AH = $1C

Return:

* DX:AX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1D - lcd_set_segments ===

* AH = $1D
* BX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1E - lcd_get_segments ===

* AH = $1E

Return: 

* AX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1F - lcd_set_sleep ===

=== INT $12/AH=$20 - lcd_get_sleep ===

=== INT $12/AH=$21 - screen_set_vram ===

* AH = $21
* AL = Screen (0, 1)
* BL = Internal RAM address, shifted right by 11

Note: This function is undocumented.

=== INT $12/AH=$22 - sprite_set_vram ===

* AH = $21
* BL = Internal RAM address, shifted right by 9

Note: This function is undocumented.</text>
    <sha1>c69966ee5c10d7cebd25da8115702154d4ea75f1</sha1>
  </revision>
  <revision>
    <id>320</id>
    <parentid>319</parentid>
    <timestamp>2024-07-23T20:28:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6741" xml:space="preserve">The Display interrupt provides an abstraction layer and helpers for the WonderSwan's [[Display|display hardware]].

Note that features specific to the WonderSwan Color are implemented using [[WonderWitch/Libwwc|libwwc]], which is linked statically with the user program and thus not part of the BIOS call surface.

== Interrupts ==

=== INT $12/AH=$00 - display_control ===

* AH = $00
* BX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$01 - display_status ===

* AH = $01

Return:

* AX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$02 - font_set_monodata ===

* AH = $02
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;8 x Tile count&lt;/code&gt; bytes)

Stores 1 bit-per-pixel tile data, which is expanded to 2 bits-per-pixel using the configured color.

=== INT $12/AH=$03 - font_set_colordata ===

* AH = $03
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Stores 2 bit-per-pixel tile data.

=== INT $12/AH=$04 - font_get_data ===

* AH = $04
* BX = Starting tile
* CX = Tile count
* DS:DX = Output data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Retrieves 2 bit-per-pixel tile data.

=== INT $12/AH=$05 - font_set_color ===

* AH = $05
* BX = Color

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... bbff
                 ||||
                 ||++- Foreground color (0-3)
                 ++--- Background color (0-3)
&lt;/pre&gt;

Used by &lt;code&gt;font_set_monodata&lt;/code&gt;.

=== INT $12/AH=$06 - font_get_color ===

* AH = $05

Return:

* AX = Color

=== INT $12/AH=$07 - screen_set_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Input tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Places a rectangular tilemap on the specified screen.

=== INT $12/AH=$08 - screen_get_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Output tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Retrieves a rectangular tilemap from the specified screen.

Special case: If CL/CH are equal to 0, &lt;code&gt;DS:DX&lt;/code&gt; is ignored and instead &lt;code&gt;AX&lt;/code&gt; is set to the tile at coordinates &lt;code&gt;(BL, BH)&lt;/code&gt;. 

=== INT $12/AH=$09 - screen_fill_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile attribute

Fills a rectangular area with the specified tile attribute.

=== INT $12/AH=$0A - screen_fill_attr ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile data
* SI = Tile mask

Modifies each tile in the specified rectangular area as follows: &lt;code&gt;tile = ((tile &amp; SI) | DX)&lt;/code&gt;.

=== INT $12/AH=$0B - sprite_set_range ===

* AH = $0B
* BX = [[Display#Sprite Table First|Sprite Table First]]
* CX = [[Display#Sprite Table Count|Sprite Table Count]]

=== INT $12/AH=$0C - sprite_set_char ===

* AH = $0C
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute

=== INT $12/AH=$0D - sprite_get_char ===

* AH = $0D
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute

=== INT $12/AH=$0E - sprite_set_location ===

* AH = $0E
* BX = Sprite ID in table (0 - 127)
* DL = X coordinate
* DH = Y coordinate

Note that DL/DH are swapped relative to the order in which the sprite coordinate bytes are stored in memory.

=== INT $12/AH=$0F - sprite_get_location ===

* AH = $0F
* BX = Sprite ID in table (0 - 127)

Return:

* AL = X coordinate
* AH = Y coordinate

=== INT $12/AH=$10 - sprite_set_char_location ===

* AH = $10
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$11 - sprite_get_char_location ===

* AH = $11
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$12 - sprite_set_data ===

* AH = $12
* BX = Initial sprite ID in table (0 - 127)
* CX = Sprite count
* DS:DX = Input data buffer (&lt;code&gt;4 x Sprite count&lt;/code&gt; bytes)

=== INT $12/AH=$13 - screen_set_scroll ===

* AH = $13
* AL = Screen (0, 1)
* BL = [[Display#Screen Scroll|Screen Scroll X]] value
* BH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$14 - screen_get_scroll ===

* AH = $14
* AL = Screen (0, 1)

Return:

* AL = [[Display#Screen Scroll|Screen Scroll X]] value
* AH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$15 - screen2_set_window ===

* AH = $15
* BL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* BH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$16 - screen2_get_window ===

* AH = $15

Return:

* AL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* AH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$17 - sprite_set_window ===

* AH = $17
* BL = [[Display#Sprite Window|Sprite Window Left]] value
* BH = [[Display#Sprite Window|Sprite Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$18 - sprite_get_window ===

* AH = $18

Return:

* AL = [[Display#Sprite Window|Sprite Window Left]] value
* AH = [[Display#Sprite Window|Sprite Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$19 - palette_set_color ===

* AH = $19
* BX = Palette index (0 - 15)
* CX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1A - palette_get_color ===

* AH = $1A
* BX = Palette index (0 - 15)

Return:

* AX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1B - lcd_set_color ===

* AH = $1B
* CX:BX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1C - lcd_get_color ===

* AH = $1C

Return:

* DX:AX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1D - lcd_set_segments ===

* AH = $1D
* BX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1E - lcd_get_segments ===

* AH = $1E

Return: 

* AX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1F - lcd_set_sleep ===

=== INT $12/AH=$20 - lcd_get_sleep ===

=== INT $12/AH=$21 - screen_set_vram ===

* AH = $21
* AL = Screen (0, 1)
* BL = Internal RAM address, shifted right by 11

Note: This function is undocumented.

=== INT $12/AH=$22 - sprite_set_vram ===

* AH = $21
* BL = Internal RAM address, shifted right by 9

Note: This function is undocumented.</text>
    <sha1>09f156ea0981ccf62c248ea00b08453466271d03</sha1>
  </revision>
  <revision>
    <id>325</id>
    <parentid>320</parentid>
    <timestamp>2024-07-27T13:39:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix AH values</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6741" xml:space="preserve">The Display interrupt provides an abstraction layer and helpers for the WonderSwan's [[Display|display hardware]].

Note that features specific to the WonderSwan Color are implemented using [[WonderWitch/Libwwc|libwwc]], which is linked statically with the user program and thus not part of the BIOS call surface.

== Interrupts ==

=== INT $12/AH=$00 - display_control ===

* AH = $00
* BX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$01 - display_status ===

* AH = $01

Return:

* AX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$02 - font_set_monodata ===

* AH = $02
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;8 x Tile count&lt;/code&gt; bytes)

Stores 1 bit-per-pixel tile data, which is expanded to 2 bits-per-pixel using the configured color.

=== INT $12/AH=$03 - font_set_colordata ===

* AH = $03
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Stores 2 bit-per-pixel tile data.

=== INT $12/AH=$04 - font_get_data ===

* AH = $04
* BX = Starting tile
* CX = Tile count
* DS:DX = Output data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Retrieves 2 bit-per-pixel tile data.

=== INT $12/AH=$05 - font_set_color ===

* AH = $05
* BX = Color

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... bbff
                 ||||
                 ||++- Foreground color (0-3)
                 ++--- Background color (0-3)
&lt;/pre&gt;

Used by &lt;code&gt;font_set_monodata&lt;/code&gt;.

=== INT $12/AH=$06 - font_get_color ===

* AH = $06

Return:

* AX = Color

=== INT $12/AH=$07 - screen_set_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Input tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Places a rectangular tilemap on the specified screen.

=== INT $12/AH=$08 - screen_get_char ===

* AH = $08
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Output tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Retrieves a rectangular tilemap from the specified screen.

Special case: If CL/CH are equal to 0, &lt;code&gt;DS:DX&lt;/code&gt; is ignored and instead &lt;code&gt;AX&lt;/code&gt; is set to the tile at coordinates &lt;code&gt;(BL, BH)&lt;/code&gt;. 

=== INT $12/AH=$09 - screen_fill_char ===

* AH = $09
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile attribute

Fills a rectangular area with the specified tile attribute.

=== INT $12/AH=$0A - screen_fill_attr ===

* AH = $0A
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile data
* SI = Tile mask

Modifies each tile in the specified rectangular area as follows: &lt;code&gt;tile = ((tile &amp; SI) | DX)&lt;/code&gt;.

=== INT $12/AH=$0B - sprite_set_range ===

* AH = $0B
* BX = [[Display#Sprite Table First|Sprite Table First]]
* CX = [[Display#Sprite Table Count|Sprite Table Count]]

=== INT $12/AH=$0C - sprite_set_char ===

* AH = $0C
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute

=== INT $12/AH=$0D - sprite_get_char ===

* AH = $0D
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute

=== INT $12/AH=$0E - sprite_set_location ===

* AH = $0E
* BX = Sprite ID in table (0 - 127)
* DL = X coordinate
* DH = Y coordinate

Note that DL/DH are swapped relative to the order in which the sprite coordinate bytes are stored in memory.

=== INT $12/AH=$0F - sprite_get_location ===

* AH = $0F
* BX = Sprite ID in table (0 - 127)

Return:

* AL = X coordinate
* AH = Y coordinate

=== INT $12/AH=$10 - sprite_set_char_location ===

* AH = $10
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$11 - sprite_get_char_location ===

* AH = $11
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$12 - sprite_set_data ===

* AH = $12
* BX = Initial sprite ID in table (0 - 127)
* CX = Sprite count
* DS:DX = Input data buffer (&lt;code&gt;4 x Sprite count&lt;/code&gt; bytes)

=== INT $12/AH=$13 - screen_set_scroll ===

* AH = $13
* AL = Screen (0, 1)
* BL = [[Display#Screen Scroll|Screen Scroll X]] value
* BH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$14 - screen_get_scroll ===

* AH = $14
* AL = Screen (0, 1)

Return:

* AL = [[Display#Screen Scroll|Screen Scroll X]] value
* AH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$15 - screen2_set_window ===

* AH = $15
* BL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* BH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$16 - screen2_get_window ===

* AH = $16

Return:

* AL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* AH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$17 - sprite_set_window ===

* AH = $17
* BL = [[Display#Sprite Window|Sprite Window Left]] value
* BH = [[Display#Sprite Window|Sprite Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$18 - sprite_get_window ===

* AH = $18

Return:

* AL = [[Display#Sprite Window|Sprite Window Left]] value
* AH = [[Display#Sprite Window|Sprite Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$19 - palette_set_color ===

* AH = $19
* BX = Palette index (0 - 15)
* CX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1A - palette_get_color ===

* AH = $1A
* BX = Palette index (0 - 15)

Return:

* AX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1B - lcd_set_color ===

* AH = $1B
* CX:BX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1C - lcd_get_color ===

* AH = $1C

Return:

* DX:AX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1D - lcd_set_segments ===

* AH = $1D
* BX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1E - lcd_get_segments ===

* AH = $1E

Return: 

* AX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1F - lcd_set_sleep ===

=== INT $12/AH=$20 - lcd_get_sleep ===

=== INT $12/AH=$21 - screen_set_vram ===

* AH = $21
* AL = Screen (0, 1)
* BL = Internal RAM address, shifted right by 11

Note: This function is undocumented.

=== INT $12/AH=$22 - sprite_set_vram ===

* AH = $22
* BL = Internal RAM address, shifted right by 9

Note: This function is undocumented.</text>
    <sha1>01db17da6d32922280e4539772322e9f1572d283</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS/Key</title>
  <ns>0</ns>
  <id>52</id>
  <revision>
    <id>321</id>
    <timestamp>2024-07-24T16:08:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Display interrupt provides helper functions for accessing the WonderSwan's [[Keypad|keypad]].  == Interrupts ==  === INT $11/AH=$00 - key_press_check ===  * AH = $00  Return:  * AX = A bitmask containing the currently held keys.  &lt;pre&gt; 15  bit  8  7  bit  0  ---- ----  ---- ----  .... 4321  4321 bas.       ||||  |||| |||       ||||  |||| ||+- Start       ||||  |||| |+-- A       ||||  |||| +--- B       ||||  ++++----- X1/X2/X3/X4       ++++----------- Y1/Y2/Y3/Y4 &lt;/pr..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1213" xml:space="preserve">The Display interrupt provides helper functions for accessing the WonderSwan's [[Keypad|keypad]].

== Interrupts ==

=== INT $11/AH=$00 - key_press_check ===

* AH = $00

Return:

* AX = A bitmask containing the currently held keys.

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... 4321  4321 bas.
      ||||  |||| |||
      ||||  |||| ||+- Start
      ||||  |||| |+-- A
      ||||  |||| +--- B
      ||||  ++++----- X1/X2/X3/X4
      ++++----------- Y1/Y2/Y3/Y4
&lt;/pre&gt;

=== INT $12/AH=$01 - key_hit_check ===

* AH = $01

Return:

* AX = A bitmask containing the newly pressed keys, if any.

=== INT $11/AH=$02 - key_wait ===

* AH = $01

Return:

* AX = A bitmask containing the newly pressed keys.

This call blocks until a key is pressed.

=== INT $11/AH=$03 - key_set_repeat ===

* AH = $03
* BL = Key repeat delay, in frames
* BH = Key repeat rate, in frames

=== INT $11/AH=$04 - key_get_repeat ===

* AH = $04

Return:

* AL = Key repeat delay, in frames
* AH = Key repeat rate, in frames

=== INT $11/AH=$05 - key_hit_check_with_repeat ===

* AH = $01

Return:

* AX = A bitmask containing the newly pressed keys, if any.

For this call, the repeat delay/rate configuration is taken into account.</text>
    <sha1>71b1ae6b80c1893035256b8d04af38c1f79f0780</sha1>
  </revision>
  <revision>
    <id>322</id>
    <parentid>321</parentid>
    <timestamp>2024-07-24T16:08:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1213" xml:space="preserve">The Display interrupt provides helper functions for accessing the WonderSwan's [[Keypad|keypad]].

== Interrupts ==

=== INT $11/AH=$00 - key_press_check ===

* AH = $00

Return:

* AX = A bitmask containing the currently held keys.

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... 4321  4321 bas.
      ||||  |||| |||
      ||||  |||| ||+- Start
      ||||  |||| |+-- A
      ||||  |||| +--- B
      ||||  ++++----- X1/X2/X3/X4
      ++++----------- Y1/Y2/Y3/Y4
&lt;/pre&gt;

=== INT $12/AH=$01 - key_hit_check ===

* AH = $01

Return:

* AX = A bitmask containing the newly pressed keys, if any.

=== INT $11/AH=$02 - key_wait ===

* AH = $02

Return:

* AX = A bitmask containing the newly pressed keys.

This call blocks until a key is pressed.

=== INT $11/AH=$03 - key_set_repeat ===

* AH = $03
* BL = Key repeat delay, in frames
* BH = Key repeat rate, in frames

=== INT $11/AH=$04 - key_get_repeat ===

* AH = $04

Return:

* AL = Key repeat delay, in frames
* AH = Key repeat rate, in frames

=== INT $11/AH=$05 - key_hit_check_with_repeat ===

* AH = $05

Return:

* AX = A bitmask containing the newly pressed keys, if any.

For this call, the repeat delay/rate configuration is taken into account.</text>
    <sha1>698ef440972143953bf68ce5297a7c4944367436</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>323</id>
    <parentid>294</parentid>
    <timestamp>2024-07-25T17:58:17Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Layout */ fix blood type order</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8947" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - 0&lt;br/&gt;
4 - AB
|-
| $76 || 1 || Last booted cartridge developer/publisher ID
|-
| $77 || 1 || Last booted cartridge game ID
|-
| $78 || 1 || Last booted cartridge game version
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>6059d59f66ce07b6bb8224bf1f803253bb0d12ea</sha1>
  </revision>
  <revision>
    <id>340</id>
    <parentid>323</parentid>
    <timestamp>2024-08-05T08:49:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix error in internal EEPROM data layout</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8982" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - 0&lt;br/&gt;
4 - AB
|-
| $76 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID)
|-
| $77 || 1 || Last booted [[ROM header]] byte 7 (color)
|-
| $78 || 1 || Last booted [[ROM header]] byte 8 (game ID)
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>0ac74b4fd203412f92d97b982022ab5e23f662da</sha1>
  </revision>
  <revision>
    <id>341</id>
    <parentid>340</parentid>
    <timestamp>2024-08-05T09:27:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Layout */ figure out bytes 0x80, 0x81, 0x82</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9292" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== ERAL - Erase All ===

This command is not guaranteed to be present on all EEPROMs.

TODO

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - 0&lt;br/&gt;
4 - AB
|-
| $76 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID)
|-
| $77 || 1 || Last booted [[ROM header]] byte 7 (color)
|-
| $78 || 1 || Last booted [[ROM header]] byte 8 (game ID)
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $80 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID) - only changed if byte 7 (color) != 0
|-
| $81 || 1 || Last booted [[ROM header]] byte 7 (color) - only changed if byte 7 (color) != 0
|-
| $82 || 1 || Last booted [[ROM header]] byte 8 (game ID) - only changed if byte 7 (color) != 0
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>9601ce270576101747ed8157ad6713c9ea92c3b0</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS/Text</title>
  <ns>0</ns>
  <id>53</id>
  <revision>
    <id>324</id>
    <timestamp>2024-07-27T08:34:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Text interrupt provides a text output display using one of the WonderSwan's screens.  == Interrupts ==  === INT $13/AH=$00 - text_screen_init ===  * AH = $00  Initializes a text window (see INT $13/AH=$01) with the following default settings:  * X, Y = 0, 0 * width, height = 28, 18 * starting tile = 512 - font tile count (in ASCII mode) * starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)  === INT $13/AH=$01 - text_window_init ===  * AH = $01 * BL..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4427" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BL = X position in text window
* BH = Y position in text window
* CL = Width of area to write number in
* CH = Flags
* DX = Number
* DS:SI = Output buffer (optional, see flags)

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:SI)
&lt;/pre&gt;

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_set_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>3efd8c7df3af914fafa3c83c1eab97fec5d99072</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS/Communication</title>
  <ns>0</ns>
  <id>54</id>
  <revision>
    <id>326</id>
    <timestamp>2024-07-27T13:42:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].  == Interrupts ==  === INT $14/AH=$00 - comm_open ===  * AH = $00  Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.  === INT $14/AH=$01 - comm_close ===  * AH = $01  Closes the serial port.  === INT $14/AH=$02 - comm_send_char ===  * AH = $02 * BL = Character (byte) to send.  Return:  * AX = Return code...."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2160" xml:space="preserve">The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].

== Interrupts ==

=== INT $14/AH=$00 - comm_open ===

* AH = $00

Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.

=== INT $14/AH=$01 - comm_close ===

* AH = $01

Closes the serial port.

=== INT $14/AH=$02 - comm_send_char ===

* AH = $02
* BL = Character (byte) to send.

Return:

* AX = Return code.

Return codes:

* 0x0000 - Success
* 0x8101 - Transfer timeout
* 0x8102 - Transfer RX overrun
* 0x8103 - Transfer cancelled

=== INT $14/AH=$03 - comm_receive_char ===

* AH = $03

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

=== INT $14/AH=$04 - comm_receive_with_timeout ===

* AH = $03
* CX = Timeout, in frames (as in &lt;code&gt;comm_set_timeout&lt;/code&gt;).

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

Unlike &lt;code&gt;comm_receive_char&lt;/code&gt;, this function uses an user-provided timeout.

=== INT $14/AH=$05 - comm_send_string ===

* AH = $05
* DS:DX = Input string to send.

Return:

* AX = Return code.

=== INT $14/AH=$06 - comm_send_block ===

* AH = $06
* CX = Buffer size, in bytes.
* DS:DX = Input buffer to send.

Return:

* AX = Return code.

=== INT $14/AH=$07 - comm_receive_block ===

* AH = $07
* CX = Buffer size, in bytes.
* DS:DX = Buffer to receive bytes to.

Return:

* AX = Return code.
* DX = Number of bytes successfully received.

=== INT $14/AH=$08 - comm_set_timeout ===

* AH = $08
* BX = Receive timeout (in frames; 0xFFFF - wait forever)
* CX = Send timeout (in frames; 0xFFFF - wait forever)

=== INT $14/AH=$09 - comm_set_baudrate ===

* AH = $09
* BX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

Only affects newly opened serial port connections.

=== INT $14/AH=$0A - comm_get_baudrate ===

* AH = $0A

Return:

* AX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

=== INT $14/AH=$0B - comm_set_cancel_key ===

* AH = $0B
* BX = Cancel key combination.

=== INT $14/AH=$0C - comm_get_cancel_key ===

* AH = $0C

Return:

* AX = Cancel key combination.

=== INT $14/AH=$0D - comm_xmodem ===

TODO</text>
    <sha1>10a086c1ac789043ffab65c993e2b15106cc59e1</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS</title>
  <ns>0</ns>
  <id>42</id>
  <revision>
    <id>327</id>
    <parentid>239</parentid>
    <timestamp>2024-07-27T13:44:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>fix missing ending parenthesis</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1422" xml:space="preserve">FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.

It provides the following functionality:

* bring-up code,
* interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware,
* 8x8 ASCII and kanji fonts,
* a monitor program, allowing FreyaOS recovery and updates via XMODEM.

Other functionality (like file system access) is instead included as part of [[WonderWitch/FreyaOS|FreyaOS]]' system libraries; some other functionality (like [[WonderWitch/libwwc|WonderSwan Color support]]) is implemented as part of the development tooling.

== Revisions ==

TODO

== Fonts ==

As part of its ROM image, FreyaBIOS provides two fonts:

* an 8x8 ASCII font,
* an 8x8 Shift-JIS kanji font - [http://hp.vector.co.jp/authors/VA002310/original.html ELISA FONT].

== Interrupts ==

* [[WonderWitch/FreyaBIOS/Exit|Exit]] (INT $10)
* [[WonderWitch/FreyaBIOS/Key|Key]] (INT $11)
* [[WonderWitch/FreyaBIOS/Display|Display]] (INT $12)
* [[WonderWitch/FreyaBIOS/Text|Text]] (INT $13)
* [[WonderWitch/FreyaBIOS/Communication|Communication]] (INT $14)
* [[WonderWitch/FreyaBIOS/Sound|Sound]] (INT $15)
* [[WonderWitch/FreyaBIOS/Timer|Timer]] (INT $16)
* [[WonderWitch/FreyaBIOS/System|System]] (INT $17)
* [[WonderWitch/FreyaBIOS/Bank|Bank]] (INT $18)

== Freya Monitor ==

TODO</text>
    <sha1>153973464cb7393762185299b48d5ff375b3906a</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>SoC</title>
  <ns>0</ns>
  <id>46</id>
  <revision>
    <id>328</id>
    <parentid>244</parentid>
    <timestamp>2024-07-28T11:58:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1789" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- MBC authentication successful?
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>05ce8088d42a27e52327ddc9c7c114c325ed9c9d</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>WonderWitch/FreyaBIOS/Bank</title>
  <ns>0</ns>
  <id>55</id>
  <revision>
    <id>329</id>
    <timestamp>2024-07-30T20:37:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Bank interrupt provides an abstraction layer for accessing the WonderWitch cartridge's flash and RAM.  == Interrupts ==  === INT $18/AH=$00 - bank_set_map ===  * AH = $00 * BX = Bank region * CX = Number of bank to map to region  Bank regions:  * 0 = SRAM (1000:xxxx) * 1 = ROM0 (2000:xxxx) * 2 = ROM1 (3000:xxxx)  === INT $18/AH=$01 - bank_get_map ===  * AH = $01 * BX = Bank region  Return:  * AX = Number of bank mapped to region  === INT $18/AH=$02 - bank_read_byte =..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1789" xml:space="preserve">The Bank interrupt provides an abstraction layer for accessing the WonderWitch cartridge's flash and RAM.

== Interrupts ==

=== INT $18/AH=$00 - bank_set_map ===

* AH = $00
* BX = Bank region
* CX = Number of bank to map to region

Bank regions:

* 0 = SRAM (1000:xxxx)
* 1 = ROM0 (2000:xxxx)
* 2 = ROM1 (3000:xxxx)

=== INT $18/AH=$01 - bank_get_map ===

* AH = $01
* BX = Bank region

Return:

* AX = Number of bank mapped to region

=== INT $18/AH=$02 - bank_read_byte ===

* AH = $02
* BX = Bank ID
* DX = Offset within bank

Return:

* AL = Byte read

Bank ID format:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 tiii iiii  iiii iiii
 |||| ||||  |||| ||||
 |+++-++++--++++-++++- Number of bank
 +-------------------- 0 = SRAM, 1 = Flash
&lt;/pre&gt;

=== INT $18/AH=$03 - bank_write_byte ===

* AH = $03
* BX = Bank ID
* CL = Byte to write
* DX = Offset within bank

=== INT $18/AH=$04 - bank_read_word ===

* AH = $04
* BX = Bank ID
* DX = Offset within bank

Return:

* AX = Word read

=== INT $18/AH=$05 - bank_write_word ===

* AH = $05
* BX = Bank ID
* CX = Word to write
* DX = Offset within bank

=== INT $18/AH=$06 - bank_read_block ===

* AH = $06
* BX = Bank ID
* CX = Number of bytes to read
* DX = Offset within bank
* DS:SI = Output buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$07 - bank_write_block ===

* AH = $07
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank
* DS:SI = Input buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$08 - bank_fill_block ===

* AH = $08
* AL = Fill value
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank

Sets &lt;code&gt;CX&lt;/code&gt; bytes in bank &lt;code&gt;BX&lt;/code&gt; to value &lt;code&gt;AL&lt;/code&gt; starting at offset &lt;code&gt;DX&lt;/code&gt;.

=== INT $18/AH=$09 - bank_erase_flash ===

* AH = $09
* BX = Bank ID</text>
    <sha1>70fb3919087d5ebc2e6f19266f63109c745d073c</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>Memory map</title>
  <ns>0</ns>
  <id>25</id>
  <revision>
    <id>330</id>
    <parentid>225</parentid>
    <timestamp>2024-08-02T16:57:40Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3890" xml:space="preserve">The WonderSwan's SoC uses a 20-bit physical memory map, split into three regions with distinct bus widths, timings, and access permissions;

{| class="wikitable"
|+ WonderSwan physical memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/2 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture. The CPU, [[Display]] and [[Sound]] components make use of data stored in a shared RAM in distinct segments of the 12.288 MHz SoC clock. This is in contrast to many other platforms which feature, for example, separate video memory. This allows the CPU to modify video and audio data without worrying about wait states or video timing; however, the video and audio components have location and alignment restrictions for data:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 4 bytes - far addresses)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
! rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

Note that an element being present on this map does not mean that the space cannot be utilized for other data. For example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space.

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper physical memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>0c3d38ba1af6c2d52a78fb0025a5f56afabe0561</sha1>
  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>Cartridge</title>
  <ns>0</ns>
  <id>45</id>
  <revision>
    <id>331</id>
    <parentid>192</parentid>
    <timestamp>2024-08-02T16:58:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="618" xml:space="preserve">== Cartridge bus ==

The SoC forwards some memory and I/O accesses to the cartridge bus:

* memory: physical addresses 0x10000 - 0xFFFFF,
* I/O: ports 0xC0 - 0xFF.

To facilitate this, the Memory/IO pin is used:

* When Memory/IO is asserted '''high''', all bus address pins specify the 20-bit linear memory address.
* When Memory/IO is asserted '''low''', bus address pins 0-7 specify the port address bits 0-7, bus address pins 8-15 are low, bus address pins 16-19 specify the port address bits 4-7.

== Interrupts ==

The cartridge bus provides an /IRQ pin which can be used by the cartridge to assert an interrupt.</text>
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<page arvcontinue="20240712193917|301">
  <title>Cartridge connector</title>
  <ns>0</ns>
  <id>44</id>
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    <id>332</id>
    <parentid>254</parentid>
    <timestamp>2024-08-02T16:58:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Signal descriptions */ linear -&gt; physical</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4825" xml:space="preserve">== Memory access ==

Both the ROM and the SRAM chip use a standard asynchronous memory interface.

It is presumed that:

* the CPU sets the address lines before each memory access while '''/OE''' or '''/WE''' respectively are still high,
* for writes the CPU sets the data lines with the falling edge of '''/WE''' (TODO: only confirmed for I/O writes),
* for reads the CPU latches the data lines on the subsequent rising edge of '''/OE'''.

Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.

Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.

== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| &lt;- CPU A15
... |  | -03| &lt;- CPU A10
... |  | -04| &lt;- CPU A11
... |  | -05| &lt;- CPU A9
... |  | -06| &lt;- CPU A8
... |  | -07| &lt;- CPU A13
... |  | -08| &lt;- CPU A14
... |  | -09| &lt;- CPU A12
... |  | -10| &lt;- CPU A7
... |  | -11| &lt;- CPU A6
... |  | -12| &lt;- CPU A5
... |  | -13| &lt;- CPU A4
... |  | -14| &lt;&gt; D15
... |  | -15| &lt;&gt; D14
... |  | -16| &lt;&gt; D7
... |  | -17| &lt;&gt; D6
... |  | -18| &lt;&gt; D5
... |  | -19| &lt;&gt; D4
... |  | -20| &lt;&gt; D3
... |  | -21| &lt;&gt; D2
... |  | -22| &lt;&gt; D1
... |  | -23| &lt;&gt; D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| &lt;- CPU A0
... |  | -27| &lt;- CPU A1
... |  | -28| &lt;- CPU A2
... |  | -29| &lt;- CPU A3
... |  | -30| &lt;- CPU A19
... |  | -31| &lt;- CPU A18
... |  | -32| &lt;- CPU A17
... |  | -33| &lt;- CPU A16
... |  | -34| &lt;&gt; D8
... |  | -35| &lt;&gt; D9
... |  | -36| &lt;&gt; D10
... |  | -37| &lt;&gt; D11
... |  | -38| &lt;&gt; D12
... |  | -39| &lt;&gt; D13
... |  | -40| &lt;- /RESET
... |  | -41| -&gt; /MBC
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -46| -&gt; /IRQ (Interrupt request)
____/  | -47| &lt;- CLK
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;

== Mechanical details ==

{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}

== Signal descriptions ==

* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to physical addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.

== Timing requirements ==

The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.

TODO: Verify how using ROM/SRAM wait states affects this.

== Authentication handshake ==

Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:

* '''/MBC''' is held high. '''A0'''-'''A3''' are set to 0xA and '''A16'''-'''A19''' are set to 0x5.
* On a rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: &lt;code&gt;1000101000101000000111&lt;/code&gt;.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.

On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.

An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].</text>
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  </revision>
</page>
<page arvcontinue="20240712193917|301">
  <title>NEC V30MZ</title>
  <ns>0</ns>
  <id>39</id>
  <revision>
    <id>333</id>
    <parentid>207</parentid>
    <timestamp>2024-08-02T18:18:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add architecture, sketch instruction set</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2907" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''')
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''')
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''')
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''')
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt;
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt;
** '''SP'''
** '''BP'''
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - code segment,
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - data segment,
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - additional data segment,
** '''SS''' - stack segment.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - instruction pointer; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - 16-bit processor flag register.

=== Flags ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 m111 odit  sz0a 0p1c
 |    ||||  || |  | |
 |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
 |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
 |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
 |    ||||  |+-------- Zero (Z)
 |    ||||  +--------- Sign (S)
 |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
 |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
 |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
 |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
 +-------------------- Mode (MD)
&lt;/pre&gt;

&lt;!-- 

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

--&gt;

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>2b50de1198a5ebd24957830d232dd07c077488a1</sha1>
  </revision>
  <revision>
    <id>334</id>
    <parentid>333</parentid>
    <timestamp>2024-08-02T18:30:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Registers */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3940" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''')
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''')
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''')
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''')
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt;
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt;
** '''SP''' - stack pointer; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses).
** '''BP'''
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - code segment,
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - data segment,
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - additional data segment,
** '''SS''' - stack segment.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - instruction pointer; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.

=== Flags ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 m111 odit  sz0a 0p1c
 |    ||||  || |  | |
 |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
 |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
 |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
 |    ||||  |+-------- Zero (Z)
 |    ||||  +--------- Sign (S)
 |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
 |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
 |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
 |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
 +-------------------- Mode (MD)
&lt;/pre&gt;

&lt;!-- 

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

--&gt;

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>d60a3e82636ac390ed1beb66e9c3a76a6f88b4a9</sha1>
  </revision>
  <revision>
    <id>335</id>
    <parentid>334</parentid>
    <timestamp>2024-08-02T19:01:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>fix formatting</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3929" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''')
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''')
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''')
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''')
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt;
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt;
** '''SP''' - stack pointer; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses).
** '''BP'''
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - code segment,
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - data segment,
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - additional data segment,
** '''SS''' - stack segment.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - instruction pointer; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.

=== Flags ===

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>a59bed3dd6d5f5b6cb069f0873a41e063b487d15</sha1>
  </revision>
  <revision>
    <id>336</id>
    <parentid>335</parentid>
    <timestamp>2024-08-03T07:27:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Flags */ elaborate</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5433" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''')
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''')
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''')
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''')
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt;
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt;
** '''SP''' - stack pointer; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses).
** '''BP'''
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - code segment,
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - data segment,
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - additional data segment,
** '''SS''' - stack segment.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - instruction pointer; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.

=== Flags ===

The V30MZ features the following flags:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

In general, they are set by operations as follows:

* '''Carry''' - stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.
* '''Parity''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.
* '''Auxillary Carry''' - stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.
* '''Zero''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.
* '''Sign''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.
* '''Overflow''' - set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

There are also programmer-controlled control flags:

* '''Single Step''' - if set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.
* '''Interrupt Enable''' - if set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.
* '''Direction''' - if set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.
* '''Mode''' - used for 8080 emulation mode in other V20/V30-family chips, does nothing on V30MZ

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>cae55ac0b8861310ddc8e0fef2be17fbe59ee2ef</sha1>
  </revision>
  <revision>
    <id>337</id>
    <parentid>336</parentid>
    <timestamp>2024-08-03T09:01:56Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Registers */ add register names</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5643" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''') - the ''accumulator'' register,
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''') - the ''base'' register,
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''') - the ''count'' register,
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''') - the ''data'' register,
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt; - the ''source index'' register,
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt; - the ''destination index'' register,
** '''SP''' - the ''stack pointer''; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses),
** '''BP''' - the ''base pointer'.
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - code segment,
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - data segment,
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - additional data segment,
** '''SS''' - stack segment.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - instruction pointer; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.

=== Flags ===

The V30MZ features the following flags:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

In general, they are set by operations as follows:

* '''Carry''' - stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.
* '''Parity''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.
* '''Auxillary Carry''' - stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.
* '''Zero''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.
* '''Sign''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.
* '''Overflow''' - set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

There are also programmer-controlled control flags:

* '''Single Step''' - if set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.
* '''Interrupt Enable''' - if set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.
* '''Direction''' - if set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.
* '''Mode''' - used for 8080 emulation mode in other V20/V30-family chips, does nothing on V30MZ

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>31db6ebc3e6f963f4ab634aa37b5aa1dc8f25715</sha1>
  </revision>
  <revision>
    <id>338</id>
    <parentid>337</parentid>
    <timestamp>2024-08-03T09:02:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Architecture */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5706" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''') - the ''accumulator'' register,
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''') - the ''base'' register,
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''') - the ''count'' register,
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''') - the ''data'' register,
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt; - the ''source index'' register,
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt; - the ''destination index'' register,
** '''SP''' - the ''stack pointer''; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses),
** '''BP''' - the ''base pointer''.
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - the ''code segment'',
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - the ''data segment'',
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - the ''extra segment''; an additional data segment,
** '''SS''' - the ''stack segment''.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - the ''instruction pointer''; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - the 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.

=== Flags ===

The V30MZ features the following flags:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

In general, they are set by operations as follows:

* '''Carry''' - stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.
* '''Parity''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.
* '''Auxillary Carry''' - stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.
* '''Zero''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.
* '''Sign''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.
* '''Overflow''' - set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

There are also programmer-controlled control flags:

* '''Single Step''' - if set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.
* '''Interrupt Enable''' - if set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.
* '''Direction''' - if set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.
* '''Mode''' - used for 8080 emulation mode in other V20/V30-family chips, does nothing on V30MZ

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>73e26fa0ecac64527386574f601440bcd9d4bdfe</sha1>
  </revision>
  <revision>
    <id>339</id>
    <parentid>338</parentid>
    <timestamp>2024-08-03T09:02:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5717" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.

== Architecture ==

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

=== Registers ===

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''') - the ''accumulator'' register,
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''') - the ''base'' register,
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''') - the ''count'' register,
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''') - the ''data'' register,
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt; - the ''source index'' register,
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt; - the ''destination index'' register,
** '''SP''' - the ''stack pointer''; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses),
** '''BP''' - the ''base pointer''.
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - the ''code segment'',
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - the ''data segment'',
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - the ''extra segment''; an additional data segment,
** '''SS''' - the ''stack segment''.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - the ''instruction pointer''; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - the 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.

=== Flags ===

The V30MZ features the following flags:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

In general, they are set by operations as follows:

* '''Carry''' - stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.
* '''Parity''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.
* '''Auxillary Carry''' - stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.
* '''Zero''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.
* '''Sign''' - set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.
* '''Overflow''' - set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

There are also programmer-controlled control flags:

* '''Single Step''' - if set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.
* '''Interrupt Enable''' - if set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.
* '''Direction''' - if set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.
* '''Mode''' - used for 8080 emulation mode in other V20/V30-family chips, does nothing on V30MZ

&lt;!--

== Instruction set ==

{| class="wikitable sortable"
|+ V30MZ Instruction Set
|-
! Instruction
! Opcode (hex)
! Opcode (bin)
! Bytes
! Cycles
! Flags
! NEC mnemonic
! Notes
|-
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
| &lt;tt&gt;04&lt;/tt&gt;
| &lt;tt&gt;00000100&lt;/tt&gt;
| 2
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AL, imm8&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD AX, imm16&lt;/tt&gt;
| &lt;tt&gt;05&lt;/tt&gt;
| &lt;tt&gt;00000101&lt;/tt&gt;
| 3
| 1
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD AW, imm16&lt;/tt&gt;
|
|-
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
| &lt;tt&gt;80 rm&lt;/tt&gt; / &lt;tt&gt;82 rm&lt;/tt&gt;
| &lt;tt&gt;100000.0 oo000mm&lt;/tt&gt;
| 3-5
| 3
| &lt;tt&gt;O...SZAPC&lt;/tt&gt;
| &lt;tt&gt;ADD mem8, imm8&lt;/tt&gt;
|
|-
|}

--&gt;

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
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    <id>345</id>
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      <id>351</id>
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    <comment>move sections out to sub-pages</comment>
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    <text bytes="988" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

== Format ==

The NEC V30MZ datasheet provides distinct names for opcodes, flags and registers, which the wiki refers to as ''NEC names''. As all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what is used throughout. For registers and flags, distinct NEC names are presented in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

== Sections ==

* [[NEC V30MZ registers]]
* [[NEC V30MZ flags]]
* [[NEC V30MZ instruction set]]
* [[NEC V30MZ interrupts]]

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
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      <id>351</id>
    </contributor>
    <comment>Created page with " = NEC V30MZ flags =  == Layout ==  The V30MZ processor features a 16-bit flag register:   15  bit  8  7  bit  0   ---- ----  ---- ----   m111 odit  sz0a 0p1c   |    ||||  || |  | |   |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)   |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)   |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)   |    ||||  |+-------- Zero (Z)   |    ||||  +--------- Sign (S)   |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)..."</comment>
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= NEC V30MZ flags =

== Layout ==

The V30MZ processor features a 16-bit flag register:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

== Status flags ==

The following flags are typically modified by instructions:

=== Carry ===

Stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.

=== Parity ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.

=== Auxillary Carry ===

Stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.

=== Zero ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.

=== Sign ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.

=== Overflow ===

Set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

== Control flags ==

The following flags are typically modified by the developer:

=== Single step ===

If set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.

Alternatively referred to as the ''trap flag''.

=== Interrupt enable ===

If set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.

=== Direction ===

If set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.

=== Mode ===

This flag does nothing on the NEC V30MZ. It was used to implement 8080 emulation mode in other V20/V30-family chips, but this functionality has been removed in the V30MZ.</text>
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      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "= NEC V30MZ registers =  * Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers: ** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''') - the ''accumulator'' register, ** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''') - the ''base'' register, ** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''') - the ''count'' register, ** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''') - the ''data'' register, * Four additional 16-bit registers: *..."</comment>
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    <format>text/x-wiki</format>
    <text bytes="2141" xml:space="preserve">= NEC V30MZ registers =

* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''') - the ''accumulator'' register,
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''') - the ''base'' register,
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''') - the ''count'' register,
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''') - the ''data'' register,
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt; - the ''source index'' register,
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt; - the ''destination index'' register,
** '''SP''' - the ''stack pointer''; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses),
** '''BP''' - the ''base pointer''.
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - the ''code segment'',
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - the ''data segment'',
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - the ''extra segment''; an additional data segment,
** '''SS''' - the ''stack segment''.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - the ''instruction pointer''; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - the 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.</text>
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    <minor/>
    <comment>/* NEC V30MZ registers */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2116" xml:space="preserve">* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
** '''AX'''&lt;sup&gt;AW&lt;/sup&gt; ('''AL''', '''AH''') - the ''accumulator'' register,
** '''BX'''&lt;sup&gt;BW&lt;/sup&gt; ('''BL''', '''BH''') - the ''base'' register,
** '''CX'''&lt;sup&gt;CW&lt;/sup&gt; ('''CL''', '''CH''') - the ''count'' register,
** '''DX'''&lt;sup&gt;DW&lt;/sup&gt; ('''DL''', '''DH''') - the ''data'' register,
* Four additional 16-bit registers:
** '''SI'''&lt;sup&gt;IX&lt;/sup&gt; - the ''source index'' register,
** '''DI'''&lt;sup&gt;IY&lt;/sup&gt; - the ''destination index'' register,
** '''SP''' - the ''stack pointer''; the stack is always addressed in the stack segment (so as &lt;code&gt;SS:SP&lt;/code&gt; far addresses),
** '''BP''' - the ''base pointer''.
* Four segment registers:
** '''CS'''&lt;sup&gt;PS&lt;/sup&gt; - the ''code segment'',
** '''DS'''&lt;sup&gt;DS0&lt;/sup&gt; - the ''data segment'',
** '''ES'''&lt;sup&gt;DS1&lt;/sup&gt; - the ''extra segment''; an additional data segment,
** '''SS''' - the ''stack segment''.
* '''IP'''&lt;sup&gt;PC&lt;/sup&gt; - the ''instruction pointer''; instructions are always addressed in the code segment (so as &lt;code&gt;CS:IP&lt;/code&gt; far addresses),
* '''FLAGS'''&lt;sup&gt;PSW&lt;/sup&gt; - the 16-bit processor flag register.

While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:

* '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
* '''CX''' is used for loop and repeat instructions as a counter.
* '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
* '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
* Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.</text>
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  <title>NEC V30MZ interrupts</title>
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    <comment>Created page with "The NEC V30MZ provides six of the eight interrupts provided by the 80186.  == Interrupts ==  === INT 0 - Divide Error ===  This interrupt is emitted as the result of a DIV&lt;sup&gt;IDIV&lt;/sup&gt; or DIVU&lt;sup&gt;DIV&lt;/sup&gt; instruction.  === INT 1 - Single Step/Break ===  This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interru..."</comment>
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    <text bytes="1561" xml:space="preserve">The NEC V30MZ provides six of the eight interrupts provided by the 80186.

== Interrupts ==

=== INT 0 - Divide Error ===

This interrupt is emitted as the result of a DIV&lt;sup&gt;IDIV&lt;/sup&gt; or DIVU&lt;sup&gt;DIV&lt;/sup&gt; instruction.

=== INT 1 - Single Step/Break ===

This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interrupt, allowing the user to store state and perform debug activities; it is then restored when returning from the interrupt, by restoring the original processor flags stored on the stack.

=== INT 2 - Non-Maskable interrupt (NMI) ===

This interrupt is emitted when the SoC requests a non-maskable interrupt. On the WonderSwan, the condtions for emitting an NMI are configured by the relevant I/O port.

=== INT 3 - Breakpoint ===

This interrupt is emitted by the INT 3&lt;sup&gt;BRK&lt;/sup&gt; instruction. Unlike other unconditional interrupt instructions, it is encoded with only one byte.

=== INT 4 - Overflow ===

This interrupt is emitted by the INTO&lt;sup&gt;BRKV&lt;/sup&gt; instruction, if the overflow flag is set while it is being executed.

=== INT 5 - Array Bounds ===

This interrupt is emitted only by the BOUND&lt;sup&gt;CHKIND&lt;/sup&gt; instruction.

== Timing ==

TODO

== Notes ==

* The following 80186 interrupts are not implemented:
** INT 6 - Unused Opcode - the V30MZ treats most unimplemented instructions as NOPs.
** INT 7 - ESC Opcode - the V30MZ, likewise, treats these instructions as NOPs.</text>
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  <title>I/O port map</title>
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      <id>351</id>
    </contributor>
    <comment>/* I/O port map */ fix $00 bit order</comment>
    <model>wikitext</model>
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    <text bytes="21483" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vv.s&lt;/tt&gt;
| RW8
| Volume segment status (v), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| Sound Channel Output Right
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| Sound Channel Output Left
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| Sound Channel Output Sum
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| Sound Speaker Main Volume&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>1af50f35debc3be260a61519a0ac04f1c13df7af</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>Interrupts</title>
  <ns>0</ns>
  <id>22</id>
  <revision>
    <id>351</id>
    <parentid>247</parentid>
    <timestamp>2024-08-22T13:10:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupts */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3090" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while enabled and the prerequisite condition is true,
** Edge - will only be requested while enabled the moment the prerequisite condition ''becomes'' true.

Level interrupts will be immediately retriggered upon acknowledging unless they are disabled, or their prerequisite condition is cleared (for example, a byte is read from the UART). Edge interrupts are only triggered the moment they happen; acknowledging them is sufficient until the next time one is issued (for example, until the next vertical blank).

The user can additionally make use of all 256 available interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector Offset}}
=== Interrupt Vector Offset ($B0 write) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| |
++++-+---- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Vector Request}}

=== Interrupt Vector Request ($B0 read) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.
&lt;/pre&gt;

* Bits &lt;code&gt;7 .. 3&lt;/code&gt; of this will always equal the user-provided vector offset.
* Bits &lt;code&gt;2 .. 0&lt;/code&gt; of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal &lt;code&gt;0&lt;/code&gt;.

{{Anchor|Interrupt Enable}}

=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

{{Anchor|Interrupt Status}}
=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>6c9ecc187c0ea6526f8280b58b1ca326baec455e</sha1>
  </revision>
  <revision>
    <id>352</id>
    <parentid>351</parentid>
    <timestamp>2024-08-22T13:11:03Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupt Enable ($B2) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3199" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while enabled and the prerequisite condition is true,
** Edge - will only be requested while enabled the moment the prerequisite condition ''becomes'' true.

Level interrupts will be immediately retriggered upon acknowledging unless they are disabled, or their prerequisite condition is cleared (for example, a byte is read from the UART). Edge interrupts are only triggered the moment they happen; acknowledging them is sufficient until the next time one is issued (for example, until the next vertical blank).

The user can additionally make use of all 256 available interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector Offset}}
=== Interrupt Vector Offset ($B0 write) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| |
++++-+---- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Vector Request}}

=== Interrupt Vector Request ($B0 read) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.
&lt;/pre&gt;

* Bits &lt;code&gt;7 .. 3&lt;/code&gt; of this will always equal the user-provided vector offset.
* Bits &lt;code&gt;2 .. 0&lt;/code&gt; of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal &lt;code&gt;0&lt;/code&gt;.

{{Anchor|Interrupt Enable}}

=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

Contrary to other systems, this also controls whether interrupts set the relevant bit in Interrupt Status.

{{Anchor|Interrupt Status}}

=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>9adaf00049c8ce0ec2a7e506e67d871114dba16d</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>Sound</title>
  <ns>0</ns>
  <id>27</id>
  <revision>
    <id>353</id>
    <parentid>276</parentid>
    <timestamp>2024-08-25T10:26:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Channel 4 Noise Control ($8E) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9450" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
425? llsh
|||  ||||
|||  |||+- Hold Ch1-4 output updates
|||  ||+-- Use 3072000 Hz CPU clock for sweep
|||  ++--- Hold noise LFSR output
|||        (Differences between bit 2/3
|||        behavior are unknown)
||+------- Force L10/R10 outputs to 0x55
|+-------- Force Ch1-4 outputs to 0x02
+--------- Force Ch1-4 outputs to 0x04
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>74d00fdcd31ce56be4e7ee420cbd85b5637ed91b</sha1>
  </revision>
  <revision>
    <id>356</id>
    <parentid>353</parentid>
    <timestamp>2024-09-10T19:40:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Test ($95) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9404" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;</text>
    <sha1>e65e156f4821136007fb4f92db18c31e83024b30</sha1>
  </revision>
  <revision>
    <id>357</id>
    <parentid>356</parentid>
    <timestamp>2024-09-13T14:17:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10073" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>ebf1cc8d201187a0927a356d6e7b327e247f13ed</sha1>
  </revision>
  <revision>
    <id>359</id>
    <parentid>357</parentid>
    <timestamp>2024-09-13T14:19:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10134" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of the ''wavetable'', and needs to be scaled accordingly for a given waveform when performing music playback.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>f04ecf5ba67406e88699ca5a27177c17563adfd2</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>DMA</title>
  <ns>0</ns>
  <id>31</id>
  <revision>
    <id>354</id>
    <parentid>238</parentid>
    <timestamp>2024-09-09T17:00:00Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* General DMA */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5163" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

The CPU is stalled immediately after General DMA is enabled; the enable bit is cleared after a completed GDMA operation.

General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

General DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of processing a transfer. If GDMA is enabled for an address that is already invalid, zero cycles are taken up.

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

== Sound DMA ==

Sound DMA allows copying sample data to either Channel 2 or Hyper Voice automatically while incurring a much lower cost than that of a CPU interrupt.

Features:

* 4000, 6000, 12000, 24000 Hz sample rates.
* '''Auto-repeat''': If enabled, every time the length counter reaches 0, a shadowed copy of the offset and length as written to the I/O ports will be restored. If disabled, bit 7 will automatically clear on transfer completion, same as with General DMA.
* '''Holding''': If enabled, the offset/length counters will be paused, and $00 will be written on every Sound DMA tick as opposed to the value in memory. This does not impact the timing of Sound DMA.

When playing back sound, the visible ports ($4A-$4C, $4E-$50) are the ones updated live; any edits to them are reflected immediately, as well as written to the shadow copy used for auto-repeat.

The enable/disable bit of Sound DMA does not affect the offset/length counters in any way; for example, if a sample is stopped mid-playthrough, then started again, it will pick up right where it left off.

Unlike General DMA, Sound DMA copies data per byte. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens the duration of Sound DMA. Due to its need to access the external cartridge bus, Sound DMA must use cycles normally reserved for the CPU; it uses &lt;code&gt;6 + N&lt;/code&gt; cycles every 128 cycles, always starting from cycle &lt;code&gt;117 mod 128&lt;/code&gt;. &lt;code&gt;N&lt;/code&gt; refers to the access time of the area from which audio is being streamed from, and is typically 1 cycle.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>49d23bdac49092bac1942b81786e4d749067deb4</sha1>
  </revision>
  <revision>
    <id>355</id>
    <parentid>354</parentid>
    <timestamp>2024-09-10T19:15:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* General DMA */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5211" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

The CPU is stalled immediately after General DMA is enabled; the enable bit is cleared after a completed GDMA operation.

General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

General DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of processing a transfer.

Note that the 5-cycle cost is not spent for DMA requests for invalid addresses or of length zero; such scenarios take up no cycles.

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

== Sound DMA ==

Sound DMA allows copying sample data to either Channel 2 or Hyper Voice automatically while incurring a much lower cost than that of a CPU interrupt.

Features:

* 4000, 6000, 12000, 24000 Hz sample rates.
* '''Auto-repeat''': If enabled, every time the length counter reaches 0, a shadowed copy of the offset and length as written to the I/O ports will be restored. If disabled, bit 7 will automatically clear on transfer completion, same as with General DMA.
* '''Holding''': If enabled, the offset/length counters will be paused, and $00 will be written on every Sound DMA tick as opposed to the value in memory. This does not impact the timing of Sound DMA.

When playing back sound, the visible ports ($4A-$4C, $4E-$50) are the ones updated live; any edits to them are reflected immediately, as well as written to the shadow copy used for auto-repeat.

The enable/disable bit of Sound DMA does not affect the offset/length counters in any way; for example, if a sample is stopped mid-playthrough, then started again, it will pick up right where it left off.

Unlike General DMA, Sound DMA copies data per byte. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens the duration of Sound DMA. Due to its need to access the external cartridge bus, Sound DMA must use cycles normally reserved for the CPU; it uses &lt;code&gt;6 + N&lt;/code&gt; cycles every 128 cycles, always starting from cycle &lt;code&gt;117 mod 128&lt;/code&gt;. &lt;code&gt;N&lt;/code&gt; refers to the access time of the area from which audio is being streamed from, and is typically 1 cycle.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>7ddda5986a9523d2c04e6dd58ad113d9d6625106</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>358</id>
    <parentid>347</parentid>
    <timestamp>2024-09-13T14:19:20Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21644" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0B
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vvhs&lt;/tt&gt;
| RW8
| Volume segments (v), Headphone segment (h), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>ea04971e51b29e89400f1b2822f4169cf4e74d89</sha1>
  </revision>
  <revision>
    <id>363</id>
    <parentid>358</parentid>
    <timestamp>2024-09-13T14:38:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */ fix typo</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21644" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vvhs&lt;/tt&gt;
| RW8
| Volume segments (v), Headphone segment (h), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>53495ea79de8474e1b9b86fbfc23cf4ccb201029</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>360</id>
    <parentid>350</parentid>
    <timestamp>2024-09-13T14:26:40Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Status ($1A) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="17865" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD Enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

{{Anchor|LCD Icon Control}}
=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>f537356c0174f36161e11d0c4a1c3f5ede2db060</sha1>
  </revision>
  <revision>
    <id>361</id>
    <parentid>360</parentid>
    <timestamp>2024-09-13T14:27:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Control ($14) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18206" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The LCD enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that segments continue displaying regardless of this configuration.

Note that port $1A also provides an LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>fb84b7419a0fc1d7d5851f69005e552eb64c53a5</sha1>
  </revision>
  <revision>
    <id>362</id>
    <parentid>361</parentid>
    <timestamp>2024-09-13T14:34:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* LCD Status ($1A) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18226" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The LCD enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that segments continue displaying regardless of this configuration.

Note that port $1A also provides an LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>8dae2639a7129bdd6ac7f3bfe58723cfb3b9e955</sha1>
  </revision>
  <revision>
    <id>394</id>
    <parentid>362</parentid>
    <timestamp>2024-11-20T02:28:29Z</timestamp>
    <contributor>
      <username>Tepples</username>
      <id>6</id>
    </contributor>
    <comment>/* LCD Final Line ($16) */ I'd suspect row inversion</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18499" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The LCD enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that segments continue displaying regardless of this configuration.

Note that port $1A also provides an LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
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</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/FreyaBIOS/Text</title>
  <ns>0</ns>
  <id>53</id>
  <revision>
    <id>364</id>
    <parentid>324</parentid>
    <timestamp>2024-10-16T15:25:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>Fix typo</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4427" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BL = X position in text window
* BH = Y position in text window
* CL = Width of area to write number in
* CH = Flags
* DX = Number
* DS:SI = Output buffer (optional, see flags)

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:SI)
&lt;/pre&gt;

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
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  </revision>
  <revision>
    <id>389</id>
    <parentid>364</parentid>
    <timestamp>2024-10-20T08:23:10Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4571" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BL = X position in text window
* BH = Y position in text window
* CL = Width of area to write number in
* CH = Flags
* DX = Number
* DS:SI = Output buffer (optional, see flags)

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:SI)
&lt;/pre&gt;

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>55179b226aae9b24f1f50a0c0a580ad4cd8aa719</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/Filesystem</title>
  <ns>0</ns>
  <id>59</id>
  <revision>
    <id>365</id>
    <timestamp>2024-10-17T14:21:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Mount points ==  {| class="wikitable" |+ FreyaOS mount points |- ! Path !! File data location !! File table location !! File table size (entries) !! Description |- | &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 || |- | &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 || |- | &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 ||  |}  == File table entry format ==  {| class="wikitable" |+ Header contents |- ! Offset !! Length !! Conten..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1507" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || Location in CPU address space (segment:offset)
|-
| 44 || 4 || Total file size, in bytes, excluding the header.
|-
| 48 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time - seconds since January 1st, 2000.
|-
| 56 || 4 || TODO
|-
| 60 || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>8e7bd8e15d95adc17a95cc7a5e40cf89bd92a68c</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch .fx files</title>
  <ns>0</ns>
  <id>6</id>
  <revision>
    <id>366</id>
    <parentid>259</parentid>
    <timestamp>2024-10-17T14:21:54Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="701" xml:space="preserve">[[WonderWitch/FreyaOS|FreyaOS]] uses [[XMODEM]] transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header&lt;ref&gt;XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block&lt;/ref&gt;.

== Format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;code&gt;#!ws&lt;/code&gt;
|-
| $04 || 60 || Padding; typically 0xFF.
|-
| $40 || 64 || [[WonderWitch/Filesystem|File entry]] (pointers relative to 0000:0000).
|}</text>
    <sha1>dd3a5d9ed5a8acde26cc7cb4a66c682fb6249334</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>367</id>
    <parentid>310</parentid>
    <timestamp>2024-10-17T14:22:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1714" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>8f41898fca4172bf24ee5a70e86e9e41c97089e7</sha1>
  </revision>
  <revision>
    <id>368</id>
    <parentid>367</parentid>
    <timestamp>2024-10-18T15:33:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1799" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Executable|Executable]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>48075adf7156cc54cf42ad4698aae87dcca9381d</sha1>
  </revision>
  <revision>
    <id>371</id>
    <parentid>368</parentid>
    <timestamp>2024-10-18T17:46:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1793" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>9b221ade48597f63860dee91699fa3cc391f4c52</sha1>
  </revision>
  <revision>
    <id>381</id>
    <parentid>371</parentid>
    <timestamp>2024-10-19T19:01:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1834" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>78c9cf9e864511aa08a00e40250a3124692373af</sha1>
  </revision>
  <revision>
    <id>398</id>
    <parentid>381</parentid>
    <timestamp>2024-11-24T17:46:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* WonderWitch */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1869" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* [[EEPROM]] (2001)
* [[Real-Time Clock]] (2003)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>009244dd9b2eac56848caea56f674e55d095f58f</sha1>
  </revision>
  <revision>
    <id>399</id>
    <parentid>398</parentid>
    <timestamp>2024-11-24T17:48:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Cartridge components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1998" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>30a738d9252399d740abfc0489bb57d09fdc384f</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/IL</title>
  <ns>0</ns>
  <id>60</id>
  <revision>
    <id>369</id>
    <timestamp>2024-10-18T15:53:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "Indirect libraries (IL) are a FreyaOS feature designed to work around the 64KB segment limit of applications by offloading helper functionality to separate library binaries.  == Calling convention ==  All functions exposed by an IL use the standard 8086 C calling convention - cdecl.  * The stack is allocated and cleaned by the caller. * &lt;code&gt;AX&lt;/code&gt;, &lt;code&gt;BX&lt;/code&gt;, &lt;code&gt;CX&lt;/code&gt;, &lt;code&gt;DX&lt;/code&gt; can be modified freely by the callee. All other registers must be res..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2364" xml:space="preserve">Indirect libraries (IL) are a FreyaOS feature designed to work around the 64KB segment limit of applications by offloading helper functionality to separate library binaries.

== Calling convention ==

All functions exposed by an IL use the standard 8086 C calling convention - cdecl.

* The stack is allocated and cleaned by the caller.
* &lt;code&gt;AX&lt;/code&gt;, &lt;code&gt;BX&lt;/code&gt;, &lt;code&gt;CX&lt;/code&gt;, &lt;code&gt;DX&lt;/code&gt; can be modified freely by the callee. All other registers must be restored before returning to its caller.

Note that &lt;code&gt;DS&lt;/code&gt; is not changed upon entry and points to the caller function's data segment.

== Format ==

=== Header ===

The location of the IL header is provided by the [[WonderWitch/Filesystem|file entry]].

{| class="wikitable"
|+ Header structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || File name; zero-terminated Shift-JIS string.
|-
| 4 || 2 || Number of functions, including &lt;code&gt;get_info&lt;/code&gt;.
|-
| 6 || 4 || Far pointer to the function &lt;code&gt;ILinfo __far *get_info(void);&lt;/code&gt;.

The function returns a pointer to the IL information structure with a valid segment (for example, sourced from CS).
|-
| 10... || 4... || Further instruction pointers according to the IL's specification.
|}

=== IL information ===

{| class="wikitable"
|+ IL information structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || Far pointer to a zero-terminated string containing the IL class name; the segment is ignored.
|-
| 4 || 4 || Far pointer to a zero-terminated string containing the IL name; the segment is ignored.
|-
| 8 || 4 || Far pointer to a zero-terminated string containing the IL version; the segment is ignored.
|-
| 12 || 4 || Far pointer to a zero-terminated string containing the IL description; the segment is ignored.
|-
| 16 || 4 || Far pointer to an array of far pointers to zero-terminated strings containing the IL dependency list; the segment is ignored.
|}


== List of ILs ==

=== Built-in ILs ===

These ILs are included in FreyaOS.

* [[WonderWitch/IL/IlibIL|IlibIL]]
* [[WonderWitch/IL/ProcIL|ProcIL]]
* [[WonderWitch/IL/FsIL|FsIL]]
* [[WonderWitch/IL/RunnableIL|RunnableIL]]
* [[WonderWitch/IL/StreamIL|StreamIL]]

=== SDK-provided ILs ===

These ILs are not included in FreyaOS, but are provided on the WonderWitch disc.

* [[WonderWitch/IL/SoundIL|SoundIL]]
* [[WonderWitch/IL/ResumeIL|ResumeIL]]</text>
    <sha1>0baaea4f0670f32d35843baa14e155e472ae406e</sha1>
  </revision>
  <revision>
    <id>370</id>
    <parentid>369</parentid>
    <timestamp>2024-10-18T16:02:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Header */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2324" xml:space="preserve">Indirect libraries (IL) are a FreyaOS feature designed to work around the 64KB segment limit of applications by offloading helper functionality to separate library binaries.

== Calling convention ==

All functions exposed by an IL use the standard 8086 C calling convention - cdecl.

* The stack is allocated and cleaned by the caller.
* &lt;code&gt;AX&lt;/code&gt;, &lt;code&gt;BX&lt;/code&gt;, &lt;code&gt;CX&lt;/code&gt;, &lt;code&gt;DX&lt;/code&gt; can be modified freely by the callee. All other registers must be restored before returning to its caller.

Note that &lt;code&gt;DS&lt;/code&gt; is not changed upon entry and points to the caller function's data segment.

== Format ==

=== Header ===

The location of the IL header is provided by the [[WonderWitch/Filesystem|file entry]].

{| class="wikitable"
|+ Header structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || TODO
|-
| 4 || 2 || Number of functions, including &lt;code&gt;get_info&lt;/code&gt;.
|-
| 6 || 4 || Far pointer to the function &lt;code&gt;ILinfo __far *get_info(void);&lt;/code&gt;.

The function returns a pointer to the IL information structure with a valid segment (for example, sourced from CS).
|-
| 10... || 4... || Further instruction pointers according to the IL's specification.
|}

=== IL information ===

{| class="wikitable"
|+ IL information structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || Far pointer to a zero-terminated string containing the IL class name; the segment is ignored.
|-
| 4 || 4 || Far pointer to a zero-terminated string containing the IL name; the segment is ignored.
|-
| 8 || 4 || Far pointer to a zero-terminated string containing the IL version; the segment is ignored.
|-
| 12 || 4 || Far pointer to a zero-terminated string containing the IL description; the segment is ignored.
|-
| 16 || 4 || Far pointer to an array of far pointers to zero-terminated strings containing the IL dependency list; the segment is ignored.
|}


== List of ILs ==

=== Built-in ILs ===

These ILs are included in FreyaOS.

* [[WonderWitch/IL/IlibIL|IlibIL]]
* [[WonderWitch/IL/ProcIL|ProcIL]]
* [[WonderWitch/IL/FsIL|FsIL]]
* [[WonderWitch/IL/RunnableIL|RunnableIL]]
* [[WonderWitch/IL/StreamIL|StreamIL]]

=== SDK-provided ILs ===

These ILs are not included in FreyaOS, but are provided on the WonderWitch disc.

* [[WonderWitch/IL/SoundIL|SoundIL]]
* [[WonderWitch/IL/ResumeIL|ResumeIL]]</text>
    <sha1>9e634a68b8d97cc668b63f70ab570f6295dbbb05</sha1>
  </revision>
  <revision>
    <id>380</id>
    <parentid>370</parentid>
    <timestamp>2024-10-19T17:12:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2441" xml:space="preserve">Indirect libraries (IL) are a FreyaOS feature designed to work around the 64KB segment limit of applications by offloading helper functionality to separate library binaries.

Traditionally, ILs use a file system name prefixed with &lt;code&gt;@&lt;/code&gt;; for example, &lt;code&gt;@proc&lt;/code&gt; for ProcIL.

== Calling convention ==

All functions exposed by an IL use the standard 8086 C calling convention - cdecl.

* The stack is allocated and cleaned by the caller.
* &lt;code&gt;AX&lt;/code&gt;, &lt;code&gt;BX&lt;/code&gt;, &lt;code&gt;CX&lt;/code&gt;, &lt;code&gt;DX&lt;/code&gt; can be modified freely by the callee. All other registers must be restored before returning to its caller.

Note that &lt;code&gt;DS&lt;/code&gt; is not changed upon entry and points to the caller function's data segment.

== Format ==

=== Header ===

The location of the IL header is provided by the [[WonderWitch/Filesystem|file entry]].

{| class="wikitable"
|+ Header structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || TODO
|-
| 4 || 2 || Number of functions, including &lt;code&gt;get_info&lt;/code&gt;.
|-
| 6 || 4 || Far pointer to the function &lt;code&gt;ILinfo __far *get_info(void);&lt;/code&gt;.

The function returns a pointer to the IL information structure with a valid segment (for example, sourced from CS).
|-
| 10... || 4... || Further instruction pointers according to the IL's specification.
|}

=== IL information ===

{| class="wikitable"
|+ IL information structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || Far pointer to a zero-terminated string containing the IL class name; the segment is ignored.
|-
| 4 || 4 || Far pointer to a zero-terminated string containing the IL name; the segment is ignored.
|-
| 8 || 4 || Far pointer to a zero-terminated string containing the IL version; the segment is ignored.
|-
| 12 || 4 || Far pointer to a zero-terminated string containing the IL description; the segment is ignored.
|-
| 16 || 4 || Far pointer to an array of far pointers to zero-terminated strings containing the IL dependency list; the segment is ignored.
|}


== List of ILs ==

=== Built-in ILs ===

These ILs are included in FreyaOS.

* [[WonderWitch/IL/IlibIL|IlibIL]]
* [[WonderWitch/IL/ProcIL|ProcIL]]
* [[WonderWitch/IL/FsIL|FsIL]]
* [[WonderWitch/IL/RunnableIL|RunnableIL]]
* [[WonderWitch/IL/StreamIL|StreamIL]]

=== SDK-provided ILs ===

These ILs are not included in FreyaOS, but are provided on the WonderWitch disc.

* [[WonderWitch/IL/SoundIL|SoundIL]]
* [[WonderWitch/IL/ResumeIL|ResumeIL]]</text>
    <sha1>266938f7d7fafa07791f715be1f091f594b7b840</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/Process</title>
  <ns>0</ns>
  <id>61</id>
  <revision>
    <id>372</id>
    <timestamp>2024-10-18T18:02:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Memory layout ==  Process memory is stored in SRAM banks 3 (process 0 - typically used by FreyaOS), 2 (process 1) and 1 (process 2). The entire bank is available to the process.  === Process control block ===  The process control block contains information about the running process. It is stored in the first 96 bytes of data.  {| class="wikitable" |+ Process control block structure |- ! Offset !! Length !! Contents |- | 0 || 4 || Compiler ID, zero-terminated string; s..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2499" xml:space="preserve">== Memory layout ==

Process memory is stored in SRAM banks 3 (process 0 - typically used by FreyaOS), 2 (process 1) and 1 (process 2). The entire bank is available to the process.

=== Process control block ===

The process control block contains information about the running process. It is stored in the first 96 bytes of data.

{| class="wikitable"
|+ Process control block structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || Compiler ID, zero-terminated string; see below
|-
| 4 || 2 || TODO
|-
| 6 || 2 || TODO
|-
| 8 || 2 || TODO
|-
| 10 || 2 || TODO
|-
| 12 || 4 || Far pointer to [[WonderWitch/IL/IlibIL|IlibIL]] library
|-
| 16 || 4 || Far pointer to [[WonderWitch/IL/ProcIL|ProcIL]] library
|-
| 20 || 4 || TODO
|-
| 24 || 64 || Current working directory of the process
|-
| 88 || 2 || Near pointer to an array of near pointers to arguments (argv)
|-
| 90 || 4 || Far pointer to the process's resource data
|-
| 94 || 2 || Near pointer to the beginning of the process's free heap area.
|}

=== Compiler IDs ===

{| class="wikitable"
|+ Known compiler IDs
|-
! ID !! Compiler !! Source
|-
| &lt;code&gt;LCC&lt;/code&gt; || LSI C || WonderWitch SDK
|-
| &lt;code&gt;TCC&lt;/code&gt; || Turbo C/C++ || WonderWitch SDK
|-
| &lt;code&gt;DMC&lt;/code&gt; || Digital Mars C || WonderWitch SDK (newer versions)
|-
| &lt;code&gt;GCC&lt;/code&gt; || GCC || Wonderful Toolchain
|-
| &lt;code&gt;TCC&lt;/code&gt; || Visual C++ || WonBe
|}

== Launching procedure ==

Launching a process is split into two stages: loading and running.

=== Load ===

The load routine begins at offset 0 into the application. It performs the following activities:

- SRAM initialization: copying static data from ROM to SRAM and zeroing SRAM memory,
- copying the compiler ID to the PCB,
- heap initialization: setting the argv and heap pointers to the location of the first free byte in SRAM,
- returning in &lt;code&gt;AX&lt;/code&gt; a near pointer to the start function (see "Run").

=== Run ===

The start function is of the form &lt;code&gt;void main(int argc, char* argv);&lt;/code&gt;. It typically performs the following activities before jumping to C code:

- configuring the stack pointer,
- resetting the display (disabling screen/sprite layers, clearing window and sprite configuration, resetting scroll),
- initializing screen/sprite VRAM locations according to user needs (one/two screens, 256/512 free tiles),
- initializing the default display settings (configuring text mode, enabling screen layers).

After running C code, &lt;code&gt;INT $10&lt;/code&gt; is triggered to exit the process.</text>
    <sha1>1db410ec4719df82df8403c2e3479d57f923be9b</sha1>
  </revision>
  <revision>
    <id>373</id>
    <parentid>372</parentid>
    <timestamp>2024-10-18T18:11:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Compiler IDs */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2504" xml:space="preserve">== Memory layout ==

Process memory is stored in SRAM banks 3 (process 0 - typically used by FreyaOS), 2 (process 1) and 1 (process 2). The entire bank is available to the process.

=== Process control block ===

The process control block contains information about the running process. It is stored in the first 96 bytes of data.

{| class="wikitable"
|+ Process control block structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || Compiler ID, zero-terminated string; see below
|-
| 4 || 2 || TODO
|-
| 6 || 2 || TODO
|-
| 8 || 2 || TODO
|-
| 10 || 2 || TODO
|-
| 12 || 4 || Far pointer to [[WonderWitch/IL/IlibIL|IlibIL]] library
|-
| 16 || 4 || Far pointer to [[WonderWitch/IL/ProcIL|ProcIL]] library
|-
| 20 || 4 || TODO
|-
| 24 || 64 || Current working directory of the process
|-
| 88 || 2 || Near pointer to an array of near pointers to arguments (argv)
|-
| 90 || 4 || Far pointer to the process's resource data
|-
| 94 || 2 || Near pointer to the beginning of the process's free heap area.
|}

=== Compiler IDs ===

{| class="wikitable"
|+ Known compiler IDs
|-
! ID !! Compiler !! Source
|-
| &lt;code&gt;LCC&lt;/code&gt; || LSI C || WonderWitch SDK
|-
| &lt;code&gt;TCC&lt;/code&gt; || Turbo C/C++ || WonderWitch SDK
|-
| &lt;code&gt;DMC&lt;/code&gt; || Digital Mars C || WonderWitch SDK (newer versions)
|-
| &lt;code&gt;GCC&lt;/code&gt; || gcc-ia16 || Wonderful Toolchain
|-
| &lt;code&gt;TCC&lt;/code&gt; || Visual C++ || WonBe
|}

== Launching procedure ==

Launching a process is split into two stages: loading and running.

=== Load ===

The load routine begins at offset 0 into the application. It performs the following activities:

- SRAM initialization: copying static data from ROM to SRAM and zeroing SRAM memory,
- copying the compiler ID to the PCB,
- heap initialization: setting the argv and heap pointers to the location of the first free byte in SRAM,
- returning in &lt;code&gt;AX&lt;/code&gt; a near pointer to the start function (see "Run").

=== Run ===

The start function is of the form &lt;code&gt;void main(int argc, char* argv);&lt;/code&gt;. It typically performs the following activities before jumping to C code:

- configuring the stack pointer,
- resetting the display (disabling screen/sprite layers, clearing window and sprite configuration, resetting scroll),
- initializing screen/sprite VRAM locations according to user needs (one/two screens, 256/512 free tiles),
- initializing the default display settings (configuring text mode, enabling screen layers).

After running C code, &lt;code&gt;INT $10&lt;/code&gt; is triggered to exit the process.</text>
    <sha1>c41bfaee469d9bedef3b42e69850663824880dc5</sha1>
  </revision>
  <revision>
    <id>374</id>
    <parentid>373</parentid>
    <timestamp>2024-10-19T07:51:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Launching procedure */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2531" xml:space="preserve">== Memory layout ==

Process memory is stored in SRAM banks 3 (process 0 - typically used by FreyaOS), 2 (process 1) and 1 (process 2). The entire bank is available to the process.

=== Process control block ===

The process control block contains information about the running process. It is stored in the first 96 bytes of data.

{| class="wikitable"
|+ Process control block structure
|-
! Offset !! Length !! Contents
|-
| 0 || 4 || Compiler ID, zero-terminated string; see below
|-
| 4 || 2 || TODO
|-
| 6 || 2 || TODO
|-
| 8 || 2 || TODO
|-
| 10 || 2 || TODO
|-
| 12 || 4 || Far pointer to [[WonderWitch/IL/IlibIL|IlibIL]] library
|-
| 16 || 4 || Far pointer to [[WonderWitch/IL/ProcIL|ProcIL]] library
|-
| 20 || 4 || TODO
|-
| 24 || 64 || Current working directory of the process
|-
| 88 || 2 || Near pointer to an array of near pointers to arguments (argv)
|-
| 90 || 4 || Far pointer to the process's resource data
|-
| 94 || 2 || Near pointer to the beginning of the process's free heap area.
|}

=== Compiler IDs ===

{| class="wikitable"
|+ Known compiler IDs
|-
! ID !! Compiler !! Source
|-
| &lt;code&gt;LCC&lt;/code&gt; || LSI C || WonderWitch SDK
|-
| &lt;code&gt;TCC&lt;/code&gt; || Turbo C/C++ || WonderWitch SDK
|-
| &lt;code&gt;DMC&lt;/code&gt; || Digital Mars C || WonderWitch SDK (newer versions)
|-
| &lt;code&gt;GCC&lt;/code&gt; || gcc-ia16 || Wonderful Toolchain
|-
| &lt;code&gt;TCC&lt;/code&gt; || Visual C++ || WonBe
|}

== Launching procedure ==

Launching a process is split into two stages: loading and running.

=== Load ===

The load routine begins at offset 0 into the application. It performs the following activities:

* SRAM initialization: copying static data from ROM to SRAM and zeroing SRAM memory,
* copying the compiler ID to the PCB,
* heap initialization: setting the argv and heap pointers to the location of the first free byte in SRAM,
* returning in &lt;code&gt;AX&lt;/code&gt; a near pointer to the start function (see "Run").

=== Run ===

The start function is of the form &lt;code&gt;void main(int argc, char* argv);&lt;/code&gt;. It typically performs the following activities before jumping to C code:

* configuring the stack pointer (SP) and data segment (DS),
* resetting the display (disabling screen/sprite layers, clearing window and sprite configuration, resetting scroll),
* initializing screen/sprite VRAM locations according to user needs (one/two screens, 256/512 free tiles),
* initializing the default display settings (configuring text mode, enabling screen layers).

After running C code, &lt;code&gt;INT $10&lt;/code&gt; is triggered to exit the process.</text>
    <sha1>45fdf39b96f5fa5c357b14aa47565a014f941009</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/FreyaBIOS/Timer</title>
  <ns>0</ns>
  <id>62</id>
  <revision>
    <id>375</id>
    <timestamp>2024-10-19T11:19:10Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Timer interrupt provides an abstraction layer for the WonderSwan's [[Timers|timers]], as well as the on-cartridge [[Real-Time Clock|RTC]].  == Types ==  === RTC fields ===  The RTC field indexes match the order of fields returned by the RTC chip.  Note that FreyaBIOS transparently converts the values to and from BCD.  {| class="wikitable" |- ! Index !! Data !! Format |- | 0 || Year || 0 - 99; 0 is assumed to be the year 2000. |- | 1 || Month || 1 - 12 |- | 2 || Date..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1837" xml:space="preserve">The Timer interrupt provides an abstraction layer for the WonderSwan's [[Timers|timers]], as well as the on-cartridge [[Real-Time Clock|RTC]].

== Types ==

=== RTC fields ===

The RTC field indexes match the order of fields returned by the RTC chip.

Note that FreyaBIOS transparently converts the values to and from BCD.

{| class="wikitable"
|-
! Index !! Data !! Format
|-
| 0 || Year || 0 - 99; 0 is assumed to be the year 2000.
|-
| 1 || Month || 1 - 12
|-
| 2 || Date (day of month) || 1 - 31
|-
| 3 || Day of week || 0 - 6; 0 = Sunday, 1 = Monday, ..., 6 = Saturday
|-
| 4 || Hour || 0 - 23
|-
| 5 || Minute || 0 - 59
|-
| 6 || Second || 0 - 59
|}

=== RTC struct ===

The RTC struct is a seven-byte memory structure, containing all RTC fields consecutively, taking up one unsinged byte each.

== Interrupts ==

=== INT $16/AH=$00 - rtc_reset ===

* AH = $00

=== INT $16/AH=$01 - rtc_set_datetime ===

* AH = $01
* BX = Field
* CX = Value of field

=== INT $16/AH=$02 - rtc_get_datetime ===

* AH = $02
* BX = Field

Return:

* AX = Value of field

=== INT $16/AH=$03 - rtc_set_datetime_struct ===

* AH = $03
* DS:DX = Pointer to RTC struct

=== INT $16/AH=$04 - rtc_get_datetime_struct ===

* AH = $04
* DS:DX = Pointer to RTC struct

=== INT $16/AH=$05 - rtc_enable_alarm ===

* AH = $05
* BL = Hour
* BH = Minute

=== INT $16/AH=$06 - rtc_disable_alarm ===

* AH = $06

=== INT $16/AH=$07 - timer_enable ===

* AH = $07
* AL = Type (0 = HBlank, 1 = VBlank)
* BL = Reload mode (0 = one-shot, 1 = repeating)
* CX = Time, in lines or frames, to wait.

=== INT $16/AH=$08 - timer_disable ===

* AH = $08
* AL = Type (0 = HBlank, 1 = VBlank)

=== INT $16/AH=$09 - timer_get_count ===

* AH = $09
* AL = Type (0 = HBlank, 1 = VBlank)

Return:

* AX = The current counter value, from the time set in &lt;code&gt;timer_enable&lt;/code&gt; down.</text>
    <sha1>1a54d001519a9a65502b35f001b0fbaf8307dd6a</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/IL/ResumeIL</title>
  <ns>0</ns>
  <id>63</id>
  <revision>
    <id>376</id>
    <timestamp>2024-10-19T12:01:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== ResumeIL ==  ResumeIL is a library which augments the process suspend/resume functionality of the built-in [[WonderWitch/IL/ProcIL|ProcIL]] library to also archive the memory areas &lt;code&gt;0x4000 - 0xBFFF&lt;/code&gt; (WSC expanded/4bpp tile memory) and &lt;code&gt;0xFE00 - 0xFFFF&lt;/code&gt; (WSC palette memory). This is done by copying this memory to &lt;code&gt;/ram0/resume.dat&lt;/code&gt;.  === Limitations ===  - This approach only allows suspending and resuming one process."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="456" xml:space="preserve">== ResumeIL ==

ResumeIL is a library which augments the process suspend/resume functionality of the built-in [[WonderWitch/IL/ProcIL|ProcIL]] library to also archive the memory areas &lt;code&gt;0x4000 - 0xBFFF&lt;/code&gt; (WSC expanded/4bpp tile memory) and &lt;code&gt;0xFE00 - 0xFFFF&lt;/code&gt; (WSC palette memory). This is done by copying this memory to &lt;code&gt;/ram0/resume.dat&lt;/code&gt;.

=== Limitations ===

- This approach only allows suspending and resuming one process.</text>
    <sha1>e41e168a5fc691d566281069a1ef1613c5bfce01</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/FreyaOS</title>
  <ns>0</ns>
  <id>49</id>
  <revision>
    <id>377</id>
    <parentid>260</parentid>
    <timestamp>2024-10-19T12:05:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add FreyaOS 1.1.2 and 1.1.3 changelog information</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2230" xml:space="preserve">FreyaOS is an operating system and library set for [[WonderWitch]], present in the second-to-last 64 KB of any WonderWitch cartridge.

It provides the following library functionality:

* process management,
* file system access,
* [[WonderWitch/IL|IL]] library management.

It additionally provides an user interface, which allows launching programs and performing file management/transfer operations.

== Revisions ==

* FreyaOS 1.0.0
* FreyaOS 1.0.2 (September 2nd, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00001.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.0.3 (November 1st, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00004.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.1.0 (December 24th, 2000 &lt;ref name="history2001"&gt;[http://wonderwitch.qute.co.jp/history200107.htm WonderWitch これまでの歩み]&lt;/ref&gt;)
* FreyaOS 1.1.1 (February 7th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.2 (June 20th, 2001 &lt;ref&gt;http://wonderwitch.qute.co.jp/announce/archives/msg00298.html&lt;/ref&gt;)
** Improved file system stability.
* FreyaOS 1.1.3 (June 26th, 2001 &lt;ref&gt;http://wonderwitch.qute.co.jp/announce/archives/msg00300.html&lt;/ref&gt;)
** Fixed a regression in programs which used resource files.
** Fixed the ''lseek()'' function in the file system library.
* FreyaOS 1.1.4 (September 27th, 2001 &lt;ref name="history2002"&gt;[http://wonderwitch.qute.co.jp/history200207.htm WonderWitch これまでの歩み 2002]&lt;/ref&gt;)
* FreyaOS 1.1.5 (March 5th, 2002 &lt;ref name="history2002"/&gt;)
* FreyaOS 1.1.6 beta1 (April 30th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00321.html FreyaOS βバージョン提供のお知らせ]&lt;/ref&gt;)
** Fixed IRAM corruption when calling ''open()''/''stat()'' after initializing SoundIL.
* FreyaOS 1.2.0 (July 13th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/index_wwp.html WonderWitchプレーヤー サポートページ]&lt;/ref&gt;)
** Validated for SwanCrystal consoles.
* FreyaOS 1.2.0S
** Special, stripped-down version of FreyaOS 1.2.0 used on pre-programmed Judgement Silversword and Dicing Knight cartridges.

== Documentation ==

* [[WonderWitch .fx files|.fx file format]]

== Notes ==

&lt;references /&gt;</text>
    <sha1>6b5814d38420b4343f07e1202569d841c8d532ab</sha1>
  </revision>
  <revision>
    <id>378</id>
    <parentid>377</parentid>
    <timestamp>2024-10-19T12:05:44Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Revisions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2338" xml:space="preserve">FreyaOS is an operating system and library set for [[WonderWitch]], present in the second-to-last 64 KB of any WonderWitch cartridge.

It provides the following library functionality:

* process management,
* file system access,
* [[WonderWitch/IL|IL]] library management.

It additionally provides an user interface, which allows launching programs and performing file management/transfer operations.

== Revisions ==

* FreyaOS 1.0.0
* FreyaOS 1.0.2 (September 2nd, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00001.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.0.3 (November 1st, 2000 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00004.html FreyaOS バージョンアップのお知らせ]&lt;/ref&gt;)
* FreyaOS 1.1.0 (December 24th, 2000 &lt;ref name="history2001"&gt;[http://wonderwitch.qute.co.jp/history200107.htm WonderWitch これまでの歩み]&lt;/ref&gt;)
* FreyaOS 1.1.1 (February 7th, 2001 &lt;ref name="history2001"/&gt;)
* FreyaOS 1.1.2 (June 20th, 2001 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00298.html 最新ソフトウェアリリースのお知らせ]&lt;/ref&gt;)
** Improved file system stability.
* FreyaOS 1.1.3 (June 26th, 2001 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00300.html 最新ソフトウェアリリースのお知らせ]&lt;/ref&gt;)
** Fixed a regression in programs which used resource files.
** Fixed the ''lseek()'' function in the file system library.
* FreyaOS 1.1.4 (September 27th, 2001 &lt;ref name="history2002"&gt;[http://wonderwitch.qute.co.jp/history200207.htm WonderWitch これまでの歩み 2002]&lt;/ref&gt;)
* FreyaOS 1.1.5 (March 5th, 2002 &lt;ref name="history2002"/&gt;)
* FreyaOS 1.1.6 beta1 (April 30th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/announce/archives/msg00321.html FreyaOS βバージョン提供のお知らせ]&lt;/ref&gt;)
** Fixed IRAM corruption when calling ''open()''/''stat()'' after initializing SoundIL.
* FreyaOS 1.2.0 (July 13th, 2002 &lt;ref&gt;[http://wonderwitch.qute.co.jp/index_wwp.html WonderWitchプレーヤー サポートページ]&lt;/ref&gt;)
** Validated for SwanCrystal consoles.
* FreyaOS 1.2.0S
** Special, stripped-down version of FreyaOS 1.2.0 used on pre-programmed Judgement Silversword and Dicing Knight cartridges.

== Documentation ==

* [[WonderWitch .fx files|.fx file format]]

== Notes ==

&lt;references /&gt;</text>
    <sha1>1ff1fa541ff80d9f75ea7f13a1ac26a563a012ee</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/IL/IlibIL</title>
  <ns>0</ns>
  <id>64</id>
  <revision>
    <id>379</id>
    <timestamp>2024-10-19T12:51:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "IlibIL is a library used to load other indirect libraries present on the system.  == Functions ==  === open ===  &lt;code&gt;int open(const char far *name, IL far *buffer);&lt;/code&gt;  Load the specified IL &lt;code&gt;name&lt;/code&gt; from &lt;code&gt;/rom0&lt;/code&gt; or &lt;code&gt;/kern&lt;/code&gt;. The IL header is copied to the provided &lt;code&gt;buffer&lt;/code&gt; with addresses appropriately relocated to match the IL's location in ROM.  === open_system ===  &lt;code&gt;int open_system(const char far *name, IL far *buffe..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="591" xml:space="preserve">IlibIL is a library used to load other indirect libraries present on the system.

== Functions ==

=== open ===

&lt;code&gt;int open(const char far *name, IL far *buffer);&lt;/code&gt;

Load the specified IL &lt;code&gt;name&lt;/code&gt; from &lt;code&gt;/rom0&lt;/code&gt; or &lt;code&gt;/kern&lt;/code&gt;. The IL header is copied to the provided &lt;code&gt;buffer&lt;/code&gt; with addresses appropriately relocated to match the IL's location in ROM.

=== open_system ===

&lt;code&gt;int open_system(const char far *name, IL far *buffer);&lt;/code&gt;

Works like &lt;code&gt;open&lt;/code&gt;, except only &lt;code&gt;/kern&lt;/code&gt; is queried for the presence of the library.</text>
    <sha1>861bb838fcd4dc14863a0e74f723b35f79da2fc7</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/Memory map</title>
  <ns>0</ns>
  <id>65</id>
  <revision>
    <id>382</id>
    <timestamp>2024-10-19T19:13:28Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Memory map ==  {| class="wikitable" |+ WonderWitch memory map ! Address ! ASCII, 1 screen ! ASCII, 2 screens ! Shift-JIS, 1 screen ! Shift-JIS, 2 screens |- | style="text-align: center;" | 0x0000 | colspan="4" style="text-align: center;" | Interrupt vectors |- | style="text-align: center;" | 0x0100 | colspan="4" style="text-align: center;" | ? |- | style="text-align: center;" | 0x0E00 | rowspan="7" style="text-align: center;" | | rowspan="5" style="text-align: center;..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1999" xml:space="preserve">== Memory map ==

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | ?
|-
| style="text-align: center;" | 0x0E00
| rowspan="7" style="text-align: center;" |
| rowspan="5" style="text-align: center;" |
| rowspan="2" style="text-align: center;" |
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.</text>
    <sha1>8471ae4596bd9d84af48164ade565d829fcfc827</sha1>
  </revision>
  <revision>
    <id>383</id>
    <parentid>382</parentid>
    <timestamp>2024-10-19T19:13:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1982" xml:space="preserve">
{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | ?
|-
| style="text-align: center;" | 0x0E00
| rowspan="7" style="text-align: center;" |
| rowspan="5" style="text-align: center;" |
| rowspan="2" style="text-align: center;" |
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.</text>
    <sha1>0fafea4cf92f1fc0afacf809039c328fb956baeb</sha1>
  </revision>
  <revision>
    <id>384</id>
    <parentid>383</parentid>
    <timestamp>2024-10-19T19:20:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2210" xml:space="preserve">The following documents the official WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | ?
|-
| style="text-align: center;" | 0x0E00
| rowspan="7" style="text-align: center;" |
| rowspan="5" style="text-align: center;" |
| rowspan="2" style="text-align: center;" |
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.</text>
    <sha1>32fb33df1ab7176cc4e4d019b83d2e2c13b1a9f9</sha1>
  </revision>
  <revision>
    <id>386</id>
    <parentid>384</parentid>
    <timestamp>2024-10-19T20:46:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3182" xml:space="preserve">The following documents the official WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | ?
|-
| style="text-align: center;" | 0x0E00
| rowspan="7" style="text-align: center;" |
| rowspan="5" style="text-align: center;" |
| rowspan="2" style="text-align: center;" |
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.

==== Interrupt vectors ====

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

{| class="wikitable"
! Bank
! Description
|-
| 0
| [[WonderWitch/Filesystem|/ram0 file data]]
|-
| 1
| Third process data
|-
| 2
| Second process data
|-
| 3
| First process data; typically used by [[WonderWitch/FreyaOS|FreyaOS]]
|}

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/Filesystem|/rom0 file data]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}</text>
    <sha1>98cf901fca2451abe57fded75f0cbaea9ee4ae81</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch</title>
  <ns>0</ns>
  <id>41</id>
  <revision>
    <id>385</id>
    <parentid>318</parentid>
    <timestamp>2024-10-19T20:43:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Memory map */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1253" xml:space="preserve">The WonderWitch is an official homebrew development kit released by Qute Corporation on July 18th, 2000.

== Hardware ==

The WonderWitch cartridge is based on the [[Bandai 2003]] mapper. It provides an RTC, as well as NOR self-flashing functionality using the Fujitsu MBM29DL400TC chip.

There were three means of acquiring WonderWitch cartridges:

* '''WonderWitch''', a software development kit containing a reflashable cartridge, a WonderSwan&lt;-&gt;RS-232 adapter, a development manual and a development tool CD;
* '''WonderWitch Player''', a priced-down user-only version omitting the development manual and tooling;
* The VAR program, allowing independent creators to buy reflashable cartridges in bulk, in units of 20 or 100.

== Software ==

The WonderWitch provides an abstraction layer and helper libraries, split into two modules:

* [[WonderWitch/FreyaBIOS|FreyaBIOS]] - providing a hardware abstraction layer and some utility functions,
* [[WonderWitch/FreyaOS|FreyaOS]] - providing helper libraries and higher-level concepts, such as processes and files.

== Development tools ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Fujitsu MBM29DL400TC datasheet]</text>
    <sha1>894f1dc0e2516dd182d318fdefff73e1d84b282f</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/FreyaBIOS</title>
  <ns>0</ns>
  <id>42</id>
  <revision>
    <id>387</id>
    <parentid>327</parentid>
    <timestamp>2024-10-19T20:46:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Revisions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1435" xml:space="preserve">FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.

It provides the following functionality:

* bring-up code,
* interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware,
* 8x8 ASCII and kanji fonts,
* a monitor program, allowing FreyaOS recovery and updates via XMODEM.

Other functionality (like file system access) is instead included as part of [[WonderWitch/FreyaOS|FreyaOS]]' system libraries; some other functionality (like [[WonderWitch/libwwc|WonderSwan Color support]]) is implemented as part of the development tooling.

== Revisions ==

- FreyaBIOS 1.0.0

== Fonts ==

As part of its ROM image, FreyaBIOS provides two fonts:

* an 8x8 ASCII font,
* an 8x8 Shift-JIS kanji font - [http://hp.vector.co.jp/authors/VA002310/original.html ELISA FONT].

== Interrupts ==

* [[WonderWitch/FreyaBIOS/Exit|Exit]] (INT $10)
* [[WonderWitch/FreyaBIOS/Key|Key]] (INT $11)
* [[WonderWitch/FreyaBIOS/Display|Display]] (INT $12)
* [[WonderWitch/FreyaBIOS/Text|Text]] (INT $13)
* [[WonderWitch/FreyaBIOS/Communication|Communication]] (INT $14)
* [[WonderWitch/FreyaBIOS/Sound|Sound]] (INT $15)
* [[WonderWitch/FreyaBIOS/Timer|Timer]] (INT $16)
* [[WonderWitch/FreyaBIOS/System|System]] (INT $17)
* [[WonderWitch/FreyaBIOS/Bank|Bank]] (INT $18)

== Freya Monitor ==

TODO</text>
    <sha1>caf9df887b876b8c9395fad863fa44868a270826</sha1>
  </revision>
  <revision>
    <id>388</id>
    <parentid>387</parentid>
    <timestamp>2024-10-19T20:46:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Revisions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1435" xml:space="preserve">FreyaBIOS is a boot program and hardware abstraction layer for [[WonderWitch]], present in the top-most (last) 64 KB of any WonderWitch cartridge.

It provides the following functionality:

* bring-up code,
* interrupt-based hardware abstraction layer, providing a more user-friendly (and less direct) interface to the WonderSwan hardware,
* 8x8 ASCII and kanji fonts,
* a monitor program, allowing FreyaOS recovery and updates via XMODEM.

Other functionality (like file system access) is instead included as part of [[WonderWitch/FreyaOS|FreyaOS]]' system libraries; some other functionality (like [[WonderWitch/libwwc|WonderSwan Color support]]) is implemented as part of the development tooling.

== Revisions ==

* FreyaBIOS 1.0.0

== Fonts ==

As part of its ROM image, FreyaBIOS provides two fonts:

* an 8x8 ASCII font,
* an 8x8 Shift-JIS kanji font - [http://hp.vector.co.jp/authors/VA002310/original.html ELISA FONT].

== Interrupts ==

* [[WonderWitch/FreyaBIOS/Exit|Exit]] (INT $10)
* [[WonderWitch/FreyaBIOS/Key|Key]] (INT $11)
* [[WonderWitch/FreyaBIOS/Display|Display]] (INT $12)
* [[WonderWitch/FreyaBIOS/Text|Text]] (INT $13)
* [[WonderWitch/FreyaBIOS/Communication|Communication]] (INT $14)
* [[WonderWitch/FreyaBIOS/Sound|Sound]] (INT $15)
* [[WonderWitch/FreyaBIOS/Timer|Timer]] (INT $16)
* [[WonderWitch/FreyaBIOS/System|System]] (INT $17)
* [[WonderWitch/FreyaBIOS/Bank|Bank]] (INT $18)

== Freya Monitor ==

TODO</text>
    <sha1>1c138b256e4b0221a7ef4b209b78cb4fdedc2cef</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/FreyaBIOS/Bank</title>
  <ns>0</ns>
  <id>55</id>
  <revision>
    <id>390</id>
    <parentid>329</parentid>
    <timestamp>2024-10-20T10:29:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1789" xml:space="preserve">The Bank interrupt provides an abstraction layer for accessing the WonderWitch cartridge's flash and RAM.

== Interrupts ==

=== INT $18/AH=$00 - bank_set_map ===

* AH = $00
* BL = Bank region
* CX = Number of bank to map to region

Bank regions:

* 0 = SRAM (1000:xxxx)
* 1 = ROM0 (2000:xxxx)
* 2 = ROM1 (3000:xxxx)

=== INT $18/AH=$01 - bank_get_map ===

* AH = $01
* BL = Bank region

Return:

* AX = Number of bank mapped to region

=== INT $18/AH=$02 - bank_read_byte ===

* AH = $02
* BX = Bank ID
* DX = Offset within bank

Return:

* AL = Byte read

Bank ID format:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 tiii iiii  iiii iiii
 |||| ||||  |||| ||||
 |+++-++++--++++-++++- Number of bank
 +-------------------- 0 = SRAM, 1 = Flash
&lt;/pre&gt;

=== INT $18/AH=$03 - bank_write_byte ===

* AH = $03
* BX = Bank ID
* CL = Byte to write
* DX = Offset within bank

=== INT $18/AH=$04 - bank_read_word ===

* AH = $04
* BX = Bank ID
* DX = Offset within bank

Return:

* AX = Word read

=== INT $18/AH=$05 - bank_write_word ===

* AH = $05
* BX = Bank ID
* CX = Word to write
* DX = Offset within bank

=== INT $18/AH=$06 - bank_read_block ===

* AH = $06
* BX = Bank ID
* CX = Number of bytes to read
* DX = Offset within bank
* DS:SI = Output buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$07 - bank_write_block ===

* AH = $07
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank
* DS:SI = Input buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$08 - bank_fill_block ===

* AH = $08
* AL = Fill value
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank

Sets &lt;code&gt;CX&lt;/code&gt; bytes in bank &lt;code&gt;BX&lt;/code&gt; to value &lt;code&gt;AL&lt;/code&gt; starting at offset &lt;code&gt;DX&lt;/code&gt;.

=== INT $18/AH=$09 - bank_erase_flash ===

* AH = $09
* BX = Bank ID</text>
    <sha1>cb27db74fdd6fa22113fa81a4aefcdf43cffe6cc</sha1>
  </revision>
  <revision>
    <id>391</id>
    <parentid>390</parentid>
    <timestamp>2024-10-20T10:39:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $18/AH=$09 - bank_erase_flash */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1837" xml:space="preserve">The Bank interrupt provides an abstraction layer for accessing the WonderWitch cartridge's flash and RAM.

== Interrupts ==

=== INT $18/AH=$00 - bank_set_map ===

* AH = $00
* BL = Bank region
* CX = Number of bank to map to region

Bank regions:

* 0 = SRAM (1000:xxxx)
* 1 = ROM0 (2000:xxxx)
* 2 = ROM1 (3000:xxxx)

=== INT $18/AH=$01 - bank_get_map ===

* AH = $01
* BL = Bank region

Return:

* AX = Number of bank mapped to region

=== INT $18/AH=$02 - bank_read_byte ===

* AH = $02
* BX = Bank ID
* DX = Offset within bank

Return:

* AL = Byte read

Bank ID format:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 tiii iiii  iiii iiii
 |||| ||||  |||| ||||
 |+++-++++--++++-++++- Number of bank
 +-------------------- 0 = SRAM, 1 = Flash
&lt;/pre&gt;

=== INT $18/AH=$03 - bank_write_byte ===

* AH = $03
* BX = Bank ID
* CL = Byte to write
* DX = Offset within bank

=== INT $18/AH=$04 - bank_read_word ===

* AH = $04
* BX = Bank ID
* DX = Offset within bank

Return:

* AX = Word read

=== INT $18/AH=$05 - bank_write_word ===

* AH = $05
* BX = Bank ID
* CX = Word to write
* DX = Offset within bank

=== INT $18/AH=$06 - bank_read_block ===

* AH = $06
* BX = Bank ID
* CX = Number of bytes to read
* DX = Offset within bank
* DS:SI = Output buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$07 - bank_write_block ===

* AH = $07
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank
* DS:SI = Input buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$08 - bank_fill_block ===

* AH = $08
* AL = Fill value
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank

Sets &lt;code&gt;CX&lt;/code&gt; bytes in bank &lt;code&gt;BX&lt;/code&gt; to value &lt;code&gt;AL&lt;/code&gt; starting at offset &lt;code&gt;DX&lt;/code&gt;.

=== INT $18/AH=$09 - bank_erase_flash ===

* AH = $09
* BX = Bank ID

Return:

* AX = zero on success (undocumented)</text>
    <sha1>78e79cae9ca99df150ec4b413138bdf851896253</sha1>
  </revision>
  <revision>
    <id>392</id>
    <parentid>391</parentid>
    <timestamp>2024-10-20T13:13:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $18/AH=$07 - bank_write_block */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1885" xml:space="preserve">The Bank interrupt provides an abstraction layer for accessing the WonderWitch cartridge's flash and RAM.

== Interrupts ==

=== INT $18/AH=$00 - bank_set_map ===

* AH = $00
* BL = Bank region
* CX = Number of bank to map to region

Bank regions:

* 0 = SRAM (1000:xxxx)
* 1 = ROM0 (2000:xxxx)
* 2 = ROM1 (3000:xxxx)

=== INT $18/AH=$01 - bank_get_map ===

* AH = $01
* BL = Bank region

Return:

* AX = Number of bank mapped to region

=== INT $18/AH=$02 - bank_read_byte ===

* AH = $02
* BX = Bank ID
* DX = Offset within bank

Return:

* AL = Byte read

Bank ID format:

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 tiii iiii  iiii iiii
 |||| ||||  |||| ||||
 |+++-++++--++++-++++- Number of bank
 +-------------------- 0 = SRAM, 1 = Flash
&lt;/pre&gt;

=== INT $18/AH=$03 - bank_write_byte ===

* AH = $03
* BX = Bank ID
* CL = Byte to write
* DX = Offset within bank

=== INT $18/AH=$04 - bank_read_word ===

* AH = $04
* BX = Bank ID
* DX = Offset within bank

Return:

* AX = Word read

=== INT $18/AH=$05 - bank_write_word ===

* AH = $05
* BX = Bank ID
* CX = Word to write
* DX = Offset within bank

=== INT $18/AH=$06 - bank_read_block ===

* AH = $06
* BX = Bank ID
* CX = Number of bytes to read
* DX = Offset within bank
* DS:SI = Output buffer, of size &lt;code&gt;CX&lt;/code&gt;

=== INT $18/AH=$07 - bank_write_block ===

* AH = $07
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank
* DS:SI = Input buffer, of size &lt;code&gt;CX&lt;/code&gt;

Return:

* AX = zero on success (undocumented)

=== INT $18/AH=$08 - bank_fill_block ===

* AH = $08
* AL = Fill value
* BX = Bank ID
* CX = Number of bytes to write
* DX = Offset within bank

Sets &lt;code&gt;CX&lt;/code&gt; bytes in bank &lt;code&gt;BX&lt;/code&gt; to value &lt;code&gt;AL&lt;/code&gt; starting at offset &lt;code&gt;DX&lt;/code&gt;.

=== INT $18/AH=$09 - bank_erase_flash ===

* AH = $09
* BX = Bank ID

Return:

* AX = zero on success (undocumented)</text>
    <sha1>b28fbd81f885a66fa1b67bb7549991d0a9476c65</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/FreyaBIOS/System</title>
  <ns>0</ns>
  <id>66</id>
  <revision>
    <id>393</id>
    <timestamp>2024-10-20T16:39:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The System interrupt provides assorted system-related functionality.  == Types ==  === Suspend/resume structure ===  This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (core 1) and &lt;code&gt;$BF00&lt;/code&gt; (core 0).  {| class="wikitable" |- ! Offset !! Size !! Contents |- | $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt; |- | $4000 || 2 || Stack segment? |- | $4002 || 2 || Data segment? |- | $4004 || 224 || Copy of IO ports &lt;code&gt;$00..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="549" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Types ==

=== Suspend/resume structure ===

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (core 1) and &lt;code&gt;$BF00&lt;/code&gt; (core 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 2 || Stack segment?
|-
| $4002 || 2 || Data segment?
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 6 || ?
|}

== Interrupts ==

TODO</text>
    <sha1>adfb4ba8b26151611ec8c5d94a2a4e1d272256c0</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>Mapper</title>
  <ns>0</ns>
  <id>17</id>
  <revision>
    <id>395</id>
    <parentid>53</parentid>
    <timestamp>2024-11-24T17:40:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>clarify terminology</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1306" xml:space="preserve">There are three documented memory-mapping chips used on the WonderSwan and Pocket Challenge V2:

* [[Bandai 2001]]
* [[Bandai 2003]]
* [[KARNAK]] (Pocket Challenge V2 cartridges only)

All three provide this same common subset for memory banking:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | Extended bankswitching
! $C0
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00BB bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Note that only the top 768KiB of said bank can be read this way.
|-
! $C1
| RAM Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb&lt;/tt&gt;
| RW8
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
|-
! $C2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb&lt;/tt&gt;
| RW8
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
|-
! $C3
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb&lt;/tt&gt;
| RW8
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
|}

Note that the number of bits in the Linear bank register depends on the mapper.

The "mono" WonderSwan expects that the register at $C3 will power up holding $FF.</text>
    <sha1>a2bf6ca1b9045148a0d0e8c802721f238fb338d5</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>Bandai 2003</title>
  <ns>0</ns>
  <id>13</id>
  <revision>
    <id>396</id>
    <parentid>253</parentid>
    <timestamp>2024-11-24T17:44:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>clarify terminology</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4561" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Data needed (D)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Real-Time Clock interface ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

(Put logic analyzer traces here)

Values are as follows:

=== $00-$0F, $1C-$1F ===
Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

=== $10, $11 ===
Send command byte ($60 or $61 respectively) and stop.

=== $12 ===
Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

=== $13 ===
Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

=== $14 ===
Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the ''first'' byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

=== $15 ===
Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

=== $16 ===
Send command byte ($66), then send three bytes of payload, then stop.

=== $17 ===
Send command byte ($67), then receive three bytes of payload, then stop.

=== $18, $1A ===
Send command byte ($68 or $6A), then send two bytes of payload, then stop.

=== $19, $1B ===
Send command byte ($69 or $6B), then receive two bytes of payload, then stop.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>eca9cb380cda5f76b432d14b1dc15aaabd83ed26</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>WonderWitch/Flash</title>
  <ns>0</ns>
  <id>67</id>
  <revision>
    <id>397</id>
    <timestamp>2024-11-24T17:46:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderWitch cartridge features a 512KiB flash chip - the MBM29DL400TC. While the WonderSwan SoC pervents writes to the ROM area, it can be written to via the SRAM area using port $CE on the [[Bandai 2003]] mapper.  TODO: Document commands.  == Links ==  * [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Datasheet]"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="380" xml:space="preserve">The WonderWitch cartridge features a 512KiB flash chip - the MBM29DL400TC. While the WonderSwan SoC pervents writes to the ROM area, it can be written to via the SRAM area using port $CE on the [[Bandai 2003]] mapper.

TODO: Document commands.

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Datasheet]</text>
    <sha1>a66d3c4628432fb01557e88cf51b45c74615c067</sha1>
  </revision>
</page>
<page arvcontinue="20240822131001|351">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>400</id>
    <parentid>274</parentid>
    <timestamp>2024-12-01T20:32:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Developer/Publisher ID ($6) */ add Hearty Robin</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5087" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || ?
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>b65ace0ec0f51bbe73f05dcf4779c52a5c323541</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>401</id>
    <parentid>394</parentid>
    <timestamp>2024-12-07T21:48:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Control ($14) */ briefly document high contrast</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18757" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1
  |+------ Aux 2
  +------- Aux 3
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}
=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>b6c5f29eabb6583fe9dc484800741607efe5de9c</sha1>
  </revision>
  <revision>
    <id>431</id>
    <parentid>401</parentid>
    <timestamp>2024-12-17T20:40:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Icon Control ($15) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18804" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features six LCD segment icons which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are, as follows:

* Aux 3 - large circle,
* Aux 2 - medium circle,
* Aux 1 - small circle,
* Horizontal orientation,
* Vertical orientation,
* Sleep.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1 (Small circle)
  |+------ Aux 2 (Medium circle)
  +------- Aux 3 (Large circle)
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
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  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>WonderWitch/FreyaBIOS/System</title>
  <ns>0</ns>
  <id>66</id>
  <revision>
    <id>402</id>
    <parentid>393</parentid>
    <timestamp>2024-12-08T09:44:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupts */ start</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2055" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Types ==

=== Suspend/resume structure ===

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (core 1) and &lt;code&gt;$BF00&lt;/code&gt; (core 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 2 || Stack segment?
|-
| $4002 || 2 || Data segment?
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 6 || ?
|}

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

=== INT $17/AH=$0C - sys_resume ===

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

=== INT $17/AH=$15 - sys_get_resume ===</text>
    <sha1>40c816ee73f278dfc209b0c472db017e1fe60820</sha1>
  </revision>
  <revision>
    <id>419</id>
    <parentid>402</parentid>
    <timestamp>2024-12-15T07:51:44Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>provide initial inormation on sys_suspend/resume</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2175" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = ?

Return:

* AX = ?

TODO

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 2 || Stack segment?
|-
| $4002 || 2 || Data segment?
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 6 || ?
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0B
* AL = Suspend slot (see below)

TODO

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

=== INT $17/AH=$15 - sys_get_resume ===</text>
    <sha1>847f602f0f4b231c1270bedc2fe8dd7128788d11</sha1>
  </revision>
  <revision>
    <id>420</id>
    <parentid>419</parentid>
    <timestamp>2024-12-15T08:02:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $17/AH=$0B - sys_suspend */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2415" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = ?

Return:

* AX = ?

TODO

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0B
* AL = Suspend slot (see below)

TODO

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

=== INT $17/AH=$15 - sys_get_resume ===</text>
    <sha1>a5bfbf8baedefe873503934d9561660ee6329553</sha1>
  </revision>
  <revision>
    <id>421</id>
    <parentid>420</parentid>
    <timestamp>2024-12-15T09:08:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2602" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = ?

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

TODO

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

=== INT $17/AH=$15 - sys_get_resume ===</text>
    <sha1>42a9d95bb375cfafa4bf2d74d3a12510dca1120f</sha1>
  </revision>
  <revision>
    <id>422</id>
    <parentid>421</parentid>
    <timestamp>2024-12-15T09:09:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $17/AH=$0B - sys_suspend */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2701" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = ?

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

=== INT $17/AH=$15 - sys_get_resume ===</text>
    <sha1>200aeec551f031aae5007f2a55bb83a423be265d</sha1>
  </revision>
  <revision>
    <id>423</id>
    <parentid>422</parentid>
    <timestamp>2024-12-15T09:09:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $17/AH=$0B - sys_suspend */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2739" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

=== INT $17/AH=$15 - sys_get_resume ===</text>
    <sha1>6adea9b76a79b7fb18cb1cf639a17e25200780bf</sha1>
  </revision>
  <revision>
    <id>424</id>
    <parentid>423</parentid>
    <timestamp>2024-12-15T11:30:32Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>initially document sys_set/get_resume</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3163" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $14

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>657fb2a86b30f8c4871020b20585db16ae54285e</sha1>
  </revision>
  <revision>
    <id>425</id>
    <parentid>424</parentid>
    <timestamp>2024-12-15T11:31:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document sys_get_version</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3378" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

 15      bit       0
 ---- ---- ---- ----
 MMMM mmmm pppp pppp
 |||| |||| |||| ||||
 |||| |||| ++++-++++- Patch version (0-127)
 |||| ++++----------- Minor version (0-15)
 ++++---------------- Major version (0-15)

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $15

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>8a896858286b52f4abd8e7e89809399f19fab041</sha1>
  </revision>
  <revision>
    <id>429</id>
    <parentid>425</parentid>
    <timestamp>2024-12-17T15:56:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3501" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

Hook the given interrupt handler and enable the interrupt.

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

Unhook the given interrupt handler and disable the interrupt.

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

 15      bit       0
 ---- ---- ---- ----
 MMMM mmmm pppp pppp
 |||| |||| |||| ||||
 |||| |||| ++++-++++- Patch version (0-127)
 |||| ++++----------- Minor version (0-15)
 ++++---------------- Major version (0-15)

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $15

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>8c3098857aad69154deb09c10676f34ee02725f1</sha1>
  </revision>
  <revision>
    <id>430</id>
    <parentid>429</parentid>
    <timestamp>2024-12-17T16:34:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $17/AH=$0F - sys_alloc_iram */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3653" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

Hook the given interrupt handler and enable the interrupt.

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

Unhook the given interrupt handler and disable the interrupt.

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

=== INT $17/AH=$05 - sys_set_sleep_time ===

=== INT $17/AH=$06 - sys_get_sleep_time ===

=== INT $17/AH=$07 - sys_set_awake_key ===

=== INT $17/AH=$08 - sys_get_awake_key ===

=== INT $17/AH=$09 - sys_set_keepalive_int ===

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

* BX = ?
* CX = bytes to allocate

Return:

* AX = near pointer to allocated IRAM block

Pointers to IRAM blocks are always segment (16 byte)-aligned.

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

 15      bit       0
 ---- ---- ---- ----
 MMMM mmmm pppp pppp
 |||| |||| |||| ||||
 |||| |||| ++++-++++- Patch version (0-127)
 |||| ++++----------- Minor version (0-15)
 ++++---------------- Major version (0-15)

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $15

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>685426b41308bef66a06e5bbeab129cd1c787655</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>WonderWitch/Flash</title>
  <ns>0</ns>
  <id>67</id>
  <revision>
    <id>403</id>
    <parentid>397</parentid>
    <timestamp>2024-12-08T09:57:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document sector layout</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1059" xml:space="preserve">The WonderWitch cartridge features a 512KiB flash chip - the MBM29DL400TC. While the WonderSwan SoC pervents writes to the ROM area, it can be written to via the SRAM area using port $CE on the [[Bandai 2003]] mapper.

== Sector layout ==

{| class="wikitable"
! Bank
! Start
! End
! Size
|-
| rowspan="6" | 2
| $00000
| $0FFFF
| 64 KB
|-
| $10000
| $1FFFF
| 64 KB
|-
| $20000
| $2FFFF
| 64 KB
|-
| $30000
| $3FFFF
| 64 KB
|-
| $40000
| $4FFFF
| 64 KB
|-
| $50000
| $5FFFF
| 64 KB
|-
| rowspan="8" | 1
| $60000
| $63FFF
| 16 KB
|-
| $64000
| $6BFFF
| 32 KB
|-
| $6C000
| $6DFFF
| 8 KB
|-
| $6E000
| $6FFFF
| 8 KB
|-
| $70000
| $71FFF
| 8 KB
|-
| $72000
| $73FFF
| 8 KB
|-
| $74000
| $7BFFF
| 32 KB
|-
| $7C000
| $7FFFF
| 16 KB
|}

Note that MBM29DL400TC allows operating simultaneously in two banks: the first 384 KB can be programmed or erased while the last 128 KB remains readable, and vice versa.

== Commands ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Datasheet]</text>
    <sha1>8136c75714649a7fef0cdfc9b261e3e3ff9561ec</sha1>
  </revision>
  <revision>
    <id>404</id>
    <parentid>403</parentid>
    <timestamp>2024-12-08T09:57:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Sector layout */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1063" xml:space="preserve">The WonderWitch cartridge features a 512KiB flash chip - the MBM29DL400TC. While the WonderSwan SoC pervents writes to the ROM area, it can be written to via the SRAM area using port $CE on the [[Bandai 2003]] mapper.

== Sector layout ==

{| class="wikitable"
! Bank
! Start
! End
! Size
|-
| rowspan="6" | 2
| $00000
| $0FFFF
| 64 KB
|-
| $10000
| $1FFFF
| 64 KB
|-
| $20000
| $2FFFF
| 64 KB
|-
| $30000
| $3FFFF
| 64 KB
|-
| $40000
| $4FFFF
| 64 KB
|-
| $50000
| $5FFFF
| 64 KB
|-
| rowspan="8" | 1
| $60000
| $63FFF
| 16 KB
|-
| $64000
| $6BFFF
| 32 KB
|-
| $6C000
| $6DFFF
| 8 KB
|-
| $6E000
| $6FFFF
| 8 KB
|-
| $70000
| $71FFF
| 8 KB
|-
| $72000
| $73FFF
| 8 KB
|-
| $74000
| $7BFFF
| 32 KB
|-
| $7C000
| $7FFFF
| 16 KB
|}

Note that the MBM29DL400TC allows operating simultaneously in two banks: the first 384 KB can be programmed or erased while the last 128 KB remains readable, and vice versa.

== Commands ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Datasheet]</text>
    <sha1>ff65adbefb78d4f7f23b80e46dc35321654497f1</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>405</id>
    <parentid>400</parentid>
    <timestamp>2024-12-08T10:01:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Developer/Publisher ID ($6) */ add Soeishinsha</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5097" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ?
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>65c20f7bac877bcb9eaa7425d1b56e88e26f34a7</sha1>
  </revision>
  <revision>
    <id>406</id>
    <parentid>405</parentid>
    <timestamp>2024-12-08T13:18:28Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Developer/Publisher ID ($6) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5115" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = Horizontal, 1 = Vertical.
      ||   Controls the splash screen's orientation.
      |+-- ROM bus width: 0 = 16-bit, 1 = 8-bit.
      +--- ROM access time: 0 = 3 CPU cycles, 1 = 1 CPU cycle.
&lt;/pre&gt;

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>5a3f0e7fc44ae69303307ce9bf26bd84df5a1de6</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>407</id>
    <parentid>283</parentid>
    <timestamp>2024-12-11T18:21:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Command -&gt; Control, disambiguate</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1627" xml:space="preserve">The Bandai 2001 (LUXSOR) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! $C4
| External EEPROM Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;&lt;br/&gt;or &lt;tt style="white-space: nowrap"&gt;0000 01CC aaaa aaaa&lt;/tt&gt;&lt;br/&gt; or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ASWR ....&lt;/tt&gt;
| W8
| Abort (A), Short (S), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

== EEPROM ==

The 2001's EEPROM interface is similar to the internal EEPROM interface, as documented on [[EEPROM#I/O_ports|the EEPROM page]]. Differences include:

* Instead of the internal EEPROM interface's P(rotect) bit, the A(bort) bit is provided. When the A bit is set, the transaction immediately stops.
* The EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

(Upload logic analyzer traces here)</text>
    <sha1>f5e14a33fb4d55ea5ad6ce489a39783f870ba2b7</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>408</id>
    <parentid>341</parentid>
    <timestamp>2024-12-12T15:26:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Commands */ ERAL/WRAL</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9445" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

The WRAL command erases the word at all address of the EEPROM, setting them to 0xFFFF.

This command is not guaranteed to be present on all EEPROMs.

=== ERAL - Erase All ===

The WRAL command takes a word and writes it to all addresses of the EEPROM.

This command is not guaranteed to be present on all EEPROMs.

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - 0&lt;br/&gt;
4 - AB
|-
| $76 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID)
|-
| $77 || 1 || Last booted [[ROM header]] byte 7 (color)
|-
| $78 || 1 || Last booted [[ROM header]] byte 8 (game ID)
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $80 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID) - only changed if byte 7 (color) != 0
|-
| $81 || 1 || Last booted [[ROM header]] byte 7 (color) - only changed if byte 7 (color) != 0
|-
| $82 || 1 || Last booted [[ROM header]] byte 8 (game ID) - only changed if byte 7 (color) != 0
|-
| $83 || 1 || Color console configuration
|-
| $84 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color console configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>60f284030b96c4d35ac57887e0a471f6e3eeda24</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>Real-Time Clock</title>
  <ns>0</ns>
  <id>40</id>
  <revision>
    <id>409</id>
    <parentid>177</parentid>
    <timestamp>2024-12-13T15:14:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>clarify register layout</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5885" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour &gt;= 12); however, writes to the bit are ignored.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>2de1c770ad7e9153610e1c0751ed0cb9efbd3e90</sha1>
  </revision>
  <revision>
    <id>410</id>
    <parentid>409</parentid>
    <timestamp>2024-12-13T15:17:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Alarm configuration */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5917" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour &gt;= 12); however, writes to the bit are ignored.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>4a6e5162754a9d230c62a337d7a6c4ec0821ef9b</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>WonderWitch/FreyaBIOS/Timer</title>
  <ns>0</ns>
  <id>62</id>
  <revision>
    <id>411</id>
    <parentid>375</parentid>
    <timestamp>2024-12-13T15:19:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1936" xml:space="preserve">The Timer interrupt provides an abstraction layer for the WonderSwan's [[Timers|timers]], as well as the on-cartridge [[Real-Time Clock|RTC]].

== Types ==

=== RTC fields ===

The RTC field indexes match the order of fields returned by the S-3511A chip. Note that the values returned by FreyaBIOS are binary numbers rather than BCD numbers - they are transparently converted when communicating with the on-cartridge RTC.

{| class="wikitable"
|-
! Index !! Data !! Format
|-
| 0 || Year || 0 - 99; 0 is assumed to be the year 2000.
|-
| 1 || Month || 1 - 12
|-
| 2 || Date (day of month) || 1 - 31
|-
| 3 || Day of week || 0 - 6; 0 = Sunday, 1 = Monday, ..., 6 = Saturday
|-
| 4 || Hour || 0 - 23
|-
| 5 || Minute || 0 - 59
|-
| 6 || Second || 0 - 59
|}

=== RTC struct ===

The RTC struct is a seven-byte memory structure, containing all RTC fields consecutively, taking up one unsinged byte each.

== Interrupts ==

=== INT $16/AH=$00 - rtc_reset ===

* AH = $00

=== INT $16/AH=$01 - rtc_set_datetime ===

* AH = $01
* BX = Field
* CX = Value of field

=== INT $16/AH=$02 - rtc_get_datetime ===

* AH = $02
* BX = Field

Return:

* AX = Value of field

=== INT $16/AH=$03 - rtc_set_datetime_struct ===

* AH = $03
* DS:DX = Pointer to RTC struct

=== INT $16/AH=$04 - rtc_get_datetime_struct ===

* AH = $04
* DS:DX = Pointer to RTC struct

=== INT $16/AH=$05 - rtc_enable_alarm ===

* AH = $05
* BL = Hour
* BH = Minute

=== INT $16/AH=$06 - rtc_disable_alarm ===

* AH = $06

=== INT $16/AH=$07 - timer_enable ===

* AH = $07
* AL = Type (0 = HBlank, 1 = VBlank)
* BL = Reload mode (0 = one-shot, 1 = repeating)
* CX = Time, in lines or frames, to wait.

=== INT $16/AH=$08 - timer_disable ===

* AH = $08
* AL = Type (0 = HBlank, 1 = VBlank)

=== INT $16/AH=$09 - timer_get_count ===

* AH = $09
* AL = Type (0 = HBlank, 1 = VBlank)

Return:

* AX = The current counter value, from the time set in &lt;code&gt;timer_enable&lt;/code&gt; down.</text>
    <sha1>38826513f6f38c92cfefc4054956e0970f14956e</sha1>
  </revision>
  <revision>
    <id>432</id>
    <parentid>411</parentid>
    <timestamp>2024-12-20T13:29:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $16/AH=$00 - rtc_reset */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2022" xml:space="preserve">The Timer interrupt provides an abstraction layer for the WonderSwan's [[Timers|timers]], as well as the on-cartridge [[Real-Time Clock|RTC]].

== Types ==

=== RTC fields ===

The RTC field indexes match the order of fields returned by the S-3511A chip. Note that the values returned by FreyaBIOS are binary numbers rather than BCD numbers - they are transparently converted when communicating with the on-cartridge RTC.

{| class="wikitable"
|-
! Index !! Data !! Format
|-
| 0 || Year || 0 - 99; 0 is assumed to be the year 2000.
|-
| 1 || Month || 1 - 12
|-
| 2 || Date (day of month) || 1 - 31
|-
| 3 || Day of week || 0 - 6; 0 = Sunday, 1 = Monday, ..., 6 = Saturday
|-
| 4 || Hour || 0 - 23
|-
| 5 || Minute || 0 - 59
|-
| 6 || Second || 0 - 59
|}

=== RTC struct ===

The RTC struct is a seven-byte memory structure, containing all RTC fields consecutively, taking up one unsinged byte each.

== Interrupts ==

=== INT $16/AH=$00 - rtc_reset ===

* AH = $00

Initializes the RTC status register (all interrupts disabled, 24-hour mode enabled).

=== INT $16/AH=$01 - rtc_set_datetime ===

* AH = $01
* BX = Field
* CX = Value of field

=== INT $16/AH=$02 - rtc_get_datetime ===

* AH = $02
* BX = Field

Return:

* AX = Value of field

=== INT $16/AH=$03 - rtc_set_datetime_struct ===

* AH = $03
* DS:DX = Pointer to RTC struct

=== INT $16/AH=$04 - rtc_get_datetime_struct ===

* AH = $04
* DS:DX = Pointer to RTC struct

=== INT $16/AH=$05 - rtc_enable_alarm ===

* AH = $05
* BL = Hour
* BH = Minute

=== INT $16/AH=$06 - rtc_disable_alarm ===

* AH = $06

=== INT $16/AH=$07 - timer_enable ===

* AH = $07
* AL = Type (0 = HBlank, 1 = VBlank)
* BL = Reload mode (0 = one-shot, 1 = repeating)
* CX = Time, in lines or frames, to wait.

=== INT $16/AH=$08 - timer_disable ===

* AH = $08
* AL = Type (0 = HBlank, 1 = VBlank)

=== INT $16/AH=$09 - timer_get_count ===

* AH = $09
* AL = Type (0 = HBlank, 1 = VBlank)

Return:

* AX = The current counter value, from the time set in &lt;code&gt;timer_enable&lt;/code&gt; down.</text>
    <sha1>da3adb44c44b18b2ce2d5876729486c779d7fbcd</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>WonderWitch/Memory map</title>
  <ns>0</ns>
  <id>65</id>
  <revision>
    <id>412</id>
    <parentid>386</parentid>
    <timestamp>2024-12-13T20:45:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3332" xml:space="preserve">The following documents the WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | Internal BIOS area
|-
| style="text-align: center;" | 0x0290
| rowspan="8" style="text-align: center;" | Stack, User IRAM
| rowspan="6" style="text-align: center;" | Stack, User IRAM
| rowspan="3" style="text-align: center;" | Stack, User IRAM
| style="text-align: center;" | Stack, User IRAM
|-
| style="text-align: center;" | 0x0E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.

==== Interrupt vectors ====

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

{| class="wikitable"
! Bank
! Description
|-
| 0
| [[WonderWitch/Filesystem|/ram0 file data]]
|-
| 1
| Third process data
|-
| 2
| Second process data
|-
| 3
| First process data; typically used by [[WonderWitch/FreyaOS|FreyaOS]]
|}

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/Filesystem|/rom0 file data]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}</text>
    <sha1>264ad8388151bd616edbccd3031616216c77b303</sha1>
  </revision>
  <revision>
    <id>413</id>
    <parentid>412</parentid>
    <timestamp>2024-12-13T20:46:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal RAM (0x00000 - 0x0FFFF) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3567" xml:space="preserve">The following documents the WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | Internal BIOS area
|-
| style="text-align: center;" | 0x0290
| rowspan="8" style="text-align: center;" | Stack, user IRAM
| rowspan="6" style="text-align: center;" | Stack, user IRAM
| rowspan="3" style="text-align: center;" | Stack, user IRAM
| style="text-align: center;" | Stack, User IRAM
|-
| style="text-align: center;" | 0x0E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.

==== Interrupt vectors ====

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|}

==== Internal BIOS area ====

{| class="wikitable"
! Start
! Length
! Description
|-
| 0x100
| 128
| Temporary memory buffer. Used for XMODEM transfers by FreyaOS.
|-
| 0x230
| 2
| Near pointer to temporary memory buffer (0x0100).
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

{| class="wikitable"
! Bank
! Description
|-
| 0
| [[WonderWitch/Filesystem|/ram0 file data]]
|-
| 1
| Third process data
|-
| 2
| Second process data
|-
| 3
| First process data; typically used by [[WonderWitch/FreyaOS|FreyaOS]]
|}

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/Filesystem|/rom0 file data]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}</text>
    <sha1>8795f1daf3c49da52baa170f58ecec1e40015fb5</sha1>
  </revision>
  <revision>
    <id>414</id>
    <parentid>413</parentid>
    <timestamp>2024-12-13T20:48:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3612" xml:space="preserve">The following documents the WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | Internal BIOS area
|-
| style="text-align: center;" | 0x0290
| rowspan="8" style="text-align: center;" | Stack, user IRAM
| rowspan="6" style="text-align: center;" | Stack, user IRAM
| rowspan="3" style="text-align: center;" | Stack, user IRAM
| style="text-align: center;" | Stack, User IRAM
|-
| style="text-align: center;" | 0x0E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.

==== Interrupt vectors ====

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|}

==== Internal BIOS area ====

{| class="wikitable"
! Start
! Length
! Description
|-
| 0x100
| 128
| Temporary memory buffer. Used for XMODEM transfers by FreyaOS.
|-
| 0x180
| 64
| Wavetable memory location.
|-
| 0x230
| 2
| Near pointer to temporary memory buffer (0x0100).
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

{| class="wikitable"
! Bank
! Description
|-
| 0
| [[WonderWitch/Filesystem|/ram0 file data]]
|-
| 1
| Third process data
|-
| 2
| Second process data
|-
| 3
| First process data; typically used by [[WonderWitch/FreyaOS|FreyaOS]]
|}

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/Filesystem|/rom0 file data]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}</text>
    <sha1>c8f8fec7ca7cd8e501b3877c69e38597a73d9004</sha1>
  </revision>
  <revision>
    <id>415</id>
    <parentid>414</parentid>
    <timestamp>2024-12-13T21:05:00Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal RAM (0x00000 - 0x0FFFF) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3802" xml:space="preserve">The following documents the WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | Internal BIOS area
|-
| style="text-align: center;" | 0x0290
| rowspan="8" style="text-align: center;" | Stack, user IRAM
| rowspan="6" style="text-align: center;" | Stack, user IRAM
| rowspan="3" style="text-align: center;" | Stack, user IRAM
| style="text-align: center;" | Stack, User IRAM
|-
| style="text-align: center;" | 0x0E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.

Note that the user IRAM area is shared between all users of FreyaBIOS - notably, FreyaOS puts 

==== Interrupt vectors ====

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|}

==== Internal BIOS area ====

{| class="wikitable"
! Start
! Length
! Description
|-
| 0x100
| 128
| Temporary memory buffer. Used for XMODEM transfers by FreyaOS.
|-
| 0x180
| 64
| Wavetable memory location.
|-
| 0x204
| 2/4?
| Written to by FreyaOS using ''sys_alloc_iram'' to point to its IRAM area.
|-
| 0x230
| 2
| Near pointer to temporary memory buffer (0x0100).
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

{| class="wikitable"
! Bank
! Description
|-
| 0
| [[WonderWitch/Filesystem|/ram0 file data]]
|-
| 1
| Third process data
|-
| 2
| Second process data
|-
| 3
| First process data; typically used by [[WonderWitch/FreyaOS|FreyaOS]]
|}

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/Filesystem|/rom0 file data]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}</text>
    <sha1>8f3627615b1d16a795a728d87f7892e5b3ff29a7</sha1>
  </revision>
  <revision>
    <id>427</id>
    <parentid>415</parentid>
    <timestamp>2024-12-16T15:29:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupt vectors */ document SoC interrupts</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3855" xml:space="preserve">The following documents the WonderWitch memory map. Note that you are not required to follow these rules to the letter; however, some amount of the beginning of memory is expected to be left to FreyaBIOS, FreyaOS, etc.

=== Internal RAM (0x00000 - 0x0FFFF) ===

{| class="wikitable"
|+ WonderWitch memory map
! Address
! ASCII, 1 screen
! ASCII, 2 screens
! Shift-JIS, 1 screen
! Shift-JIS, 2 screens
|-
| style="text-align: center;" | 0x0000
| colspan="4" style="text-align: center;" | Interrupt vectors
|-
| style="text-align: center;" | 0x0100
| colspan="4" style="text-align: center;" | Internal BIOS area
|-
| style="text-align: center;" | 0x0290
| rowspan="8" style="text-align: center;" | Stack, user IRAM
| rowspan="6" style="text-align: center;" | Stack, user IRAM
| rowspan="3" style="text-align: center;" | Stack, user IRAM
| style="text-align: center;" | Stack, User IRAM
|-
| style="text-align: center;" | 0x0E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1000
| rowspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x1600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x1800
| style="text-align: center;" | Screen 1
| style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2000
| rowspan="6" colspan="2" style="text-align: center;" | Tile data (512 tiles)
|-
| style="text-align: center;" | 0x2600
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x2800
| rowspan="2" style="text-align: center;" | Screen 2
|-
| style="text-align: center;" | 0x2E00
| style="text-align: center;" | Sprite table
|-
| style="text-align: center;" | 0x3000
| colspan="2" style="text-align: center;" | Screen 1
|-
| style="text-align: center;" | 0x3800
| colspan="2" style="text-align: center;" | Tile data (128 tiles)
|-
| style="text-align: center;" | 0x4000
| colspan="4" style="text-align: center;" | Color tile data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|-
| style="text-align: center;" | 0xC000
| colspan="4" style="text-align: center;" | Unused; never restored on program suspend/resume.
|-
| style="text-align: center;" | 0xFE00
| colspan="4" style="text-align: center;" | Color palette data; only restored with [[WonderWitch/IL/ResumeIL|ResumeIL]].
|}

In all modes, the stack is placed immediately before the sprite table.

Note that the user IRAM area is shared between all users of FreyaBIOS - notably, FreyaOS puts 

==== Interrupt vectors ====

{| class="wikitable"
! Start
! End
! Description
|-
| 0x00
| 0x07
| CPU interrupts
|-
| 0x08
| 0x0F
|
|-
| 0x10
| 0x18
| [[WonderWitch/FreyaBIOS|FreyaBIOS]] interrupts
|-
| 0x19
| 0x27
|
|-
| 0x28
| 0x2F
| SoC interrupts
|}

==== Internal BIOS area ====

{| class="wikitable"
! Start
! Length
! Description
|-
| 0x100
| 128
| Temporary memory buffer. Used for XMODEM transfers by FreyaOS.
|-
| 0x180
| 64
| Wavetable memory location.
|-
| 0x204
| 2/4?
| Written to by FreyaOS using ''sys_alloc_iram'' to point to its IRAM area.
|-
| 0x230
| 2
| Near pointer to temporary memory buffer (0x0100).
|}

=== Cartridge SRAM (0x10000 - 0x1FFFF) ===

{| class="wikitable"
! Bank
! Description
|-
| 0
| [[WonderWitch/Filesystem|/ram0 file data]]
|-
| 1
| Third process data
|-
| 2
| Second process data
|-
| 3
| First process data; typically used by [[WonderWitch/FreyaOS|FreyaOS]]
|}

=== Cartridge flash (0x80000 - 0xFFFFF) ===

The 512KB of NOR flash memory is mapped and partitioned as follows:

{| class="wikitable"
! Linear address
! Size
! Description
|-
| 0x8nnnn
| rowspan="6" | 384 KB
| rowspan="6" | [[WonderWitch/Filesystem|/rom0 file data]]
|-
| 0x9nnnn
|-
| 0xAnnnn
|-
| 0xBnnnn
|-
| 0xCnnnn
|-
| 0xDnnnn
|-
| 0xEnnnn
| 64 KB
| [[WonderWitch/FreyaOS|FreyaOS]]
|-
| 0xFnnnn
| 64 KB
| [[WonderWitch/FreyaBIOS|FreyaBIOS]]
|}</text>
    <sha1>6945e1835188234a04d4b6019249c68571d2ff53</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>WonderWitch/FreyaBIOS/Communication</title>
  <ns>0</ns>
  <id>54</id>
  <revision>
    <id>416</id>
    <parentid>326</parentid>
    <timestamp>2024-12-14T10:36:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $14/AH=$0D - comm_xmodem */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3981" xml:space="preserve">The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].

== Interrupts ==

=== INT $14/AH=$00 - comm_open ===

* AH = $00

Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.

=== INT $14/AH=$01 - comm_close ===

* AH = $01

Closes the serial port.

=== INT $14/AH=$02 - comm_send_char ===

* AH = $02
* BL = Character (byte) to send.

Return:

* AX = Return code.

Return codes:

* 0x0000 - Success
* 0x8101 - Transfer timeout
* 0x8102 - Transfer RX overrun
* 0x8103 - Transfer cancelled

=== INT $14/AH=$03 - comm_receive_char ===

* AH = $03

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

=== INT $14/AH=$04 - comm_receive_with_timeout ===

* AH = $03
* CX = Timeout, in frames (as in &lt;code&gt;comm_set_timeout&lt;/code&gt;).

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

Unlike &lt;code&gt;comm_receive_char&lt;/code&gt;, this function uses an user-provided timeout.

=== INT $14/AH=$05 - comm_send_string ===

* AH = $05
* DS:DX = Input string to send.

Return:

* AX = Return code.

=== INT $14/AH=$06 - comm_send_block ===

* AH = $06
* CX = Buffer size, in bytes.
* DS:DX = Input buffer to send.

Return:

* AX = Return code.

=== INT $14/AH=$07 - comm_receive_block ===

* AH = $07
* CX = Buffer size, in bytes.
* DS:DX = Buffer to receive bytes to.

Return:

* AX = Return code.
* DX = Number of bytes successfully received.

=== INT $14/AH=$08 - comm_set_timeout ===

* AH = $08
* BX = Receive timeout (in frames; 0xFFFF - wait forever)
* CX = Send timeout (in frames; 0xFFFF - wait forever)

=== INT $14/AH=$09 - comm_set_baudrate ===

* AH = $09
* BX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

Only affects newly opened serial port connections.

=== INT $14/AH=$0A - comm_get_baudrate ===

* AH = $0A

Return:

* AX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

=== INT $14/AH=$0B - comm_set_cancel_key ===

* AH = $0B
* BX = Cancel key combination.

=== INT $14/AH=$0C - comm_get_cancel_key ===

* AH = $0C

Return:

* AX = Cancel key combination.

=== INT $14/AH=$0D - comm_xmodem ===

* AH = $0D
* DS:BX = pointer to XMODEM state structure

Returns:

* AX = new state (equal to ''State'' in the structure)

==== Usage ====


==== Data structures ====

{| class="wikitable"
|+ XMODEM state structure
! Offset
! Size
! Description
|-
| $00
| 2
| State (or error code, if bit 15 set)
|-
| $02
| 1
| Mode
|-
| $03
| 1
| Number of total block transfer retries performed
|-
| $04
| 2
| Number of blocks received/sent
|-
| $06
| 2
| Maximum number of blocks to receive
Number of blocks to send
|-
| $08
| 2
| Size of block, typically 128 bytes
|-
| $0A
| 2
| Bank to write to/read from
|-
| $0C
| 2
| Offset to write to/read from
|-
| $0E
| 2
| ?
|}

{| class="wikitable"
|+ XMODEM state values
! Value
! Description
|-
| $0001
| Start
Set initial values:
* Number of retries = 0
* Current block = 0
* Block size = 128 bytes
Goes to state "Negotiate".
|-
| $0002
| Negotiate
Also receives the first block.&lt;br/&gt;
Goes to state "Block".
|-
| $0003
| Block
Sends or receives a block.&lt;br/&gt;
Goes to state "Block" (if successful), "Retry Block" (if failed), or "Close" (if transfer complete).
|-
| $0004
| Retry Block
Same as Block.
|-
| $0005
| Close
Finishes the XMODEM transfer.&lt;br/&gt;
Goes to state "Done".
|-
| $0006
| Abort
Treated as an "Invalid state value".
|-
| $0007
| Done
Treated as an "Invalid state value".
|-
| $0008
| Erase bank
Goes to state "Block".
|-
| $8100
| Serial I/O: Busy
|-
| $8101
| Serial I/O: Transfer timeout
|-
| $8102
| Serial I/O: Transfer RX overrun
|-
| $8103
| Serial I/O: Transfer cancelled
|-
| $8104
| Invalid state value
|-
| $8105
| XMODEM transfer cancelled
|-
| $8106
| XMODEM block lost during transfer
|-
| $8107
| XMODEM transfer too large
|}

XMODEM mode:

 7  bit  0
 ---- ----
 .... .?od
        ||
        |+- Direction: 0 = Send, 1 = Receive
        +-- Enable obfuscation</text>
    <sha1>c4d7e0f4928cde730e170e7fef8316a5bf8abb69</sha1>
  </revision>
  <revision>
    <id>417</id>
    <parentid>416</parentid>
    <timestamp>2024-12-14T10:39:31Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Usage */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4311" xml:space="preserve">The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].

== Interrupts ==

=== INT $14/AH=$00 - comm_open ===

* AH = $00

Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.

=== INT $14/AH=$01 - comm_close ===

* AH = $01

Closes the serial port.

=== INT $14/AH=$02 - comm_send_char ===

* AH = $02
* BL = Character (byte) to send.

Return:

* AX = Return code.

Return codes:

* 0x0000 - Success
* 0x8101 - Transfer timeout
* 0x8102 - Transfer RX overrun
* 0x8103 - Transfer cancelled

=== INT $14/AH=$03 - comm_receive_char ===

* AH = $03

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

=== INT $14/AH=$04 - comm_receive_with_timeout ===

* AH = $03
* CX = Timeout, in frames (as in &lt;code&gt;comm_set_timeout&lt;/code&gt;).

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

Unlike &lt;code&gt;comm_receive_char&lt;/code&gt;, this function uses an user-provided timeout.

=== INT $14/AH=$05 - comm_send_string ===

* AH = $05
* DS:DX = Input string to send.

Return:

* AX = Return code.

=== INT $14/AH=$06 - comm_send_block ===

* AH = $06
* CX = Buffer size, in bytes.
* DS:DX = Input buffer to send.

Return:

* AX = Return code.

=== INT $14/AH=$07 - comm_receive_block ===

* AH = $07
* CX = Buffer size, in bytes.
* DS:DX = Buffer to receive bytes to.

Return:

* AX = Return code.
* DX = Number of bytes successfully received.

=== INT $14/AH=$08 - comm_set_timeout ===

* AH = $08
* BX = Receive timeout (in frames; 0xFFFF - wait forever)
* CX = Send timeout (in frames; 0xFFFF - wait forever)

=== INT $14/AH=$09 - comm_set_baudrate ===

* AH = $09
* BX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

Only affects newly opened serial port connections.

=== INT $14/AH=$0A - comm_get_baudrate ===

* AH = $0A

Return:

* AX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

=== INT $14/AH=$0B - comm_set_cancel_key ===

* AH = $0B
* BX = Cancel key combination.

=== INT $14/AH=$0C - comm_get_cancel_key ===

* AH = $0C

Return:

* AX = Cancel key combination.

=== INT $14/AH=$0D - comm_xmodem ===

* AH = $0D
* DS:BX = pointer to XMODEM state structure

Returns:

* AX = new state (equal to ''State'' in the structure)

==== Usage ====

To use comm_xmodem, allocate the state structure and set the following values:

* State = $0001 ("Start")
* Mode = your mode of choice
* Maximum number of blocks = the transfer size, in XMODEM blocks
* Bank, Offset = the transfer source/destination

Next, keep calling comm_xmodem until the "Done" state, or an error, is returned.

==== Data structures ====

{| class="wikitable"
|+ XMODEM state structure
! Offset
! Size
! Description
|-
| $00
| 2
| State (or error code, if bit 15 set)
|-
| $02
| 1
| Mode
|-
| $03
| 1
| Number of total block transfer retries performed
|-
| $04
| 2
| Number of blocks received/sent
|-
| $06
| 2
| Maximum number of blocks to receive
Number of blocks to send
|-
| $08
| 2
| Size of block, typically 128 bytes
|-
| $0A
| 2
| Bank to write to/read from
|-
| $0C
| 2
| Offset to write to/read from
|-
| $0E
| 2
| ?
|}

{| class="wikitable"
|+ XMODEM state values
! Value
! Description
|-
| $0001
| Start
Set initial values:
* Number of retries = 0
* Current block = 0
* Block size = 128 bytes
Goes to state "Negotiate".
|-
| $0002
| Negotiate
Also receives the first block.&lt;br/&gt;
Goes to state "Block".
|-
| $0003
| Block
Sends or receives a block.&lt;br/&gt;
Goes to state "Block" (if successful), "Retry Block" (if failed), or "Close" (if transfer complete).
|-
| $0004
| Retry Block
Same as Block.
|-
| $0005
| Close
Finishes the XMODEM transfer.&lt;br/&gt;
Goes to state "Done".
|-
| $0006
| Abort
Treated as an "Invalid state value".
|-
| $0007
| Done
Treated as an "Invalid state value".
|-
| $0008
| Erase bank
Goes to state "Block".
|-
| $8100
| Serial I/O: Busy
|-
| $8101
| Serial I/O: Transfer timeout
|-
| $8102
| Serial I/O: Transfer RX overrun
|-
| $8103
| Serial I/O: Transfer cancelled
|-
| $8104
| Invalid state value
|-
| $8105
| XMODEM transfer cancelled
|-
| $8106
| XMODEM block lost during transfer
|-
| $8107
| XMODEM transfer too large
|}

XMODEM mode:

 7  bit  0
 ---- ----
 .... .?od
        ||
        |+- Direction: 0 = Send, 1 = Receive
        +-- Enable obfuscation</text>
    <sha1>b0cf24c05046ff8f87b3b65322fc7e5195223863</sha1>
  </revision>
  <revision>
    <id>418</id>
    <parentid>417</parentid>
    <timestamp>2024-12-14T21:27:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>comm_xmodem: clarify basic workflows</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5027" xml:space="preserve">The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].

== Interrupts ==

=== INT $14/AH=$00 - comm_open ===

* AH = $00

Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.

=== INT $14/AH=$01 - comm_close ===

* AH = $01

Closes the serial port.

=== INT $14/AH=$02 - comm_send_char ===

* AH = $02
* BL = Character (byte) to send.

Return:

* AX = Return code.

Return codes:

* 0x0000 - Success
* 0x8101 - Transfer timeout
* 0x8102 - Transfer RX overrun
* 0x8103 - Transfer cancelled

=== INT $14/AH=$03 - comm_receive_char ===

* AH = $03

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

=== INT $14/AH=$04 - comm_receive_with_timeout ===

* AH = $03
* CX = Timeout, in frames (as in &lt;code&gt;comm_set_timeout&lt;/code&gt;).

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

Unlike &lt;code&gt;comm_receive_char&lt;/code&gt;, this function uses an user-provided timeout.

=== INT $14/AH=$05 - comm_send_string ===

* AH = $05
* DS:DX = Input string to send.

Return:

* AX = Return code.

=== INT $14/AH=$06 - comm_send_block ===

* AH = $06
* CX = Buffer size, in bytes.
* DS:DX = Input buffer to send.

Return:

* AX = Return code.

=== INT $14/AH=$07 - comm_receive_block ===

* AH = $07
* CX = Buffer size, in bytes.
* DS:DX = Buffer to receive bytes to.

Return:

* AX = Return code.
* DX = Number of bytes successfully received.

=== INT $14/AH=$08 - comm_set_timeout ===

* AH = $08
* BX = Receive timeout (in frames; 0xFFFF - wait forever)
* CX = Send timeout (in frames; 0xFFFF - wait forever)

=== INT $14/AH=$09 - comm_set_baudrate ===

* AH = $09
* BX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

Only affects newly opened serial port connections.

=== INT $14/AH=$0A - comm_get_baudrate ===

* AH = $0A

Return:

* AX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

=== INT $14/AH=$0B - comm_set_cancel_key ===

* AH = $0B
* BX = Cancel key combination.

=== INT $14/AH=$0C - comm_get_cancel_key ===

* AH = $0C

Return:

* AX = Cancel key combination.

=== INT $14/AH=$0D - comm_xmodem ===

* AH = $0D
* DS:BX = pointer to XMODEM state structure

Returns:

* AX = new state (equal to ''State'' in the structure)

==== Usage ====

To use comm_xmodem, allocate the state structure and set the following values:

* State = $0001 ("Start")
* Mode = your mode of choice
* Maximum number of blocks = the transfer size, in XMODEM blocks
* Bank, Offset = the transfer source/destination

Next, keep calling comm_xmodem until the "Done" state, or an error, is returned.

===== Typical flow - Send =====

* Initial: State = Start, Mode = Send
* State = Negotiate
* State = Block, Count = 0
* State = Block, Count = 1
* ...
* State = Block, Count = Max
* State = Close
* State = Done

===== Typical flow - Receive =====

* Initial: State = Start, Mode = Receive
* State = Negotiate
* State = Block, Count = 1
* State = Block, Count = 2
* ...
* State = Block, Count = N
* State = Close
* State = Done

Note that in the ''Receive'' flow, the Negotiate state returns ''after'' receiving the first block, as opposed to ''before'' sending the first block.

In both cases, the final block (Max) is not sent/received; if such a value is reached, the "transfer too large" error code is returned.

==== Data structures ====

{| class="wikitable"
|+ XMODEM state structure
! Offset
! Size
! Description
|-
| $00
| 2
| State (or error code, if bit 15 set)
|-
| $02
| 1
| Mode
|-
| $03
| 1
| Number of total block transfer retries performed
|-
| $04
| 2
| Number of blocks received/sent
|-
| $06
| 2
| Maximum number of blocks to receive
Number of blocks to send
|-
| $08
| 2
| Size of block, typically 128 bytes
|-
| $0A
| 2
| Bank to write to/read from
|-
| $0C
| 2
| Offset to write to/read from
|-
| $0E
| 2
| ?
|}

{| class="wikitable"
|+ XMODEM state values
! Value
! Description
|-
| $0001
| Start
Set initial values:
* Number of retries = 0
* Current block = 0
* Block size = 128 bytes
Goes to state "Negotiate".
|-
| $0002
| Negotiate
Also receives the first block.&lt;br/&gt;
Goes to state "Block".
|-
| $0003
| Block
Sends or receives a block.&lt;br/&gt;
Goes to state "Block" (if successful), "Retry Block" (if failed), or "Close" (if transfer complete).
|-
| $0004
| Retry Block
Same as Block.
|-
| $0005
| Close
Finishes the XMODEM transfer.&lt;br/&gt;
Goes to state "Done".
|-
| $0006
| Abort
Treated as an "Invalid state value".
|-
| $0007
| Done
Treated as an "Invalid state value".
|-
| $0008
| Erase bank
Goes to state "Block".
|-
| $8100
| Serial I/O: Busy
|-
| $8101
| Serial I/O: Transfer timeout
|-
| $8102
| Serial I/O: Transfer RX overrun
|-
| $8103
| Serial I/O: Transfer cancelled
|-
| $8104
| Invalid state value
|-
| $8105
| XMODEM transfer cancelled
|-
| $8106
| XMODEM block lost during transfer
|-
| $8107
| XMODEM transfer too large
|}

XMODEM mode:

 7  bit  0
 ---- ----
 .... .?od
        ||
        |+- Direction: 0 = Send, 1 = Receive
        +-- Enable obfuscation</text>
    <sha1>1211a7c4c967af7539dc477a6d5fa5c4eb154682</sha1>
  </revision>
  <revision>
    <id>426</id>
    <parentid>418</parentid>
    <timestamp>2024-12-16T14:13:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $14/AH=$0D - comm_xmodem */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5127" xml:space="preserve">The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].

== Interrupts ==

=== INT $14/AH=$00 - comm_open ===

* AH = $00

Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.

=== INT $14/AH=$01 - comm_close ===

* AH = $01

Closes the serial port.

=== INT $14/AH=$02 - comm_send_char ===

* AH = $02
* BL = Character (byte) to send.

Return:

* AX = Return code.

Return codes:

* 0x0000 - Success
* 0x8101 - Transfer timeout
* 0x8102 - Transfer RX overrun
* 0x8103 - Transfer cancelled

=== INT $14/AH=$03 - comm_receive_char ===

* AH = $03

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

=== INT $14/AH=$04 - comm_receive_with_timeout ===

* AH = $03
* CX = Timeout, in frames (as in &lt;code&gt;comm_set_timeout&lt;/code&gt;).

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

Unlike &lt;code&gt;comm_receive_char&lt;/code&gt;, this function uses an user-provided timeout.

=== INT $14/AH=$05 - comm_send_string ===

* AH = $05
* DS:DX = Input string to send.

Return:

* AX = Return code.

=== INT $14/AH=$06 - comm_send_block ===

* AH = $06
* CX = Buffer size, in bytes.
* DS:DX = Input buffer to send.

Return:

* AX = Return code.

=== INT $14/AH=$07 - comm_receive_block ===

* AH = $07
* CX = Buffer size, in bytes.
* DS:DX = Buffer to receive bytes to.

Return:

* AX = Return code.
* DX = Number of bytes successfully received.

=== INT $14/AH=$08 - comm_set_timeout ===

* AH = $08
* BX = Receive timeout (in frames; 0xFFFF - wait forever)
* CX = Send timeout (in frames; 0xFFFF - wait forever)

=== INT $14/AH=$09 - comm_set_baudrate ===

* AH = $09
* BX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

Only affects newly opened serial port connections.

=== INT $14/AH=$0A - comm_get_baudrate ===

* AH = $0A

Return:

* AX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

=== INT $14/AH=$0B - comm_set_cancel_key ===

* AH = $0B
* BX = Cancel key combination.

=== INT $14/AH=$0C - comm_get_cancel_key ===

* AH = $0C

Return:

* AX = Cancel key combination.

=== INT $14/AH=$0D - comm_xmodem ===

* AH = $0D
* DS:BX = pointer to XMODEM state structure

Returns:

* AX = new state (equal to ''State'' in the structure)

==== Usage ====

To use comm_xmodem, allocate the state structure and set the following values:

* State = $0001 ("Start")
* Mode = your mode of choice
* Maximum number of blocks = the transfer size, in XMODEM blocks
* Bank, Offset = the transfer source/destination

Next, keep calling comm_xmodem until the "Done" state, or an error, is returned.

The Bank and Offset are auto-incremented by the block size (in bytes) on each successful transfer.

===== Typical flow - Send =====

* Initial: State = Start, Mode = Send
* State = Negotiate
* State = Block, Count = 0
* State = Block, Count = 1
* ...
* State = Block, Count = Max
* State = Close
* State = Done

===== Typical flow - Receive =====

* Initial: State = Start, Mode = Receive
* State = Negotiate
* State = Block, Count = 1
* State = Block, Count = 2
* ...
* State = Block, Count = N
* State = Close
* State = Done

Note that in the ''Receive'' flow, the Negotiate state returns ''after'' receiving the first block, as opposed to ''before'' sending the first block.

In both cases, the final block (Max) is not sent/received; if such a value is reached, the "transfer too large" error code is returned.

==== Data structures ====

{| class="wikitable"
|+ XMODEM state structure
! Offset
! Size
! Description
|-
| $00
| 2
| State (or error code, if bit 15 set)
|-
| $02
| 1
| Mode
|-
| $03
| 1
| Number of total block transfer retries performed
|-
| $04
| 2
| Number of blocks received/sent
|-
| $06
| 2
| Maximum number of blocks to receive
Number of blocks to send
|-
| $08
| 2
| Size of block, typically 128 bytes
|-
| $0A
| 2
| Bank to write to/read from
|-
| $0C
| 2
| Offset to write to/read from
|-
| $0E
| 2
| ?
|}

{| class="wikitable"
|+ XMODEM state values
! Value
! Description
|-
| $0001
| Start
Set initial values:
* Number of retries = 0
* Current block = 0
* Block size = 128 bytes
Goes to state "Negotiate".
|-
| $0002
| Negotiate
Also receives the first block.&lt;br/&gt;
Goes to state "Block".
|-
| $0003
| Block
Sends or receives a block.&lt;br/&gt;
Goes to state "Block" (if successful), "Retry Block" (if failed), or "Close" (if transfer complete).
|-
| $0004
| Retry Block
Same as Block.
|-
| $0005
| Close
Finishes the XMODEM transfer.&lt;br/&gt;
Goes to state "Done".
|-
| $0006
| Abort
Treated as an "Invalid state value".
|-
| $0007
| Done
Treated as an "Invalid state value".
|-
| $0008
| Erase bank
Goes to state "Block".
|-
| $8100
| Serial I/O: Busy
|-
| $8101
| Serial I/O: Transfer timeout
|-
| $8102
| Serial I/O: Transfer RX overrun
|-
| $8103
| Serial I/O: Transfer cancelled
|-
| $8104
| Invalid state value
|-
| $8105
| XMODEM transfer cancelled
|-
| $8106
| XMODEM block lost during transfer
|-
| $8107
| XMODEM transfer too large
|}

XMODEM mode:

 7  bit  0
 ---- ----
 .... .?od
        ||
        |+- Direction: 0 = Send, 1 = Receive
        +-- Enable obfuscation</text>
    <sha1>6c32fe368ca29d43c4730d77804c2be827333f95</sha1>
  </revision>
  <revision>
    <id>428</id>
    <parentid>426</parentid>
    <timestamp>2024-12-16T20:01:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $14/AH=$0D - comm_xmodem */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5227" xml:space="preserve">The Communication (comm) interrupt provides an abstraction layer and helpers for the WonderSwan's [[UART|serial port]].

== Interrupts ==

=== INT $14/AH=$00 - comm_open ===

* AH = $00

Opens the serial port. Note that the baud rate must be set before calling &lt;code&gt;comm_open&lt;/code&gt;.

=== INT $14/AH=$01 - comm_close ===

* AH = $01

Closes the serial port.

=== INT $14/AH=$02 - comm_send_char ===

* AH = $02
* BL = Character (byte) to send.

Return:

* AX = Return code.

Return codes:

* 0x0000 - Success
* 0x8101 - Transfer timeout
* 0x8102 - Transfer RX overrun
* 0x8103 - Transfer cancelled

=== INT $14/AH=$03 - comm_receive_char ===

* AH = $03

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

=== INT $14/AH=$04 - comm_receive_with_timeout ===

* AH = $03
* CX = Timeout, in frames (as in &lt;code&gt;comm_set_timeout&lt;/code&gt;).

Return:

* AX = Character (byte) read (0x0000 - 0xFFFF) or error return code.

Unlike &lt;code&gt;comm_receive_char&lt;/code&gt;, this function uses an user-provided timeout.

=== INT $14/AH=$05 - comm_send_string ===

* AH = $05
* DS:DX = Input string to send.

Return:

* AX = Return code.

=== INT $14/AH=$06 - comm_send_block ===

* AH = $06
* CX = Buffer size, in bytes.
* DS:DX = Input buffer to send.

Return:

* AX = Return code.

=== INT $14/AH=$07 - comm_receive_block ===

* AH = $07
* CX = Buffer size, in bytes.
* DS:DX = Buffer to receive bytes to.

Return:

* AX = Return code.
* DX = Number of bytes successfully received.

=== INT $14/AH=$08 - comm_set_timeout ===

* AH = $08
* BX = Receive timeout (in frames; 0xFFFF - wait forever)
* CX = Send timeout (in frames; 0xFFFF - wait forever)

=== INT $14/AH=$09 - comm_set_baudrate ===

* AH = $09
* BX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

Only affects newly opened serial port connections.

=== INT $14/AH=$0A - comm_get_baudrate ===

* AH = $0A

Return:

* AX = Baud rate (0 = 9600 bps, 1 = 38400 bps).

=== INT $14/AH=$0B - comm_set_cancel_key ===

* AH = $0B
* BX = Cancel key combination.

=== INT $14/AH=$0C - comm_get_cancel_key ===

* AH = $0C

Return:

* AX = Cancel key combination.

=== INT $14/AH=$0D - comm_xmodem ===

* AH = $0D
* DS:BX = pointer to XMODEM state structure

Returns:

* AX = new state (equal to ''State'' in the structure)

==== Usage ====

To use comm_xmodem, allocate the state structure and set the following values:

* State = $0001 ("Start")
* Mode = your mode of choice
* Maximum number of blocks = the transfer size, in XMODEM blocks
* Bank, Offset = the transfer source/destination

Next, keep calling comm_xmodem until the "Done" state, or an error, is returned.

The Bank and Offset are auto-incremented by the block size (in bytes) on each successful transfer.

===== Typical flow - Send =====

* Initial: State = Start, Mode = Send
* State = Negotiate
* State = Block, Count = 0
* State = Block, Count = 1
* ...
* State = Block, Count = Max
* State = Close
* State = Done

===== Typical flow - Receive =====

* Initial: State = Start, Mode = Receive
* State = Negotiate
* State = Block, Count = 1
* State = Block, Count = 2
* ...
* State = Block, Count = N
* State = Close
* State = Done

Note that in the ''Receive'' flow, the Negotiate state returns ''after'' receiving the first block, as opposed to ''before'' sending the first block.

In both cases, the final block (Max) is not sent/received; if such a value is reached, the "transfer too large" error code is returned.

==== Data structures ====

{| class="wikitable"
|+ XMODEM state structure
! Offset
! Size
! Description
|-
| $00
| 2
| State (or error code, if bit 15 set)
|-
| $02
| 1
| Mode
|-
| $03
| 1
| Number of total block transfer retries performed
|-
| $04
| 2
| Number of blocks received/sent
|-
| $06
| 2
| Maximum number of blocks to receive
Number of blocks to send
|-
| $08
| 2
| Size of block, typically 128 bytes
|-
| $0A
| 2
| Bank to write to/read from
|-
| $0C
| 2
| Offset to write to/read from
|-
| $0E
| 2
| ?
|}

{| class="wikitable"
|+ XMODEM state values
! Value
! Description
|-
| $0001
| Start
Set initial values:
* Number of retries = 0
* Current block = 0
* Block size = 128 bytes
Goes to state "Negotiate".
|-
| $0002
| Negotiate
Also receives the first block.&lt;br/&gt;
Goes to state "Block".
|-
| $0003
| Block
Send: Sends a block and waits for ACK/NAK.&lt;br/&gt;
Receive: Sends ACK and receives a block.&lt;/br&gt;
Goes to state "Block" (if successful), "Retry Block" (if failed), or "Close" (if transfer complete).
|-
| $0004
| Retry Block
Same as Block, except NAK is sent in "Receive" mode.
|-
| $0005
| Close
Finishes the XMODEM transfer.&lt;br/&gt;
Goes to state "Done".
|-
| $0006
| Abort
Treated as an "Invalid state value".
|-
| $0007
| Done
Treated as an "Invalid state value".
|-
| $0008
| Erase bank
Goes to state "Block".
|-
| $8100
| Serial I/O: Busy
|-
| $8101
| Serial I/O: Transfer timeout
|-
| $8102
| Serial I/O: Transfer RX overrun
|-
| $8103
| Serial I/O: Transfer cancelled
|-
| $8104
| Invalid state value
|-
| $8105
| XMODEM transfer cancelled
|-
| $8106
| XMODEM block lost during transfer
|-
| $8107
| XMODEM transfer too large
|}

XMODEM mode:

 7  bit  0
 ---- ----
 .... .?od
        ||
        |+- Direction: 0 = Send, 1 = Receive
        +-- Enable obfuscation</text>
    <sha1>7038af5a9e43a47733ce5de8a8ac1016ad1f684a</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>NEC V30MZ instruction set</title>
  <ns>0</ns>
  <id>68</id>
  <revision>
    <id>433</id>
    <timestamp>2024-12-26T14:32:59Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>auto-generated initial template</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10367" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |

|}

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{{Anchor|AAD}}
=== AAD ===

{{Anchor|AAM}}
=== AAM ===

{{Anchor|AAS}}
=== AAS ===

{{Anchor|ADC}}
=== ADC ===

{{Anchor|ADD}}
=== ADD ===

{{Anchor|AND}}
=== AND ===

{{Anchor|BOUND}}
=== BOUND ===

{{Anchor|CALL}}
=== CALL ===

{{Anchor|CBW}}
=== CBW ===

{{Anchor|CLC}}
=== CLC ===

{{Anchor|CLD}}
=== CLD ===

{{Anchor|CLI}}
=== CLI ===

{{Anchor|CMC}}
=== CMC ===

{{Anchor|CMP}}
=== CMP ===

{{Anchor|CMPSB}}
=== CMPSB ===

{{Anchor|CMPSW}}
=== CMPSW ===

{{Anchor|CS}}
=== CS ===

{{Anchor|CWD}}
=== CWD ===

{{Anchor|DAA}}
=== DAA ===

{{Anchor|DAS}}
=== DAS ===

{{Anchor|DEC}}
=== DEC ===

{{Anchor|DIV}}
=== DIV ===

{{Anchor|DS}}
=== DS ===

{{Anchor|ENTER}}
=== ENTER ===

{{Anchor|ES}}
=== ES ===

{{Anchor|HLT}}
=== HLT ===

{{Anchor|IDIV}}
=== IDIV ===

{{Anchor|IMUL}}
=== IMUL ===

{{Anchor|IN}}
=== IN ===

{{Anchor|INC}}
=== INC ===

{{Anchor|INSB}}
=== INSB ===

{{Anchor|INSW}}
=== INSW ===

{{Anchor|INT}}
=== INT ===

{{Anchor|INTO}}
=== INTO ===

{{Anchor|IRET}}
=== IRET ===

{{Anchor|JA}}
=== JA ===

{{Anchor|JBE}}
=== JBE ===

{{Anchor|JC}}
=== JC/JB ===

{{Anchor|JCXZ}}
=== JCXZ ===

{{Anchor|JG}}
=== JG ===

{{Anchor|JGE}}
=== JGE ===

{{Anchor|JL}}
=== JL ===

{{Anchor|JLE}}
=== JLE ===

{{Anchor|JMP}}
=== JMP ===

{{Anchor|JNC}}
=== JNC/JAE ===

{{Anchor|JNO}}
=== JNO ===

{{Anchor|JNP}}
=== JNP ===

{{Anchor|JNS}}
=== JNS ===

{{Anchor|JNZ}}
=== JNZ/JNE ===

{{Anchor|JO}}
=== JO ===

{{Anchor|JP}}
=== JP ===

{{Anchor|JS}}
=== JS ===

{{Anchor|JZ}}
=== JZ/JE ===

{{Anchor|LAHF}}
=== LAHF ===

{{Anchor|LDS}}
=== LDS ===

{{Anchor|LEA}}
=== LEA ===

{{Anchor|LEAVE}}
=== LEAVE ===

{{Anchor|LES}}
=== LES ===

{{Anchor|LOCK}}
=== LOCK ===

{{Anchor|LODSB}}
=== LODSB ===

{{Anchor|LODSW}}
=== LODSW ===

{{Anchor|LOOP}}
=== LOOP ===

{{Anchor|LOOPE}}
=== LOOPE ===

{{Anchor|LOOPNE}}
=== LOOPNE ===

{{Anchor|MOV}}
=== MOV ===

{{Anchor|MOVSB}}
=== MOVSB ===

{{Anchor|MOVSW}}
=== MOVSW ===

{{Anchor|MUL}}
=== MUL ===

{{Anchor|NEG}}
=== NEG ===

{{Anchor|NOP}}
=== NOP ===

{{Anchor|NOT}}
=== NOT ===

{{Anchor|OR}}
=== OR ===

{{Anchor|OUT}}
=== OUT ===

{{Anchor|OUTSB}}
=== OUTSB ===

{{Anchor|OUTSW}}
=== OUTSW ===

{{Anchor|POLL}}
=== POLL ===

{{Anchor|POP}}
=== POP ===

{{Anchor|POPA}}
=== POPA ===

{{Anchor|POPF}}
=== POPF ===

{{Anchor|PUSH}}
=== PUSH ===

{{Anchor|PUSHA}}
=== PUSHA ===

{{Anchor|PUSHF}}
=== PUSHF ===

{{Anchor|RCL}}
=== RCL ===

{{Anchor|RCR}}
=== RCR ===

{{Anchor|REP}}
=== REP/REPE/REPZ ===

{{Anchor|REPNE}}
=== REPNE/REPNZ ===

{{Anchor|RET}}
=== RET ===

{{Anchor|RETF}}
=== RETF ===

{{Anchor|ROL}}
=== ROL ===

{{Anchor|ROR}}
=== ROR ===

{{Anchor|SAHF}}
=== SAHF ===

{{Anchor|SAR}}
=== SAR ===

{{Anchor|SBB}}
=== SBB ===

{{Anchor|SCASB}}
=== SCASB ===

{{Anchor|SCASW}}
=== SCASW ===

{{Anchor|SHL}}
=== SHL ===

{{Anchor|SHR}}
=== SHR ===

{{Anchor|SS}}
=== SS ===

{{Anchor|STC}}
=== STC ===

{{Anchor|STD}}
=== STD ===

{{Anchor|STI}}
=== STI ===

{{Anchor|STOSB}}
=== STOSB ===

{{Anchor|STOSW}}
=== STOSW ===

{{Anchor|SUB}}
=== SUB ===

{{Anchor|TEST}}
=== TEST ===

{{Anchor|XCHG}}
=== XCHG ===

{{Anchor|XLAT}}
=== XLAT ===

{{Anchor|XOR}}
=== XOR ===</text>
    <sha1>2320bb20f029f40380308beea1159d595414d86c</sha1>
  </revision>
  <revision>
    <id>434</id>
    <parentid>433</parentid>
    <timestamp>2024-12-26T14:34:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Official instructions by type */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10283" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| colspan="10" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |

|}

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{{Anchor|AAD}}
=== AAD ===

{{Anchor|AAM}}
=== AAM ===

{{Anchor|AAS}}
=== AAS ===

{{Anchor|ADC}}
=== ADC ===

{{Anchor|ADD}}
=== ADD ===

{{Anchor|AND}}
=== AND ===

{{Anchor|BOUND}}
=== BOUND ===

{{Anchor|CALL}}
=== CALL ===

{{Anchor|CBW}}
=== CBW ===

{{Anchor|CLC}}
=== CLC ===

{{Anchor|CLD}}
=== CLD ===

{{Anchor|CLI}}
=== CLI ===

{{Anchor|CMC}}
=== CMC ===

{{Anchor|CMP}}
=== CMP ===

{{Anchor|CMPSB}}
=== CMPSB ===

{{Anchor|CMPSW}}
=== CMPSW ===

{{Anchor|CS}}
=== CS ===

{{Anchor|CWD}}
=== CWD ===

{{Anchor|DAA}}
=== DAA ===

{{Anchor|DAS}}
=== DAS ===

{{Anchor|DEC}}
=== DEC ===

{{Anchor|DIV}}
=== DIV ===

{{Anchor|DS}}
=== DS ===

{{Anchor|ENTER}}
=== ENTER ===

{{Anchor|ES}}
=== ES ===

{{Anchor|HLT}}
=== HLT ===

{{Anchor|IDIV}}
=== IDIV ===

{{Anchor|IMUL}}
=== IMUL ===

{{Anchor|IN}}
=== IN ===

{{Anchor|INC}}
=== INC ===

{{Anchor|INSB}}
=== INSB ===

{{Anchor|INSW}}
=== INSW ===

{{Anchor|INT}}
=== INT ===

{{Anchor|INTO}}
=== INTO ===

{{Anchor|IRET}}
=== IRET ===

{{Anchor|JA}}
=== JA ===

{{Anchor|JBE}}
=== JBE ===

{{Anchor|JC}}
=== JC/JB ===

{{Anchor|JCXZ}}
=== JCXZ ===

{{Anchor|JG}}
=== JG ===

{{Anchor|JGE}}
=== JGE ===

{{Anchor|JL}}
=== JL ===

{{Anchor|JLE}}
=== JLE ===

{{Anchor|JMP}}
=== JMP ===

{{Anchor|JNC}}
=== JNC/JAE ===

{{Anchor|JNO}}
=== JNO ===

{{Anchor|JNP}}
=== JNP ===

{{Anchor|JNS}}
=== JNS ===

{{Anchor|JNZ}}
=== JNZ/JNE ===

{{Anchor|JO}}
=== JO ===

{{Anchor|JP}}
=== JP ===

{{Anchor|JS}}
=== JS ===

{{Anchor|JZ}}
=== JZ/JE ===

{{Anchor|LAHF}}
=== LAHF ===

{{Anchor|LDS}}
=== LDS ===

{{Anchor|LEA}}
=== LEA ===

{{Anchor|LEAVE}}
=== LEAVE ===

{{Anchor|LES}}
=== LES ===

{{Anchor|LOCK}}
=== LOCK ===

{{Anchor|LODSB}}
=== LODSB ===

{{Anchor|LODSW}}
=== LODSW ===

{{Anchor|LOOP}}
=== LOOP ===

{{Anchor|LOOPE}}
=== LOOPE ===

{{Anchor|LOOPNE}}
=== LOOPNE ===

{{Anchor|MOV}}
=== MOV ===

{{Anchor|MOVSB}}
=== MOVSB ===

{{Anchor|MOVSW}}
=== MOVSW ===

{{Anchor|MUL}}
=== MUL ===

{{Anchor|NEG}}
=== NEG ===

{{Anchor|NOP}}
=== NOP ===

{{Anchor|NOT}}
=== NOT ===

{{Anchor|OR}}
=== OR ===

{{Anchor|OUT}}
=== OUT ===

{{Anchor|OUTSB}}
=== OUTSB ===

{{Anchor|OUTSW}}
=== OUTSW ===

{{Anchor|POLL}}
=== POLL ===

{{Anchor|POP}}
=== POP ===

{{Anchor|POPA}}
=== POPA ===

{{Anchor|POPF}}
=== POPF ===

{{Anchor|PUSH}}
=== PUSH ===

{{Anchor|PUSHA}}
=== PUSHA ===

{{Anchor|PUSHF}}
=== PUSHF ===

{{Anchor|RCL}}
=== RCL ===

{{Anchor|RCR}}
=== RCR ===

{{Anchor|REP}}
=== REP/REPE/REPZ ===

{{Anchor|REPNE}}
=== REPNE/REPNZ ===

{{Anchor|RET}}
=== RET ===

{{Anchor|RETF}}
=== RETF ===

{{Anchor|ROL}}
=== ROL ===

{{Anchor|ROR}}
=== ROR ===

{{Anchor|SAHF}}
=== SAHF ===

{{Anchor|SAR}}
=== SAR ===

{{Anchor|SBB}}
=== SBB ===

{{Anchor|SCASB}}
=== SCASB ===

{{Anchor|SCASW}}
=== SCASW ===

{{Anchor|SHL}}
=== SHL ===

{{Anchor|SHR}}
=== SHR ===

{{Anchor|SS}}
=== SS ===

{{Anchor|STC}}
=== STC ===

{{Anchor|STD}}
=== STD ===

{{Anchor|STI}}
=== STI ===

{{Anchor|STOSB}}
=== STOSB ===

{{Anchor|STOSW}}
=== STOSW ===

{{Anchor|SUB}}
=== SUB ===

{{Anchor|TEST}}
=== TEST ===

{{Anchor|XCHG}}
=== XCHG ===

{{Anchor|XLAT}}
=== XLAT ===

{{Anchor|XOR}}
=== XOR ===</text>
    <sha1>0d7210c40961af4989a76a932abc106762294306</sha1>
  </revision>
  <revision>
    <id>435</id>
    <parentid>434</parentid>
    <timestamp>2024-12-26T14:45:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add NEC opcode translation table, line separators</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15073" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}
== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |

|}

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

----
{{Anchor|AND}}
=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>a3343a9e168cbacc3a5662720878ece8b8542393</sha1>
  </revision>
  <revision>
    <id>436</id>
    <parentid>435</parentid>
    <timestamp>2024-12-26T17:47:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add modr/m byte section</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="15122" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

----
{{Anchor|AND}}
=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>8d80146217376a4dda1effc28ad7e99c9ce72643</sha1>
  </revision>
  <revision>
    <id>437</id>
    <parentid>436</parentid>
    <timestamp>2024-12-26T18:02:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* ModR/M byte */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16827" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte, marked as &lt;tt&gt;oorrrmmm&lt;/tt&gt;, is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that ''oo'' = &lt;tt&gt;00&lt;/tt&gt;, ''mmm'' = &lt;tt&gt;110&lt;/tt&gt; is a special case.

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

----
{{Anchor|AND}}
=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>611d31a260470ad4b3d258e064be92cdb6528104</sha1>
  </revision>
  <revision>
    <id>438</id>
    <parentid>437</parentid>
    <timestamp>2024-12-26T18:04:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* ModR/M byte */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16995" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;rm&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

----
{{Anchor|AND}}
=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>886c8cba11ea7da29c50b9214b80813ff149bee8</sha1>
  </revision>
  <revision>
    <id>439</id>
    <parentid>438</parentid>
    <timestamp>2024-12-26T18:09:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* ModR/M byte */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="16995" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

----
{{Anchor|AND}}
=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>45480ee9df666f29bd83589225959eb52f35c630</sha1>
  </revision>
  <revision>
    <id>440</id>
    <parentid>439</parentid>
    <timestamp>2024-12-26T18:18:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* ADD */ first attempt at an instruction encoding table</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18328" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>b233e4a3c2aaa70239e917528e82534b0ce5dc08</sha1>
  </revision>
  <revision>
    <id>441</id>
    <parentid>440</parentid>
    <timestamp>2024-12-26T18:18:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* ADD */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="18338" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

----
{{Anchor|ADC}}
=== ADC ===

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}

=== AND ===

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

----
{{Anchor|DAS}}
=== DAS ===

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

----
{{Anchor|JBE}}
=== JBE ===

----
{{Anchor|JC}}
=== JC/JB ===

----
{{Anchor|JCXZ}}
=== JCXZ ===

----
{{Anchor|JG}}
=== JG ===

----
{{Anchor|JGE}}
=== JGE ===

----
{{Anchor|JL}}
=== JL ===

----
{{Anchor|JLE}}
=== JLE ===

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

----
{{Anchor|JNO}}
=== JNO ===

----
{{Anchor|JNP}}
=== JNP ===

----
{{Anchor|JNS}}
=== JNS ===

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

----
{{Anchor|JO}}
=== JO ===

----
{{Anchor|JP}}
=== JP ===

----
{{Anchor|JS}}
=== JS ===

----
{{Anchor|JZ}}
=== JZ/JE ===

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>9cfb48a075c6ee00f49d9543f0692fee7bdb5fa2</sha1>
  </revision>
  <revision>
    <id>443</id>
    <parentid>441</parentid>
    <timestamp>2024-12-26T18:39:03Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Official instructions */ progress on opcode tables</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="24878" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

----
{{Anchor|CALL}}
=== CALL ===

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

----
{{Anchor|CLD}}
=== CLD ===

----
{{Anchor|CLI}}
=== CLI ===

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

----
{{Anchor|INTO}}
=== INTO ===

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

----
{{Anchor|STD}}
=== STD ===

----
{{Anchor|STI}}
=== STI ===

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>020738bcf615b6cbe04b46cc88ea156fbb1138f8</sha1>
  </revision>
  <revision>
    <id>445</id>
    <parentid>443</parentid>
    <timestamp>2024-12-26T19:01:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Official instructions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="27684" xml:space="preserve">__NOTOC__
{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>1bfea947b22ee331cf26f9b88fff2c4f4064edf9</sha1>
  </revision>
  <revision>
    <id>446</id>
    <parentid>445</parentid>
    <timestamp>2024-12-26T19:33:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="27729" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

----
{{Anchor|AAM}}
=== AAM ===

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

----
{{Anchor|CMP}}
=== CMP ===

----
{{Anchor|CMPSB}}
=== CMPSB ===

----
{{Anchor|CMPSW}}
=== CMPSW ===

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

----
{{Anchor|SCASW}}
=== SCASW ===

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>80d7ac67480ef1d9f565e4bd04fff27da73e7d8b</sha1>
  </revision>
  <revision>
    <id>447</id>
    <parentid>446</parentid>
    <timestamp>2024-12-26T19:40:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="30501" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location with an optional signed 8-bit (disp8) or 16-bit (disp16) displacement or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>6b9ca4a6b3d227a2789d2acdaaf0d90916cda1a7</sha1>
  </revision>
  <revision>
    <id>448</id>
    <parentid>447</parentid>
    <timestamp>2024-12-26T19:50:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* ModR/M byte */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="30538" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case. Displacements are either 8-bit or 16-bit signed values and they always immediately follow the ModR/M byte.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>e69fd666fb461ec138e14002d553e83e13ae59a9</sha1>
  </revision>
  <revision>
    <id>449</id>
    <parentid>448</parentid>
    <timestamp>2024-12-26T19:50:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Instruction encoding */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="30555" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case. Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>3d169338085fef12c5d7fdaf56da29438f35d13b</sha1>
  </revision>
  <revision>
    <id>450</id>
    <parentid>449</parentid>
    <timestamp>2024-12-26T19:51:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Instruction encoding */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="30621" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

----
{{Anchor|DIV}}
=== DIV ===

----
{{Anchor|DS}}
=== DS ===

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

----
{{Anchor|HLT}}
=== HLT ===

----
{{Anchor|IDIV}}
=== IDIV ===

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

----
{{Anchor|INC}}
=== INC ===

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

----
{{Anchor|LOOPE}}
=== LOOPE ===

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>d45320bccce96a0db6298a646be828f1b68bb3e7</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>NEC V30MZ</title>
  <ns>0</ns>
  <id>39</id>
  <revision>
    <id>442</id>
    <parentid>345</parentid>
    <timestamp>2024-12-26T18:19:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sections */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1031" xml:space="preserve">The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

== Format ==

The NEC V30MZ datasheet provides distinct names for opcodes, flags and registers, which the wiki refers to as ''NEC names''. As all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what is used throughout. For registers and flags, distinct NEC names are presented in the following format: Intel&lt;sup&gt;NEC&lt;/sup&gt;.

== Sections ==

* [[NEC V30MZ registers]]
* [[NEC V30MZ flags]]
* [[NEC V30MZ instruction set]]
** [[NEC V30MZ undocumented instructions]]
* [[NEC V30MZ interrupts]]

== Links ==

* [https://www.ardent-tool.com/CPU/docs/NEC/V20-V30/v30mz.pdf NEC V30MZ datasheet]
* [http://perfectkiosk.net/stsws.html#cpu STSWS - CPU - V30MZ/V Series Microprocessor]</text>
    <sha1>c7b9ca49e4fc86efa763cf95fd249fdf5ef26c6d</sha1>
  </revision>
</page>
<page arvcontinue="20241207214819|401">
  <title>NEC V30MZ undocumented instructions</title>
  <ns>0</ns>
  <id>69</id>
  <revision>
    <id>444</id>
    <timestamp>2024-12-26T18:42:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "TODO. For now, see https://github.com/FluBBaOfWard/WSCpuTest/blob/main/README.md"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="80" xml:space="preserve">TODO. For now, see https://github.com/FluBBaOfWard/WSCpuTest/blob/main/README.md</text>
    <sha1>c1b28dfebfd37b9656e454ef198ecb23955ffe58</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>WonderWitch/FreyaBIOS/System</title>
  <ns>0</ns>
  <id>66</id>
  <revision>
    <id>451</id>
    <parentid>430</parentid>
    <timestamp>2024-12-27T19:02:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document some sleep functions</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4354" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

Hook the given interrupt handler and enable the interrupt.

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

Unhook the given interrupt handler and disable the interrupt.

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

* AH = $04

Puts the system to sleep; the LCD panel is disabled and the CPU is halted.

TODO: Document precise wake up conditions (it's definitely the key pattern - is an interrupt sufficient?).

=== INT $17/AH=$05 - sys_set_sleep_time ===

* AH = $05
* BL = Sleep time, in minutes

=== INT $17/AH=$06 - sys_get_sleep_time ===

* AH = $06

Return:

* AL = Sleep time, in minutes

=== INT $17/AH=$07 - sys_set_awake_key ===

* AH = $07
* BX = Key pattern to wake up from sleep.

If the key pattern is set to $0000, pressing any key will wake up the console.

=== INT $17/AH=$08 - sys_get_awake_key ===

* AH = $08

Return:

* AX = Key pattern to wake up from sleep.

=== INT $17/AH=$09 - sys_set_keepalive_int ===

* AH = $09
* BL = [[Interrupts|Interrupt mask]]

Set the interrupt mask to be applied while the console is sleeping.

By default, this is set to $02 - that is, only the key interrupt is listened to during sleep.

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

* BX = ?
* CX = bytes to allocate

Return:

* AX = near pointer to allocated IRAM block

Pointers to IRAM blocks are always segment (16 byte)-aligned.

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

 15      bit       0
 ---- ---- ---- ----
 MMMM mmmm pppp pppp
 |||| |||| |||| ||||
 |||| |||| ++++-++++- Patch version (0-127)
 |||| ++++----------- Minor version (0-15)
 ++++---------------- Major version (0-15)

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $15

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>3c86aacb392bba5c43d3e9d8c274de579ce0a661</sha1>
  </revision>
  <revision>
    <id>472</id>
    <parentid>451</parentid>
    <timestamp>2024-12-29T09:46:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $17/AH=$0A - sys_get_ownerinfo */ document return codes</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4440" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

Hook the given interrupt handler and enable the interrupt.

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

Unhook the given interrupt handler and disable the interrupt.

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

* AH = $04

Puts the system to sleep; the LCD panel is disabled and the CPU is halted.

TODO: Document precise wake up conditions (it's definitely the key pattern - is an interrupt sufficient?).

=== INT $17/AH=$05 - sys_set_sleep_time ===

* AH = $05
* BL = Sleep time, in minutes

=== INT $17/AH=$06 - sys_get_sleep_time ===

* AH = $06

Return:

* AL = Sleep time, in minutes

=== INT $17/AH=$07 - sys_set_awake_key ===

* AH = $07
* BX = Key pattern to wake up from sleep.

If the key pattern is set to $0000, pressing any key will wake up the console.

=== INT $17/AH=$08 - sys_get_awake_key ===

* AH = $08

Return:

* AX = Key pattern to wake up from sleep.

=== INT $17/AH=$09 - sys_set_keepalive_int ===

* AH = $09
* BL = [[Interrupts|Interrupt mask]]

Set the interrupt mask to be applied while the console is sleeping.

By default, this is set to $02 - that is, only the key interrupt is listened to during sleep.

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Return:

* AX:
  * $0000 - Success
  * $8101 - Internal EEPROM communication timeout

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

* BX = ?
* CX = bytes to allocate

Return:

* AX = near pointer to allocated IRAM block

Pointers to IRAM blocks are always segment (16 byte)-aligned.

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

 15      bit       0
 ---- ---- ---- ----
 MMMM mmmm pppp pppp
 |||| |||| |||| ||||
 |||| |||| ++++-++++- Patch version (0-127)
 |||| ++++----------- Minor version (0-15)
 ++++---------------- Major version (0-15)

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $15

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>80cfcd9695792ba5ee23bb435747339a076d4bb8</sha1>
  </revision>
  <revision>
    <id>473</id>
    <parentid>472</parentid>
    <timestamp>2024-12-29T09:46:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* INT $17/AH=$0A - sys_get_ownerinfo */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4438" xml:space="preserve">The System interrupt provides assorted system-related functionality.

== Interrupts ==

=== INT $17/AH=$00 - sys_interrupt_set_hook ===

* AH = $00
* AL = Interrupt index
* DS:BX = Pointer to new vector (read from)
* DS:DX = Pointer to old vector (written to)

Hook the given interrupt handler and enable the interrupt.

=== INT $17/AH=$01 - sys_interrupt_reset_hook ===

* AH = $01
* AL = Interrupt index
* DS:BX = Pointer to old vector (read from)

Unhook the given interrupt handler and disable the interrupt.

=== INT $17/AH=$02 - sys_wait ===

* AH = $02
* CX = Frames to wait

=== INT $17/AH=$03 - sys_get_tick_count ===

* AH = $03

Return:

* DX:AX = Number of frames since system start

=== INT $17/AH=$04 - sys_sleep ===

* AH = $04

Puts the system to sleep; the LCD panel is disabled and the CPU is halted.

TODO: Document precise wake up conditions (it's definitely the key pattern - is an interrupt sufficient?).

=== INT $17/AH=$05 - sys_set_sleep_time ===

* AH = $05
* BL = Sleep time, in minutes

=== INT $17/AH=$06 - sys_get_sleep_time ===

* AH = $06

Return:

* AL = Sleep time, in minutes

=== INT $17/AH=$07 - sys_set_awake_key ===

* AH = $07
* BX = Key pattern to wake up from sleep.

If the key pattern is set to $0000, pressing any key will wake up the console.

=== INT $17/AH=$08 - sys_get_awake_key ===

* AH = $08

Return:

* AX = Key pattern to wake up from sleep.

=== INT $17/AH=$09 - sys_set_keepalive_int ===

* AH = $09
* BL = [[Interrupts|Interrupt mask]]

Set the interrupt mask to be applied while the console is sleeping.

By default, this is set to $02 - that is, only the key interrupt is listened to during sleep.

=== INT $17/AH=$0A - sys_get_ownerinfo ===

* AH = $0A
* DS:DX = Output buffer
* CX = Output buffer size, in bytes

Return:

* AX:
** $0000 - Success
** $8101 - Internal EEPROM communication timeout

Errata:

* The FreyaBIOS implementation only works correctly in the "mono" mode. An alternate implementation that supports "color" mode is provided as part of libwwc.

=== INT $17/AH=$0B - sys_suspend ===

* AH = $0B
* AL = Suspend slot (see below)
* DS:BX = Pointer to I/O resume table (see below)

Return:

* AX = 0 if suspend successful, 1 if returning from suspend (via sys_resume).

Makes a copy of the execution state (IRAM, I/O ports, stack) to be restored via sys_resume (see below).

==== Suspend/resume structure ====

This structure is stored in SRAM block 3, offset &lt;code&gt;$7E00&lt;/code&gt; (slot 1) and &lt;code&gt;$BF00&lt;/code&gt; (slot 0).

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $0000 || 16384 || Copy of RAM area &lt;code&gt;$0000&lt;/code&gt; - &lt;code&gt;$3FFF&lt;/code&gt;
|-
| $4000 || 4 || Far pointer to I/O resume table (DS:BX), plus 1
|-
| $4004 || 224 || Copy of IO ports &lt;code&gt;$00&lt;/code&gt; - &lt;code&gt;$DF&lt;/code&gt;
|-
| $40E4 || 2 || Value of CX?
|-
| $40E6 || 2 || Value of SP?
|-
| $40E8 || 2 || Value of SS?
|}

In addition, these SRAM block 3 locations are used:

{| class="wikitable"
|-
! Offset !! Contents
|-
| $FFEE || Resumable status for slot 0 (bit 7 = resumable?, bit ?..0 = ID)
|-
| $FFEF || Resumable status for slot 1 (bit 7 = resumable?, bit ?..0 = ID)
|}

==== I/O resume table ====

{| class="wikitable"
|-
! Offset !! Size !! Contents
|-
| $00 || 2 || 'IO'
|-
| $02 || 224 || Resume configuration for each I/O port
|}

=== INT $17/AH=$0C - sys_resume ===

* AH = $0C
* AL = Suspend slot?

Resumes execution from an existing suspend slot. Returns to where ''sys_suspend'' was last called, but with a different return value.

=== INT $17/AH=$0D - sys_set_remote ===

=== INT $17/AH=$0E - sys_get_remote ===

=== INT $17/AH=$0F - sys_alloc_iram ===

* BX = ?
* CX = bytes to allocate

Return:

* AX = near pointer to allocated IRAM block

Pointers to IRAM blocks are always segment (16 byte)-aligned.

=== INT $17/AH=$10 - sys_free_iram ===

=== INT $17/AH=$11 - sys_get_my_iram ===

=== INT $17/AH=$12 - sys_get_version ===

* AH = $12

Return:

* AX = BIOS version

 15      bit       0
 ---- ---- ---- ----
 MMMM mmmm pppp pppp
 |||| |||| |||| ||||
 |||| |||| ++++-++++- Patch version (0-127)
 |||| ++++----------- Minor version (0-15)
 ++++---------------- Major version (0-15)

=== INT $17/AH=$13 - sys_swap ===

=== INT $17/AH=$14 - sys_set_resume ===

* AH = $14
* BL = Resumable flag for slot ?
* BH = Resumable flag for slot ?

=== INT $17/AH=$15 - sys_get_resume ===

* AH = $15

Return:

* AL = Resumable flag for slot ?
* AH = Resumable flag for slot ?</text>
    <sha1>afbffc7acd1077ede44ad8091d65bbf8edddb8b2</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>NEC V30MZ instruction set</title>
  <ns>0</ns>
  <id>68</id>
  <revision>
    <id>452</id>
    <parentid>450</parentid>
    <timestamp>2024-12-27T21:27:12Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="34120" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>0fc3f709d1e009091103c2ec39eebc30be5b11e9</sha1>
  </revision>
  <revision>
    <id>453</id>
    <parentid>452</parentid>
    <timestamp>2024-12-27T21:28:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Official instructions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="34581" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>3486fbd16e89d919b14b7eb2964f8bab160e71ef</sha1>
  </revision>
  <revision>
    <id>454</id>
    <parentid>453</parentid>
    <timestamp>2024-12-27T21:31:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Official instructions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="35131" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
=== INSB ===

----
{{Anchor|INSW}}
=== INSW ===

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
=== OUTSB ===

----
{{Anchor|OUTSW}}
=== OUTSW ===

----
{{Anchor|POLL}}
=== POLL ===

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

----</text>
    <sha1>cd5169d8c63f06b0060b0662b1ae05573762a5e8</sha1>
  </revision>
  <revision>
    <id>455</id>
    <parentid>454</parentid>
    <timestamp>2024-12-27T21:50:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="35869" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
=== CMPSB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CMPSW}}
=== CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
=== LODSB ===

----
{{Anchor|LODSW}}
=== LODSW ===

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
=== MOVSB ===

----
{{Anchor|MOVSW}}
=== MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
=== SCASB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SCASW}}
=== SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
=== STOSB ===

----
{{Anchor|STOSW}}
=== STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

----

== Notes ==

&lt;references /&gt;</text>
    <sha1>d237c1644321c82f0a1c37bdf9c9f961d4087d34</sha1>
  </revision>
  <revision>
    <id>456</id>
    <parentid>455</parentid>
    <timestamp>2024-12-27T21:53:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="36304" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}


----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

----

== Notes ==

&lt;references /&gt;</text>
    <sha1>9c0d934326ecc4a44b841f82395fff965d16fdc7</sha1>
  </revision>
  <revision>
    <id>457</id>
    <parentid>456</parentid>
    <timestamp>2024-12-27T22:24:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="43619" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----

== Notes ==

&lt;references /&gt;</text>
    <sha1>e49970d2ec9476f48b0e8cc43beb5062e7009131</sha1>
  </revision>
  <revision>
    <id>458</id>
    <parentid>457</parentid>
    <timestamp>2024-12-27T22:24:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* MOV */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="43618" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2+ || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2+ || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2+ || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2+ || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}

=== MOVSB/MOVSW ===

----
{{Anchor|MUL}}
=== MUL ===

----
{{Anchor|NEG}}
=== NEG ===

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

----
{{Anchor|POPA}}
=== POPA ===

----
{{Anchor|POPF}}
=== POPF ===

----
{{Anchor|PUSH}}
=== PUSH ===

----
{{Anchor|PUSHA}}
=== PUSHA ===

----
{{Anchor|PUSHF}}
=== PUSHF ===

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

----
{{Anchor|RETF}}
=== RETF ===

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----

== Notes ==

&lt;references /&gt;</text>
    <sha1>7937618c29a2b8f55f9b72c0eda245dba2fba2f7</sha1>
  </revision>
  <revision>
    <id>459</id>
    <parentid>458</parentid>
    <timestamp>2024-12-27T22:41:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="48241" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

----
{{Anchor|RCR}}
=== RCR ===

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

----
{{Anchor|ROR}}
=== ROR ===

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

----
{{Anchor|SHR}}
=== SHR ===

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----

== Notes ==

&lt;references /&gt;</text>
    <sha1>cc3a0f22b8f0018bc76f531c3eb0765f5274351f</sha1>
  </revision>
  <revision>
    <id>460</id>
    <parentid>459</parentid>
    <timestamp>2024-12-27T23:32:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="56664" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010rm&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010rm&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010rm&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011rm&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011rm&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011rm&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000rm&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000rm&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000rm&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}
=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001rm&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001rm&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001rm&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111rm&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111rm&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111rm&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100rm&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100rm&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100rm&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101rm&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101rm&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101rm&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----

== Notes ==

&lt;references /&gt;</text>
    <sha1>c5e8333b5622ded24c20de76d80ade53e83e9a7f</sha1>
  </revision>
  <revision>
    <id>461</id>
    <parentid>460</parentid>
    <timestamp>2024-12-27T23:34:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="56658" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010rm&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010rm&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010rm&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011rm&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011rm&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011rm&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000rm&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000rm&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000rm&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}
=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001rm&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001rm&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001rm&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111rm&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111rm&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111rm&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100rm&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100rm&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100rm&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101rm&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101rm&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101rm&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>587399df505ed661498a0898b5c38f0b73e748ac</sha1>
  </revision>
  <revision>
    <id>462</id>
    <parentid>461</parentid>
    <timestamp>2024-12-27T23:35:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* ROL */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="56660" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010rm&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010rm&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010rm&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011rm&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011rm&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011rm&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000rm&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000rm&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000rm&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001rm&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001rm&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001rm&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111rm&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111rm&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111rm&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100rm&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100rm&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100rm&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101rm&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101rm&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101rm&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101rm&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>4b6cddd836171a84484a3ab447af1334f252b21e</sha1>
  </revision>
  <revision>
    <id>463</id>
    <parentid>462</parentid>
    <timestamp>2024-12-27T23:37:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="56940" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

----
{{Anchor|NOT}}
=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>dc4c05e02503ff017068fecc786f0ce947c5bf1b</sha1>
  </revision>
  <revision>
    <id>464</id>
    <parentid>463</parentid>
    <timestamp>2024-12-27T23:37:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* NOP */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57095" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>97f42dde991d8c6967d6c5b7cbea6b66c373d734</sha1>
  </revision>
  <revision>
    <id>468</id>
    <parentid>464</parentid>
    <timestamp>2024-12-28T11:02:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Official instructions */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57736" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 9
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|ROL}}
=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>e1dfb756a5671ab1b749ccc85242ebba19bdbd43</sha1>
  </revision>
  <revision>
    <id>481</id>
    <parentid>468</parentid>
    <timestamp>2024-12-31T10:12:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* RETF */ fix cycle counts</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57737" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the ''Register'' field also refers to a register; it is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt;.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>06b6ef3f57b2d7965d19b924589b279cc88741f6</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>Accessory port pinout</title>
  <ns>0</ns>
  <id>43</id>
  <revision>
    <id>465</id>
    <parentid>188</parentid>
    <timestamp>2024-12-28T07:07:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* HDMI connector mapping */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2031" xml:space="preserve">The WonderSwan accessory (EXT) port provides an [[UART]] serial port and I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; Accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Luckily, it turns out that male HDMI connectors are somewhat electrically compatible with male EXT port connectors. This allows repurposing them as a replacement for a female EXT port connector.

* Note that using an HDMI plug may cause increased wear on the connector.
* In addition, an HDMI plug lacks the plastic sleeve which the original EXT port connector has, which leads to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Due to the lack of availability of new EXT port connectors, this is a popular solution among DIY users and lower-end aftermarket accessories.

HDMI pins connect to EXT port pins as follows:

{| class="wikitable"
|-
! EXT !! HDMI
|-
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>00bc2daa0684910a2004fe9635f745bebc27bd24</sha1>
  </revision>
  <revision>
    <id>470</id>
    <parentid>465</parentid>
    <timestamp>2024-12-28T15:07:54Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2122" xml:space="preserve">The WonderSwan accessory (EXT) port provides:

* 3.3V power delivery to the peripheral,
* an [[UART]] serial port,
* an I&lt;sup&gt;2&lt;/sup&gt;S digital audio output.

Note that the UART uses inverted polarity.

== Pinout ==

(Female 8-pin port on peripheral)

&lt;pre&gt;
       MISO_          _MOSI
            \        /
      +3V_   \      /   _GND
    ______\ __\ __ /__ /______
   |      04__03__02__01      |
   |   __|""  ""  ""  ""|__   |
   |  |__                __|  |
   '.    |..__..__..__..|    .'
     \____05__06__07__08____/
         _/   /    \   \_
     BCLK    /      \    /HDPN
           _/        \_
       LRCK            SDAT
&lt;/pre&gt;


{| class="wikitable"
|-
! Pin !! Group !! Description
|-
| 01 (GND)
| Power
| Ground
|-
| 02 (MOSI)
| rowspan="2" | [[UART]]
| WonderSwan -&gt; Accessory
|-
| 03 (MISO)
| Accessory -&gt; WonderSwan
|-
| 04 (+3V)
| Power
| 3.3 volt?
|-
| 05 (BCLK)
| rowspan="4" | I&lt;sup&gt;2&lt;/sup&gt;S
| Bit clock
|-
| 06 (LRCK)
| Channel clock
|-
| 07 (SDAT)
| Bit data
|-
| 08 (/HDPN)
| Headphone detect
|}

== HDMI connector mapping ==

Luckily, it turns out that male HDMI connectors are somewhat electrically compatible with male EXT port connectors. This allows repurposing them as a replacement for a female EXT port connector.

* Note that using an HDMI plug may cause increased wear on the connector.
* In addition, an HDMI plug lacks the plastic sleeve which the original EXT port connector has, which leads to a loose connection.
** One solution is to 3D-print a sleeve to improve connection.
** Another solution is to include some type of LED/indicator in order to validate proper connection.

Due to the lack of availability of new EXT port connectors, this is a popular solution among DIY users and lower-end aftermarket accessories.

HDMI pins connect to EXT port pins as follows:

{| class="wikitable"
|-
! EXT !! HDMI
|-
| 01 (GND)
| 15 (SCL)
|-
| 02 (MOSI)
| 11 (TMDS Clock Shield)
|-
| 03 (MISO)
| 7 (TMDS Data 0 +)
|-
| 04 (+3V)
| 3 (TMDS Data 2 -)
|-
| 05 (BCLK)
| 4 (TMDS Data 1 +)
|-
| 06 (LRCK)
| 8 (TMDS Data 0 Shield)
|-
| 07 (SDAT)
| 12 (TMDS Clock -)
|-
| 08 (/HDPN)
| 16 (SDA)
|}</text>
    <sha1>cfa9a96448909d312cac4b84db0a7e5a5400c78a</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>NEC V30MZ flags</title>
  <ns>0</ns>
  <id>56</id>
  <revision>
    <id>466</id>
    <parentid>342</parentid>
    <timestamp>2024-12-28T10:59:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Status flags */ add anchors</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2410" xml:space="preserve">
= NEC V30MZ flags =

== Layout ==

The V30MZ processor features a 16-bit flag register:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (Z)
  |    ||||  +--------- Sign (S)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

== Status flags ==

The following flags are typically modified by instructions:

{{Anchor|CF}}
=== Carry ===

Stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.

{{Anchor|PF}}
=== Parity ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.

{{Anchor|AF}}
=== Auxillary Carry ===

Stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.

{{Anchor|ZF}}
=== Zero ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.

{{Anchor|SF}}
=== Sign ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.

{{Anchor|OF}}
=== Overflow ===

Set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

== Control flags ==

The following flags are typically modified by the developer:

=== Single step ===

If set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.

Alternatively referred to as the ''trap flag''.

=== Interrupt enable ===

If set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.

=== Direction ===

If set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.

=== Mode ===

This flag does nothing on the NEC V30MZ. It was used to implement 8080 emulation mode in other V20/V30-family chips, but this functionality has been removed in the V30MZ.</text>
    <sha1>838eab05e6fde77eb5a0d3c347b3af61bc58604d</sha1>
  </revision>
  <revision>
    <id>467</id>
    <parentid>466</parentid>
    <timestamp>2024-12-28T10:59:55Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>add remaining anchors</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2492" xml:space="preserve">
= NEC V30MZ flags =

== Layout ==

The V30MZ processor features a 16-bit flag register:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (ZF&lt;sup&gt;Z&lt;/sup&gt;)
  |    ||||  +--------- Sign (SF&lt;sup&gt;S&lt;/sup&gt;)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

== Status flags ==

The following flags are typically modified by instructions:

{{Anchor|CF}}
=== Carry ===

Stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.

{{Anchor|PF}}
=== Parity ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.

{{Anchor|AF}}
=== Auxillary Carry ===

Stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.

{{Anchor|ZF}}
=== Zero ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.

{{Anchor|SF}}
=== Sign ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.

{{Anchor|OF}}
=== Overflow ===

Set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

== Control flags ==

The following flags are typically modified by the developer:

{{Anchor|TF}}
=== Single step ===

If set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.

Alternatively referred to as the ''trap flag''.

{{Anchor|IF}}
=== Interrupt enable ===

If set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.

{{Anchor|DF}}
=== Direction ===

If set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.

{{Anchor|MD}}
=== Mode ===

This flag does nothing on the NEC V30MZ. It was used to implement 8080 emulation mode in other V20/V30-family chips, but this functionality has been removed in the V30MZ.</text>
    <sha1>8e17805122b4c7a13d0814513327918729424f4d</sha1>
  </revision>
  <revision>
    <id>469</id>
    <parentid>467</parentid>
    <timestamp>2024-12-28T11:04:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2542" xml:space="preserve">
= NEC V30MZ flags =

== Layout ==

The V30MZ processor features a 16-bit flag register:

 15  bit  8  7  bit  0
  ---- ----  ---- ----
  m111 odit  sz0a 0p1c
  |    ||||  || |  | |
  |    ||||  || |  | +- Carry (CF&lt;sup&gt;CY&lt;/sup&gt;)
  |    ||||  || |  +--- Parity (PF&lt;sup&gt;P&lt;/sup&gt;)
  |    ||||  || +------ Auxillary Carry (AF&lt;sup&gt;AC&lt;/sup&gt;)
  |    ||||  |+-------- Zero (ZF&lt;sup&gt;Z&lt;/sup&gt;)
  |    ||||  +--------- Sign (SF&lt;sup&gt;S&lt;/sup&gt;)
  |    |||+------------ Single Step&lt;sup&gt;Break&lt;/sup&gt; (TF&lt;sup&gt;BRK&lt;/sup&gt;)
  |    ||+------------- Interrupt Enable (IF&lt;sup&gt;IE&lt;/sup&gt;)
  |    |+-------------- Direction (DF&lt;sup&gt;DIR&lt;/sup&gt;)
  |    +--------------- Overflow (OF&lt;sup&gt;V&lt;/sup&gt;)
  +-------------------- Mode (MD)

== Status flags ==

The following flags are typically modified by instructions:

{{Anchor|CF}}
=== CF - Carry ===

Stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations.

{{Anchor|PF}}
=== PF - Parity ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the lower 8 bits of the result are even.

{{Anchor|AF}}
=== AF - Auxillary Carry ===

Stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.

{{Anchor|ZF}}
=== ZF - Zero ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the result is equal to zero.

{{Anchor|SF}}
=== SF - Sign ===

Set to &lt;tt&gt;1&lt;/tt&gt; if, after arithmetic and logical operations, the highest bit of the result is set.

{{Anchor|OF}}
=== OF - Overflow ===

Set to &lt;tt&gt;1&lt;/tt&gt; if an overflow occured as part of the arithmetic operation.

== Control flags ==

The following flags are typically modified by the developer:

{{Anchor|TF}}
=== TF - Single step ===

If set to &lt;tt&gt;1&lt;/tt&gt;, after every instruction, a software interrupt (vector 1) is generated.

Alternatively referred to as the ''trap flag''.

{{Anchor|IF}}
=== IF - Interrupt enable ===

If set to &lt;tt&gt;1&lt;/tt&gt;, enables maskable interrupt handling via the interrupt vector table; cleared to &lt;tt&gt;0&lt;/tt&gt; as part of interrupt handling and restored by the &lt;tt&gt;IRET&lt;/tt&gt; opcode.

{{Anchor|DF}}
=== DF - Direction ===

If set to &lt;tt&gt;1&lt;/tt&gt;, string instructions decrement pointers as part of their operation; if set to &lt;tt&gt;0&lt;/tt&gt;, the pointers are to be incremented.

{{Anchor|MD}}
=== MD - Mode ===

This flag does nothing on the NEC V30MZ. It was used to implement 8080 emulation mode in other V20/V30-family chips, but this functionality has been removed in the V30MZ.</text>
    <sha1>3edea312d6c8869b4a8146d30d48f14ee4578d23</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>Cartridge connector</title>
  <ns>0</ns>
  <id>44</id>
  <revision>
    <id>471</id>
    <parentid>332</parentid>
    <timestamp>2024-12-28T15:47:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Pinout */ oops</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4825" xml:space="preserve">== Memory access ==

Both the ROM and the SRAM chip use a standard asynchronous memory interface.

It is presumed that:

* the CPU sets the address lines before each memory access while '''/OE''' or '''/WE''' respectively are still high,
* for writes the CPU sets the data lines with the falling edge of '''/WE''' (TODO: only confirmed for I/O writes),
* for reads the CPU latches the data lines on the subsequent rising edge of '''/OE'''.

Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on [[ROM header|header]] configuration.

Note that in 16-bit mode, the output on address line '''A0''' is undetermined and should be ignored.

== Pinout ==

&lt;pre&gt;
Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--48| -- GND
... \  | -47| &lt;- CLK
... |  | -46| -&gt; /IRQ (Interrupt request)
... |  | -45| &lt;- /SEL (Cartridge select)
... |  | -44| &lt;- /WR  (Write enable)
... |  | -43| &lt;- /RD  (Read enable)
... |  | -42| &lt;- M/IO (Memory/IO)
... |  | -41| -&gt; /MBC
... |  | -40| &lt;- /RESET
... |  | -39| &lt;&gt; D13
... |  | -38| &lt;&gt; D12
... |  | -37| &lt;&gt; D11
... |  | -36| &lt;&gt; D10
... |  | -35| &lt;&gt; D9
... |  | -34| &lt;&gt; D8
... |  | -33| &lt;- CPU A16
... |  | -32| &lt;- CPU A17
... |  | -31| &lt;- CPU A18
... |  | -30| &lt;- CPU A19
... |  | -29| &lt;- CPU A3
... |  | -28| &lt;- CPU A2
... |  | -27| &lt;- CPU A1
... |  | -26| &lt;- CPU A0
... |  |--25| -- +3.3V
... |  |--24| -- +3.3V
... |  | -23| &lt;&gt; D0
... |  | -22| &lt;&gt; D1
... |  | -21| &lt;&gt; D2
... |  | -20| &lt;&gt; D3
... |  | -19| &lt;&gt; D4
... |  | -18| &lt;&gt; D5
... |  | -17| &lt;&gt; D6
... |  | -16| &lt;&gt; D7
... |  | -15| &lt;&gt; D14
... |  | -14| &lt;&gt; D15
... |  | -13| &lt;- CPU A4
... |  | -12| &lt;- CPU A5
... |  | -11| &lt;- CPU A6
... |  | -10| &lt;- CPU A7
... |  | -09| &lt;- CPU A12
... |  | -08| &lt;- CPU A14
... |  | -07| &lt;- CPU A13
... |  | -06| &lt;- CPU A8
... |  | -05| &lt;- CPU A9
... |  | -04| &lt;- CPU A11
... |  | -03| &lt;- CPU A10
____/  | -02| &lt;- CPU A15
       |--01| -- GND
_______|====|

Cartridge              Console
(label side)            (back)
&lt;/pre&gt;

== Mechanical details ==

{| class="wikitable"
|-
! Distance !! Length (in mm)
|-
| Distance pad to pad || 1.25
|-
| Left edge to first pad || 0.7
|-
| Last pad to right edge || 0.95
|-
| Bottom edge to longer pads (GND, Vcc) || 0.5
|-
| Bottom edge to shorter pads || 1
|}

== Signal descriptions ==

* '''/RESET''': Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
* '''/MBC''': Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
* '''M/IO''': Memory/IO bus selection. The cartridge bus allows both memory access (to physical addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
** When Memory/IO is '''high''', pins A0-A19 specify the 20-bit linear memory address.
** When Memory/IO is '''low''', pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
* '''/IRQ''': Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
* '''CLK''': A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.

== Timing requirements ==

The '''/OE''' or '''/WE''' signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.

TODO: Verify how using ROM/SRAM wait states affects this.

== Authentication handshake ==

Shortly after '''/RESET''' goes high, a handshake between the SoC and the cartridge is performed, in order:

* '''/MBC''' is held high. '''A0'''-'''A3''' are set to 0xA and '''A16'''-'''A19''' are set to 0x5.
* On a rising edge of '''CLK''', '''A0'''-'''A3''' are set to 0x5 and '''A16'''-'''A19''' are set to 0xA.
* The cartridge continues to hold '''/MBC''' high for three additional '''CLK''' rising edges. Note that the SoC appears to allow some variance in this number of cycles.
* For each subsequent rising edge of '''CLK''', the cartridge is expected to output the following binary sequence through its '''/MBC''' pin: &lt;code&gt;1000101000101000000111&lt;/code&gt;.
* After this is finished, '''/MBC''' is expected to stay high indefinitely.

On a successful handshake, the [[SoC]] sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.

An example public domain (CC0) VHDL implementation by trap15 is available [https://bitbucket.org/trap15/mbc-unlock here].</text>
    <sha1>d14349724e9b2bb4cc0ca4be28027c2138dc568d</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>WonderWitch/FreyaBIOS/Text</title>
  <ns>0</ns>
  <id>53</id>
  <revision>
    <id>474</id>
    <parentid>389</parentid>
    <timestamp>2024-12-29T10:07:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $13/AH=$07 - text_put_numeric */ fix text_put_numeric</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4620" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BX =
** if flag bit 7 clear:
*** BL = X position in text window
*** BH = Y position in text window
** if flag bit 7 set:
*** DS:BX = Output buffer to write to
* CL = Width of area to write number in
* CH = Flags
* DX = Number

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:SI)
&lt;/pre&gt;

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>c07329659e8de4ec29f4ee160eb252181341608c</sha1>
  </revision>
  <revision>
    <id>475</id>
    <parentid>474</parentid>
    <timestamp>2024-12-29T10:22:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $13/AH=$07 - text_put_numeric */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4939" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BX =
** if flag bit 7 clear:
*** BL = X position in text window
*** BH = Y position in text window
** if flag bit 7 set:
*** DS:BX = Output buffer to write to
* CL = Width of area to write number in
* CH = Flags
* DX = Number

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal (always pads with zeroes, aligns to right)
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left (ignores padding)
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:SI)
&lt;/pre&gt;

Errata:

- When padding a signed number with zeroes, the minus sign will be output after the zeroes; for example, calling text_put_numeric for the number &lt;tt&gt;-1234&lt;/tt&gt; with a length of 8 and those flags will print &lt;tt&gt;000-1234&lt;/tt&gt;, not &lt;tt&gt;-0001234&lt;/tt&gt;.

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>c1651be778a2c04349e92ebd3ed553e3e7852703</sha1>
  </revision>
  <revision>
    <id>476</id>
    <parentid>475</parentid>
    <timestamp>2024-12-29T10:25:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $13/AH=$07 - text_put_numeric */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4964" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BX =
** if flag bit 7 clear:
*** BL = X position in text window
*** BH = Y position in text window
** if flag bit 7 set:
*** DS:BX = Output buffer to write to
* CL = Width of area to write number in
* CH = Flags
* DX = Number

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal (always pads with zeroes, aligns to right, assumes unsigned number)
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left (ignores padding)
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:SI)
&lt;/pre&gt;

Errata:

- When padding a signed number with zeroes, the minus sign will be output after the zeroes; for example, calling text_put_numeric for the number &lt;tt&gt;-1234&lt;/tt&gt; with a length of 8 and those flags will print &lt;tt&gt;000-1234&lt;/tt&gt;, not &lt;tt&gt;-0001234&lt;/tt&gt;.

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>969218bdc097adb4ed3800e85d8634ebae8d05da</sha1>
  </revision>
  <revision>
    <id>477</id>
    <parentid>476</parentid>
    <timestamp>2024-12-29T13:33:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $13/AH=$07 - text_put_numeric */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4964" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BX =
** if flag bit 7 clear:
*** BL = X position in text window
*** BH = Y position in text window
** if flag bit 7 set:
*** DS:BX = Output buffer to write to
* CL = Width of area to write number in
* CH = Flags
* DX = Number

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal (always pads with zeroes, aligns to right, assumes unsigned number)
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = align to left (ignores padding)
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:BX)
&lt;/pre&gt;

Errata:

- When padding a signed number with zeroes, the minus sign will be output after the zeroes; for example, calling text_put_numeric for the number &lt;tt&gt;-1234&lt;/tt&gt; with a length of 8 and those flags will print &lt;tt&gt;000-1234&lt;/tt&gt;, not &lt;tt&gt;-0001234&lt;/tt&gt;.

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>66e1fbb910d0da30fbe48286212058a09c60202b</sha1>
  </revision>
  <revision>
    <id>478</id>
    <parentid>477</parentid>
    <timestamp>2024-12-29T13:49:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $13/AH=$07 - text_put_numeric */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5174" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BX =
** if flag bit 7 clear:
*** BL = X position in text window
*** BH = Y position in text window
** if flag bit 7 set:
*** DS:BX = Output buffer to write to (at least [max(CL, length of number in characters) + 1] bytes)
* CL = Width of area to write number in
* CH = Flags
* DX = Number

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal (always pads with zeroes, aligns to right, assumes unsigned number)
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = no align to right
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:BX)
&lt;/pre&gt;

Errata:

- When padding a signed number with zeroes, the minus sign will be output after the zeroes; for example, calling text_put_numeric for the number &lt;tt&gt;-1234&lt;/tt&gt; with a length of 8 and those flags will print &lt;tt&gt;000-1234&lt;/tt&gt;, not &lt;tt&gt;-0001234&lt;/tt&gt;.
- When writing to a buffer, the code always appends a NUL character (0) at the end; as such, the buffer should always be one byte larger than the maximum width.

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>99144513418d34c72e3ba1427eca11c3dce1ca73</sha1>
  </revision>
  <revision>
    <id>479</id>
    <parentid>478</parentid>
    <timestamp>2024-12-29T13:49:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* INT $13/AH=$07 - text_put_numeric */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5174" xml:space="preserve">The Text interrupt provides a text output display using one of the WonderSwan's screens.

== Interrupts ==

=== INT $13/AH=$00 - text_screen_init ===

* AH = $00

Initializes a text window (see INT $13/AH=$01) with the following default settings:

* X, Y = 0, 0
* width, height = 28, 18
* starting tile = 512 - font tile count (in ASCII mode)
* starting tile = 512 - (width x height) (in Shift-JIS and mixed modes)

=== INT $13/AH=$01 - text_window_init ===

* AH = $01
* BL = X position on screen, in tiles
* BH = Y position on screen, in tiles
* CL = width, in tiles
* CH = height, in tiles
* DX = starting tile

Initializes a text window starting at &lt;code&gt;(BL, BH)&lt;/code&gt; with a size of &lt;code&gt;CL x CH&lt;/code&gt; tiles on the configured screen.

This requires the following number of tiles, starting at &lt;code&gt;DX&lt;/code&gt;:

* font tile count (in ASCII mode)
* width x height (in Shift-JIS and mixed modes)

=== INT $13/AH=$02 - text_set_mode ===

* AH = $02
* BX = Text mode

Available modes:

* 0 = ASCII mode
* 1 = mixed (ASCII and Shift-JIS) mode
* 2 = Shift-JIS mode

=== INT $13/AH=$03 - text_get_mode ===

* AH = $03

Return:

* BX = Text mode

=== INT $13/AH=$04 - text_put_char ===

* AH = $04
* BL = X position in text window
* BH = Y position in text window
* CX = Character code

=== INT $13/AH=$05 - text_put_string ===

* AH = $05
* BL = X position in text window
* BH = Y position in text window
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$06 - text_put_substring ===

* AH = $06
* BL = X position in text window
* BH = Y position in text window
* CX = Maximum length of string to print
* DS:DX = String to print

Return:

* AX = Number of characters displayed

=== INT $13/AH=$07 - text_put_numeric ===

* AH = $07
* BX =
** if flag bit 7 clear:
*** BL = X position in text window
*** BH = Y position in text window
** if flag bit 7 set:
*** DS:BX = Output buffer to write to (at least [max(CL, length of number in characters) + 1] bytes)
* CL = Width of area to write number in
* CH = Flags
* DX = Number

Return:

* AX = Number of characters displayed

Numeric output flags:

&lt;pre&gt;
7  bit  0
---- ----
o... slzx
|    ||||
|    |||+- 0 = output in decimal
|    |||   1 = output in hexadecimal (always pads with zeroes, aligns to right, assumes unsigned number)
|    ||+---- 0 = pad with spaces
|    ||      1 = pad with zeroes
|    |+------- 0 = align to right
|    |         1 = no align to right
|    +---------- 0 = number is unsigned
|                1 = number is signed
+----------------- 0 = output to text window (at BL, BH)
                   1 = output to buffer (DS:BX)
&lt;/pre&gt;

Errata:

* When padding a signed number with zeroes, the minus sign will be output after the zeroes; for example, calling text_put_numeric for the number &lt;tt&gt;-1234&lt;/tt&gt; with a length of 8 and those flags will print &lt;tt&gt;000-1234&lt;/tt&gt;, not &lt;tt&gt;-0001234&lt;/tt&gt;.
* When writing to a buffer, the code always appends a NUL character (0) at the end; as such, the buffer should always be one byte larger than the maximum width.

=== INT $13/AH=$08 - text_fill_char ===

* AH = $08
* BL = X position in text window
* BH = Y position in text window
* CX = Length
* DX = Character code

Repeat the specified character code &lt;code&gt;CX&lt;/code&gt; times.

=== INT $13/AH=$09 - text_set_palette ===

* AH = $09
* BX = Palette color (0-15).

Set the palette used by printed text.

=== INT $13/AH=$0A - text_get_palette ===

* AH = $0A

Return:

* AX = Palette color (0-15).

Retrieve the palette used by printed text.

=== INT $13/AH=$0B - text_set_ank_font ===

* AH = $0B
* BL = Starting character code.
* BH = Bit depth; 0 = 1bpp, 1 = 2bpp.
* CX = Number of tiles.
* DS:DX = Input buffer containing font data.

=== INT $13/AH=$0C - text_set_sjis_font ===

TODO

=== INT $13/AH=$0D - text_get_fontdata ===

* AH = $0D
* CX = Character code.
* DS:DX = Output buffer for the character's tile data.

=== INT $13/AH=$0E - text_set_screen ===

* AH = $0E
* AL = Screen ID (0, 1).

=== INT $13/AH=$0F - text_get_screen ===

* AH = $0F

Return:

* AL = Screen ID (0, 1).

=== INT $13/AH=$10 - cursor_display ===

* AH = $10
* AL = Cursor status (0 = disabled, 1 = enabled).

Controls the visibility of a blinking cursor on the text screen.

=== INT $13/AH=$11 - cursor_status ===

* AH = $11

Return:

* AX = Cursor status.

&lt;pre&gt;
7  bit  0
---- ----
.... ..ve
       ||
       |+- 0 = disabled, 1 = enabled
       +-- 0 = currently not visible, 1 = visible
&lt;/pre&gt;

=== INT $13/AH=$12 - cursor_set_location ===

* AH = $12
* BL = X position
* BH = Y position
* CL = Width, in tiles
* CH = Height, in tiles

=== INT $13/AH=$13 - cursor_get_location ===

* AH = $13

Return:

* AL = X position
* AH = Y position
* DL = Width, in tiles
* DH = Height, in tiles

=== INT $13/AH=$14 - cursor_set_type ===

* AH = $14
* BL = Palette (0-15) used by cursor area when visible
* CL = Blinking rate, in frames (0 = always visible)

The defaults are as follows:

* Palette = 1
* Blinking rate = 30

=== INT $13/AH=$15 - cursor_get_type ===

* AH = $15

Return:

* AL = Palette (0-15) used by cursor area when visible
* AH = Blinking rate, in frames (0 = always visible)</text>
    <sha1>d551fb709329d840332e3a216e32e15bdd6108a0</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>WonderWitch/FreyaBIOS/Display</title>
  <ns>0</ns>
  <id>51</id>
  <revision>
    <id>480</id>
    <parentid>325</parentid>
    <timestamp>2024-12-29T15:58:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $12/AH=$12 - sprite_set_data */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6958" xml:space="preserve">The Display interrupt provides an abstraction layer and helpers for the WonderSwan's [[Display|display hardware]].

Note that features specific to the WonderSwan Color are implemented using [[WonderWitch/Libwwc|libwwc]], which is linked statically with the user program and thus not part of the BIOS call surface.

== Interrupts ==

=== INT $12/AH=$00 - display_control ===

* AH = $00
* BX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$01 - display_status ===

* AH = $01

Return:

* AX = [[Display#Display Control|Display Control]] value

=== INT $12/AH=$02 - font_set_monodata ===

* AH = $02
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;8 x Tile count&lt;/code&gt; bytes)

Stores 1 bit-per-pixel tile data, which is expanded to 2 bits-per-pixel using the configured color.

=== INT $12/AH=$03 - font_set_colordata ===

* AH = $03
* BX = Starting tile
* CX = Tile count
* DS:DX = Input data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Stores 2 bit-per-pixel tile data.

=== INT $12/AH=$04 - font_get_data ===

* AH = $04
* BX = Starting tile
* CX = Tile count
* DS:DX = Output data buffer (&lt;code&gt;16 x Tile count&lt;/code&gt; bytes)

Retrieves 2 bit-per-pixel tile data.

=== INT $12/AH=$05 - font_set_color ===

* AH = $05
* BX = Color

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... bbff
                 ||||
                 ||++- Foreground color (0-3)
                 ++--- Background color (0-3)
&lt;/pre&gt;

Used by &lt;code&gt;font_set_monodata&lt;/code&gt;.

=== INT $12/AH=$06 - font_get_color ===

* AH = $06

Return:

* AX = Color

=== INT $12/AH=$07 - screen_set_char ===

* AH = $07
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Input tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Places a rectangular tilemap on the specified screen.

=== INT $12/AH=$08 - screen_get_char ===

* AH = $08
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DS:DX = Output tilemap buffer (&lt;code&gt;2 x Width x Height&lt;/code&gt; bytes)

Retrieves a rectangular tilemap from the specified screen.

Special case: If CL/CH are equal to 0, &lt;code&gt;DS:DX&lt;/code&gt; is ignored and instead &lt;code&gt;AX&lt;/code&gt; is set to the tile at coordinates &lt;code&gt;(BL, BH)&lt;/code&gt;. 

=== INT $12/AH=$09 - screen_fill_char ===

* AH = $09
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile attribute

Fills a rectangular area with the specified tile attribute.

=== INT $12/AH=$0A - screen_fill_attr ===

* AH = $0A
* AL = Screen (0, 1)
* BL = Top-left tile X coordinate
* BH = Top-left tile Y coordinate
* CL = Width, in tiles
* CH = Height, in tiles
* DX = Tile data
* SI = Tile mask

Modifies each tile in the specified rectangular area as follows: &lt;code&gt;tile = ((tile &amp; SI) | DX)&lt;/code&gt;.

=== INT $12/AH=$0B - sprite_set_range ===

* AH = $0B
* BX = [[Display#Sprite Table First|Sprite Table First]]
* CX = [[Display#Sprite Table Count|Sprite Table Count]]

=== INT $12/AH=$0C - sprite_set_char ===

* AH = $0C
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute

=== INT $12/AH=$0D - sprite_get_char ===

* AH = $0D
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute

=== INT $12/AH=$0E - sprite_set_location ===

* AH = $0E
* BX = Sprite ID in table (0 - 127)
* DL = X coordinate
* DH = Y coordinate

Note that DL/DH are swapped relative to the order in which the sprite coordinate bytes are stored in memory.

=== INT $12/AH=$0F - sprite_get_location ===

* AH = $0F
* BX = Sprite ID in table (0 - 127)

Return:

* AL = X coordinate
* AH = Y coordinate

=== INT $12/AH=$10 - sprite_set_char_location ===

* AH = $10
* BX = Sprite ID in table (0 - 127)
* CX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$11 - sprite_get_char_location ===

* AH = $11
* BX = Sprite ID in table (0 - 127)

Return:

* AX = Sprite attribute
* DL = X coordinate
* DH = Y coordinate

=== INT $12/AH=$12 - sprite_set_data ===

* AH = $12
* BX = Initial sprite ID in table (0 - 127)
* CX = Sprite count
* DS:DX = Input data buffer (&lt;code&gt;4 x Sprite count&lt;/code&gt; bytes)

Note that, unlike per-sprite calls (sprite_set_location, etc.), each sprite's coordinates follow the hardware layout in memory: that is, the third byte is the Y coordinate, while the fourth byte is the X coordinate.

=== INT $12/AH=$13 - screen_set_scroll ===

* AH = $13
* AL = Screen (0, 1)
* BL = [[Display#Screen Scroll|Screen Scroll X]] value
* BH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$14 - screen_get_scroll ===

* AH = $14
* AL = Screen (0, 1)

Return:

* AL = [[Display#Screen Scroll|Screen Scroll X]] value
* AH = [[Display#Screen Scroll|Screen Scroll Y]] value

=== INT $12/AH=$15 - screen2_set_window ===

* AH = $15
* BL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* BH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$16 - screen2_get_window ===

* AH = $16

Return:

* AL = [[Display#Screen 2 Window|Screen 2 Window Left]] value
* AH = [[Display#Screen 2 Window|Screen 2 Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$17 - sprite_set_window ===

* AH = $17
* BL = [[Display#Sprite Window|Sprite Window Left]] value
* BH = [[Display#Sprite Window|Sprite Window Top]] value
* CL = Window width
* CH = Window height

=== INT $12/AH=$18 - sprite_get_window ===

* AH = $18

Return:

* AL = [[Display#Sprite Window|Sprite Window Left]] value
* AH = [[Display#Sprite Window|Sprite Window Top]] value
* DL = Window width
* DH = Window height

=== INT $12/AH=$19 - palette_set_color ===

* AH = $19
* BX = Palette index (0 - 15)
* CX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1A - palette_get_color ===

* AH = $1A
* BX = Palette index (0 - 15)

Return:

* AX = [[Display#LCD Mono Palette|LCD Mono Palette]] value

=== INT $12/AH=$1B - lcd_set_color ===

* AH = $1B
* CX:BX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1C - lcd_get_color ===

* AH = $1C

Return:

* DX:AX = [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT]] value

=== INT $12/AH=$1D - lcd_set_segments ===

* AH = $1D
* BX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1E - lcd_get_segments ===

* AH = $1E

Return: 

* AX = [[Display#LCD Icon Control|LCD Icon Control]] value

=== INT $12/AH=$1F - lcd_set_sleep ===

=== INT $12/AH=$20 - lcd_get_sleep ===

=== INT $12/AH=$21 - screen_set_vram ===

* AH = $21
* AL = Screen (0, 1)
* BL = Internal RAM address, shifted right by 11

Note: This function is undocumented.

=== INT $12/AH=$22 - sprite_set_vram ===

* AH = $22
* BL = Internal RAM address, shifted right by 9

Note: This function is undocumented.</text>
    <sha1>37a6c303b93197fe5f40581d452e3e84bfed9469</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>WonderWitch/Flash</title>
  <ns>0</ns>
  <id>67</id>
  <revision>
    <id>482</id>
    <parentid>404</parentid>
    <timestamp>2025-01-01T17:36:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sector layout */ validate sector protection settings on WW cart</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1227" xml:space="preserve">The WonderWitch cartridge features a 512KiB flash chip - the MBM29DL400TC. While the WonderSwan SoC pervents writes to the ROM area, it can be written to via the SRAM area using port $CE on the [[Bandai 2003]] mapper.

== Sector layout ==

{| class="wikitable"
! Bank
! Start
! End
! Size
! Protected
|-
| rowspan="6" style="text-align: center;" | 2
| $00000
| $0FFFF
| 64 KB
| rowspan="10" style="text-align: center;" | No
|-
| $10000
| $1FFFF
| 64 KB
|-
| $20000
| $2FFFF
| 64 KB
|-
| $30000
| $3FFFF
| 64 KB
|-
| $40000
| $4FFFF
| 64 KB
|-
| $50000
| $5FFFF
| 64 KB
|-
| rowspan="8" style="text-align: center;" | 1
| $60000
| $63FFF
| 16 KB
|-
| $64000
| $6BFFF
| 32 KB
|-
| $6C000
| $6DFFF
| 8 KB
|-
| $6E000
| $6FFFF
| 8 KB
|-
| $70000
| $71FFF
| 8 KB
| rowspan="4" style="text-align: center;" | Yes
|-
| $72000
| $73FFF
| 8 KB
|-
| $74000
| $7BFFF
| 32 KB
|-
| $7C000
| $7FFFF
| 16 KB
|}

Note that the MBM29DL400TC allows operating simultaneously in two banks: the first 384 KB can be programmed or erased while the last 128 KB remains readable, and vice versa.

== Commands ==

TODO

== Links ==

* [https://github.com/up-n-atom/WonderWitch/blob/main/Datasheets/MBM29DL400BC-12PFTN_to_MBM29DL400TC-90PFTN.pdf Datasheet]</text>
    <sha1>ea9d2c33a29744c03c16b73afac63a66a9499b62</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>483</id>
    <parentid>399</parentid>
    <timestamp>2025-01-19T12:21:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Cartridge components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2016" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]]

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>38d0186907d622ff3c7c007501e81965a73db811</sha1>
  </revision>
  <revision>
    <id>484</id>
    <parentid>483</parentid>
    <timestamp>2025-01-19T12:22:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Cartridge components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2069" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>c9184e5c98f16b75f2e19a7393e35393f66c87d1</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>485</id>
    <parentid>431</parentid>
    <timestamp>2025-01-21T14:32:39Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>/* Icons */ describe all 13 icons</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19282" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1 (Small circle)
  |+------ Aux 2 (Medium circle)
  +------- Aux 3 (Large circle)
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone segment
   | ||
   | ||    Volume segments:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone segments are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, enable the Headphone segment.
* If headphones are not plugged in, enable the Speaker segment and the following Volume segments:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible segments after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>6a820be0cfa04404055c2db81678b51f21a2ae26</sha1>
  </revision>
  <revision>
    <id>486</id>
    <parentid>485</parentid>
    <timestamp>2025-01-21T16:04:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>segment -&gt; icon</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19261" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Aux 1 (Small circle)
  |+------ Aux 2 (Medium circle)
  +------- Aux 3 (Large circle)
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone icon
   | ||
   | ||    Volume icons:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>bc52ad31cae4bf25d90a0fc5cd0081a83abedfa4</sha1>
  </revision>
  <revision>
    <id>488</id>
    <parentid>486</parentid>
    <timestamp>2025-01-21T16:05:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Icon Control ($15) */ use "Etc" over "Aux" to match official terminology</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19264" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* six LCD icons to the bottom or right of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone icon
   | ||
   | ||    Volume icons:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>2abf15dfc20106eda1293e546c2fdc1842791e35</sha1>
  </revision>
  <revision>
    <id>490</id>
    <parentid>488</parentid>
    <timestamp>2025-01-21T16:09:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19291" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* a bar of LCD icon segments to the bottom (WS) or right (WSC/SC) of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;


{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone icon
   | ||
   | ||    Volume icons:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>eb1758d35c8b6434ff9e997359cb2fe965861945</sha1>
  </revision>
  <revision>
    <id>491</id>
    <parentid>490</parentid>
    <timestamp>2025-01-21T16:23:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O ports */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19888" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* a bar of LCD icon segments to the bottom (WS) or right (WSC/SC) of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone icon
   | ||
   | ||    Volume icons:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>635612c42269856da03581fa98a3a8ee1d192ed3</sha1>
  </revision>
  <revision>
    <id>492</id>
    <parentid>491</parentid>
    <timestamp>2025-01-21T16:26:55Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>/* LCD Icon Control ($15) */ "sleep" or "power save" icon is a star or shooting star</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="19895" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* a bar of LCD icon segments to the bottom (WS) or right (WSC/SC) of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

{{Anchor|LCD Mono Shade LUT}}

=== LCD Mono Shade LUT ($1C-$1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== LCD Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== Internal I/O ports ==

These I/O ports are said to be internal and not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone icon
   | ||
   | ||    Volume icons:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>837157a7ddba43d1416699a92beadcd0eac9965c</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>487</id>
    <parentid>363</parentid>
    <timestamp>2025-01-21T16:04:34Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21638" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Auxillary 3 (3), Auxillary 2 (2), Auxillary 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vvhs&lt;/tt&gt;
| RW8
| Volume icons (v), Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>deb4155e11d7013b348a4037e88cbcc430f8978e</sha1>
  </revision>
  <revision>
    <id>489</id>
    <parentid>487</parentid>
    <timestamp>2025-01-21T16:05:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>use "Etc" over "Aux" to match official terminology</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="21623" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vvhs&lt;/tt&gt;
| RW8
| Volume icons (v), Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>fd42429958b990ea438ec015ca9705cbfde669bc</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>MediaWiki:Licenses</title>
  <ns>8</ns>
  <id>70</id>
  <revision>
    <id>493</id>
    <timestamp>2025-02-05T15:57:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "* Unknown license|I don't know * cc-by-4.0|Creative Commons Attribution 4.0 * cc0-1.0|CC0 1.0"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="93" xml:space="preserve">* Unknown license|I don't know
* cc-by-4.0|Creative Commons Attribution 4.0
* cc0-1.0|CC0 1.0</text>
    <sha1>377ec51ee7be5a4280f7f1d8e41c10d906f74f53</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>File:MobileWonderGate PCB top.jpg</title>
  <ns>6</ns>
  <id>71</id>
  <revision>
    <id>494</id>
    <timestamp>2025-02-05T15:57:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Top of the MobileWonderGate peripheral's PCB.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="87" xml:space="preserve">== Summary ==
Top of the MobileWonderGate peripheral's PCB.
== Licensing ==
{{cc0-1.0}}</text>
    <sha1>e52af2652c480f240e1f97614442cdce42ab4e3a</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>File:MobileWonderGate PCB bottom.jpg</title>
  <ns>6</ns>
  <id>72</id>
  <revision>
    <id>495</id>
    <timestamp>2025-02-05T15:57:44Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Bottom of the MobileWonderGate peripheral's PCB.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="90" xml:space="preserve">== Summary ==
Bottom of the MobileWonderGate peripheral's PCB.
== Licensing ==
{{cc0-1.0}}</text>
    <sha1>2f963ab367d1498cbba290a14838b96e6900337a</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>Template:Cc0-1.0</title>
  <ns>10</ns>
  <id>73</id>
  <revision>
    <id>496</id>
    <timestamp>2025-02-05T15:58:14Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "[[Category:CC0 1.0 files|{{PAGENAME}}]] [https://creativecommons.org/publicdomain/zero/1.0/ cc0-1.0 license text]"</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="113" xml:space="preserve">[[Category:CC0 1.0 files|{{PAGENAME}}]]
[https://creativecommons.org/publicdomain/zero/1.0/ cc0-1.0 license text]</text>
    <sha1>f9517b7758fe476bda9a31fcd8dd1ca5a2d98d3c</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>WonderGate</title>
  <ns>0</ns>
  <id>14</id>
  <revision>
    <id>497</id>
    <parentid>196</parentid>
    <timestamp>2025-02-05T16:02:54Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Initial hardware documentation</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1802" xml:space="preserve">The MobileWonderGate is a PPP Internet adapter for the WonderSwan, utilizing a PDC-standard mobile phone as a modem.

== Hardware ==

The MobileWonderGate features the following major components:

* Suntac D82525GC001 - CPU?
* ST M29W800AT - 8 Mbit NOR flash
* CY7C1021V33 - 1 Mbit SRAM

&lt;gallery&gt;
File:MobileWonderGate_PCB_top.jpg|PCB top|alt=PCB top
File:MobileWonderGate_PCB_bottom.jpg|PCB bottom|alt=PCB bottom
&lt;/gallery&gt;

== Commands ==

All command communication uses the following format over 9,600 baud [[UART]]:

{| class="wikitable"
|-
! Offset !! Length !! Description
|-
| $00 || 1 || Command type
|-
| $01 || 1 || Zero?
|-
| $02 || 1 || Remaining length (from $03 onwards)
|-
| $03 || 1 || Command
|-
| $04 || ... || Parameters
|}

The following command IDs will be provided in the &lt;code&gt;Type:Command&lt;/code&gt; format.

=== Check PDC status ($01:$00) ===

=== Initialize adapter ($01:$02) ===

=== Dial phone number ($01:$08) ===

=== Hang up ($01:$0A) ===

=== Set PPP login/password ($01:$10) ===

=== Set DNS servers ($01:$11) ===

=== Get adapter status ($02:$01) ===

=== Deinitialize adapter ($0F:$FF) ===

=== Create socket ($11:$01) ===

=== Connect to socket ($11:$03) ===

=== Close socket ($11:$07) ===

=== Get host name/IP address ($11:$08) ===

=== Read line from socket ($11:$0D) ===

=== Write bytes to socket ($11:$0E) ===

=== Read bytes from socket ($11:$0F) ===

== Servers ==

{| class="wikitable"
|-
! Software !! Hostname
|-
| rowspan="2" | MobileWonderGate (web browser)
| [[WonderGate/bplXX.mopera.ne.jp|bpl01.mopera.ne.jp]]
|-
| [[WonderGate/bplXX.mopera.ne.jp|bpl02.mopera.ne.jp]]
|-
| Pocket Fighter
|
|-
| Rainbow Islands - Putty's Party
|
|-
| Star Hearts
|
|-
| Terrors 2
| [[WonderGate/terrors2.wgg.channel.or.jp|terrors2.wgg.channel.or.jp]]
|-
| Wizardry
|
|}</text>
    <sha1>461c03c0ea01acca0a726f694f1df65eb52e6d19</sha1>
  </revision>
  <revision>
    <id>498</id>
    <parentid>497</parentid>
    <timestamp>2025-02-05T17:33:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Hardware */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1904" xml:space="preserve">The MobileWonderGate is a PPP Internet adapter for the WonderSwan, utilizing a PDC-standard mobile phone as a modem.

== Hardware ==

The MobileWonderGate features the following major components:

* Suntac D82525GC001 - CPU?
* ST M29W800AT - 8 Mbit NOR flash
* CY7C1021V33 - 1 Mbit SRAM

The connector used for the PHS cable appears to be a 10-pin JST SH-1.0, but this has to be verified.

&lt;gallery&gt;
File:MobileWonderGate_PCB_top.jpg|PCB top|alt=PCB top
File:MobileWonderGate_PCB_bottom.jpg|PCB bottom|alt=PCB bottom
&lt;/gallery&gt;

== Commands ==

All command communication uses the following format over 9,600 baud [[UART]]:

{| class="wikitable"
|-
! Offset !! Length !! Description
|-
| $00 || 1 || Command type
|-
| $01 || 1 || Zero?
|-
| $02 || 1 || Remaining length (from $03 onwards)
|-
| $03 || 1 || Command
|-
| $04 || ... || Parameters
|}

The following command IDs will be provided in the &lt;code&gt;Type:Command&lt;/code&gt; format.

=== Check PDC status ($01:$00) ===

=== Initialize adapter ($01:$02) ===

=== Dial phone number ($01:$08) ===

=== Hang up ($01:$0A) ===

=== Set PPP login/password ($01:$10) ===

=== Set DNS servers ($01:$11) ===

=== Get adapter status ($02:$01) ===

=== Deinitialize adapter ($0F:$FF) ===

=== Create socket ($11:$01) ===

=== Connect to socket ($11:$03) ===

=== Close socket ($11:$07) ===

=== Get host name/IP address ($11:$08) ===

=== Read line from socket ($11:$0D) ===

=== Write bytes to socket ($11:$0E) ===

=== Read bytes from socket ($11:$0F) ===

== Servers ==

{| class="wikitable"
|-
! Software !! Hostname
|-
| rowspan="2" | MobileWonderGate (web browser)
| [[WonderGate/bplXX.mopera.ne.jp|bpl01.mopera.ne.jp]]
|-
| [[WonderGate/bplXX.mopera.ne.jp|bpl02.mopera.ne.jp]]
|-
| Pocket Fighter
|
|-
| Rainbow Islands - Putty's Party
|
|-
| Star Hearts
|
|-
| Terrors 2
| [[WonderGate/terrors2.wgg.channel.or.jp|terrors2.wgg.channel.or.jp]]
|-
| Wizardry
|
|}</text>
    <sha1>14be966f7e0c8c2ac09e1e310823325a9c4da220</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>499</id>
    <parentid>406</parentid>
    <timestamp>2025-02-21T19:34:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Flags ($C) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5200" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ?SBv
      |||
      ||+- Starting screen orientation: 0 = horizontal, 1 = vertical
      ||   Controls the splash screen's orientation.
      |+-- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
      +--- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 1 and 2 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>37c540adf1adf47e606a78354c88138af73ca9ca</sha1>
  </revision>
</page>
<page arvcontinue="20241227190206|451">
  <title>Display/IO Ports</title>
  <ns>0</ns>
  <id>74</id>
  <revision>
    <id>500</id>
    <timestamp>2025-02-22T15:21:00Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Graphics I/O ports ==  {{Anchor|Display Control}} === Display Control ($00) ===  &lt;pre&gt; 7  bit  0 ---- ---- ..wo Ws21   || ||||   || |||+- Enable Screen 1 layer   || ||+-- Enable Screen 2 layer   || |+--- Enable Sprite layer   || +---- Enable Sprite window   |+------ Screen 2 tiles are drawn (if window enabled):   |        0 = inside window,   |        1 = outside window.   +------- Enable Screen 2 window &lt;/pre&gt;  {{Anchor|Display Background}}  === Display Background Co..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8528" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
...v vvhs
   | ||||
   | |||+- LCD sleep: 0 = no, 1 = sleep
   | ||+-- Headphone icon
   | ||
   | ||    Volume icons:
   | |+--- - Volume B (medium, high)
   | +---- - Volume A (low, high)
   +------ - Speaker
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
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</page>
<page arvcontinue="20250222152141|501">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>501</id>
    <parentid>492</parentid>
    <timestamp>2025-02-22T15:21:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>move I/O ports out</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11654" xml:space="preserve">The WonderSwan's display functionality generally consists of:

* a 224x144 display clocked at ~75.47 Hz by default, capable of displaying:
** up to sixteen distinct shades of gray
** 12-bit RGB444 color&lt;sup&gt;(color)&lt;/sup&gt;
* two 32x32 background layers ("screens"), capable of displaying up to 512 (1024&lt;sup&gt;(color)&lt;/sup&gt;) distinct tiles,
* a sprite layer, capable of displaying up to 128 8x8 sprites (up to 32 per line),
* a bar of LCD icon segments to the bottom (WS) or right (WSC/SC) of the display, usable as additional indicators.

== Components ==

=== Tiles ===

The WonderSwan can display up to 512 distinct tiles at a time, with two bits of palette index information for every pixel.

The WonderSwan Color expands this to 1024 distinct tiles for background (with 512 remaining the limit for sprites), while also introducing modes with four bits of palette index information for every pixel.

==== 2 bits per pixel, planar ====

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

==== 4 bits per pixel, planar ====

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

==== 4 bits per pixel, packed ====

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.

=== Palettes ===

The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

==== Mono ====

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

==== Color ====

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

==== Transparency ====

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

=== Background color ===

The background color is displayed if no ''opaque'' pixel from screens or sprites is drawn. This color is set in I/O port ''0x01'':

* In mono modes, it is set to an entry in the shade lookup table (0-7),
* In color modes, it is set to an entry in the color palette (0-255). Note that this allows you to use the first color (color zero) of any palette, which is normally ignored and assumed to be ''transparent''.

=== Screens ===

A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.

=== Sprites ===

The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.

=== Visibility priority ===

For display components, the visibility priority is as follows:

* Sprite 0, high priority
* Sprite 127, high priority
* Screen 2
* Sprite 0, low priority
* Sprite 127, low priority
* Screen 1
* Background color

=== Windows ===

Screen 2 and sprites can optionally have their drawing restricted within or outside of their specific rectangular windows.

Note that for sprites, the window is enabled globally (for all sprites), but each sprite can individually decide if it's rendered inside or outside of it.

=== Icons ===

The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== See also ==

* [[Display/IO Ports|Display I/O ports]]</text>
    <sha1>8d7bdb25ce8caa5eedcdb730d0658a393ee46d63</sha1>
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  <revision>
    <id>508</id>
    <parentid>501</parentid>
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      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2215" xml:space="preserve">The WonderSwan features a 224x144 display capable of displaying up to 16 shades of gray (mono) or 4096 colors (color).

{| class="wikitable"
! ↑ Front ↑
! Window
! Scroll
|-
| align="center" | Sprites, high priority
| ✔
|
|-
| align="center" | Screen 2
| ✔
| ✔
|-
| align="center" | Sprites, low priority
| ✔
|
|-
| align="center" | Screen 1
| 
| ✔
|-
| align="center" | Background color
| 
|
|-
! ↑ Back ↑
!
!
|}

== Features ==

Screens are 32x32 tile maps; each map entry can use one of 512 (mono) or 1024 (color) tiles, one of sixteen distinct palettes, as well as be drawn mirrored or flipped.

The sprite layer consists of 128 distinct sprites. These can use any of the first 512 tiles, palettes 8 through 15, as well as be drawn over or under screen 2.

The window functionality can be used to restrict drawing of Screen 2's tiles, as well as the sprite layer, to a given pixel-perfect window. Individual sprites can be marked as being drawn inside or outside the window.

Each palette consists of four colors, of which the first entry - color zero - is opaque in palettes 0-3 and 8-11 and transparent otherwise. The color models additionally feature a sixteen-color palette mode, in which color zero is always considered transparent. The background color is displayed if no ''opaque'' pixel from any screens or sprites is drawn.

In addition, a set of LCD segment-based icons is provided to a side of the display which can be independently controlled as an indicator to the user.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== More information ==

* [[Display/Tile Data|Tile data]]
* [[Display/Palettes|Color palettes]]
* [[Display/Screens|Screen format]]
* [[Display/Sprites|Sprite format]]
* [[Display/LCD Icons|LCD icons]]
* [[Display/IO Ports|I/O ports]]</text>
    <sha1>1822169930cc4dc54eb80d0d2cae2ec658924805</sha1>
  </revision>
  <revision>
    <id>509</id>
    <parentid>508</parentid>
    <timestamp>2025-02-23T09:56:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* More information */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2213" xml:space="preserve">The WonderSwan features a 224x144 display capable of displaying up to 16 shades of gray (mono) or 4096 colors (color).

{| class="wikitable"
! ↑ Front ↑
! Window
! Scroll
|-
| align="center" | Sprites, high priority
| ✔
|
|-
| align="center" | Screen 2
| ✔
| ✔
|-
| align="center" | Sprites, low priority
| ✔
|
|-
| align="center" | Screen 1
| 
| ✔
|-
| align="center" | Background color
| 
|
|-
! ↑ Back ↑
!
!
|}

== Features ==

Screens are 32x32 tile maps; each map entry can use one of 512 (mono) or 1024 (color) tiles, one of sixteen distinct palettes, as well as be drawn mirrored or flipped.

The sprite layer consists of 128 distinct sprites. These can use any of the first 512 tiles, palettes 8 through 15, as well as be drawn over or under screen 2.

The window functionality can be used to restrict drawing of Screen 2's tiles, as well as the sprite layer, to a given pixel-perfect window. Individual sprites can be marked as being drawn inside or outside the window.

Each palette consists of four colors, of which the first entry - color zero - is opaque in palettes 0-3 and 8-11 and transparent otherwise. The color models additionally feature a sixteen-color palette mode, in which color zero is always considered transparent. The background color is displayed if no ''opaque'' pixel from any screens or sprites is drawn.

In addition, a set of LCD segment-based icons is provided to a side of the display which can be independently controlled as an indicator to the user.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== More information ==

* [[Display/Tile Data|Tile data]]
* [[Display/Palette|Color palette]]
* [[Display/Screens|Screen format]]
* [[Display/Sprites|Sprite format]]
* [[Display/LCD Icons|LCD icons]]
* [[Display/IO Ports|I/O ports]]</text>
    <sha1>db680ed2e36b1e724d3dbdd8a458cea382fe9d54</sha1>
  </revision>
  <revision>
    <id>515</id>
    <parentid>509</parentid>
    <timestamp>2025-02-23T10:06:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2227" xml:space="preserve">The WonderSwan features a 224x144 display capable of displaying up to 16 shades of gray (mono) or 4096 colors (color).

{| class="wikitable"
! ↑ Front ↑
! Window
! Scroll
|-
| align="center" | Sprites, high priority
| ✔
|
|-
| align="center" | Screen 2
| ✔
| ✔
|-
| align="center" | Sprites, low priority
| ✔
|
|-
| align="center" | Screen 1
| 
| ✔
|-
| align="center" | Background color
| 
|
|-
! ↑ Back ↑
! Window
! Scroll
|}

== Features ==

Screens are 32x32 tile maps; each map entry can use one of 512 (mono) or 1024 (color) tiles, one of sixteen distinct palettes, as well as be drawn mirrored or flipped.

The sprite layer consists of 128 distinct sprites. These can use any of the first 512 tiles, palettes 8 through 15, as well as be drawn over or under screen 2.

The window functionality can be used to restrict drawing of Screen 2's tiles, as well as the sprite layer, to a given pixel-perfect window. Individual sprites can be marked as being drawn inside or outside the window.

Each palette consists of four colors, of which the first entry - color zero - is opaque in palettes 0-3 and 8-11 and transparent otherwise. The color models additionally feature a sixteen-color palette mode, in which color zero is always considered transparent. The background color is displayed if no ''opaque'' pixel from any screens or sprites is drawn.

In addition, a set of LCD segment-based icons is provided to a side of the display which can be independently controlled as an indicator to the user.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== More information ==

* [[Display/Tile Data|Tile data]]
* [[Display/Palette|Color palette]]
* [[Display/Screens|Screen format]]
* [[Display/Sprites|Sprite format]]
* [[Display/LCD Icons|LCD icons]]
* [[Display/IO Ports|I/O ports]]</text>
    <sha1>1af84ba660a84cba0b038cdc7cea6306e82b3384</sha1>
  </revision>
  <revision>
    <id>516</id>
    <parentid>515</parentid>
    <timestamp>2025-02-23T11:02:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* More information */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2257" xml:space="preserve">The WonderSwan features a 224x144 display capable of displaying up to 16 shades of gray (mono) or 4096 colors (color).

{| class="wikitable"
! ↑ Front ↑
! Window
! Scroll
|-
| align="center" | Sprites, high priority
| ✔
|
|-
| align="center" | Screen 2
| ✔
| ✔
|-
| align="center" | Sprites, low priority
| ✔
|
|-
| align="center" | Screen 1
| 
| ✔
|-
| align="center" | Background color
| 
|
|-
! ↑ Back ↑
! Window
! Scroll
|}

== Features ==

Screens are 32x32 tile maps; each map entry can use one of 512 (mono) or 1024 (color) tiles, one of sixteen distinct palettes, as well as be drawn mirrored or flipped.

The sprite layer consists of 128 distinct sprites. These can use any of the first 512 tiles, palettes 8 through 15, as well as be drawn over or under screen 2.

The window functionality can be used to restrict drawing of Screen 2's tiles, as well as the sprite layer, to a given pixel-perfect window. Individual sprites can be marked as being drawn inside or outside the window.

Each palette consists of four colors, of which the first entry - color zero - is opaque in palettes 0-3 and 8-11 and transparent otherwise. The color models additionally feature a sixteen-color palette mode, in which color zero is always considered transparent. The background color is displayed if no ''opaque'' pixel from any screens or sprites is drawn.

In addition, a set of LCD segment-based icons is provided to a side of the display which can be independently controlled as an indicator to the user.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== More information ==

* [[Display/Tile Data|Tile data]]
* [[Display/Palette|Color palette]]
* [[Display/Screens|Screen format]]
* [[Display/Sprites|Sprite format]]
* [[Display/Windows|Windows]]
* [[Display/LCD Icons|LCD icons]]
* [[Display/IO Ports|I/O ports]]</text>
    <sha1>6255c2cfba6c6c1af1d4d8683566ccbaa4a0c9de</sha1>
  </revision>
  <revision>
    <id>521</id>
    <parentid>516</parentid>
    <timestamp>2025-02-23T11:13:27Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Features */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2345" xml:space="preserve">The WonderSwan features a 224x144 display capable of displaying up to 16 shades of gray (mono) or 4096 colors (color).

{| class="wikitable"
! ↑ Front ↑
! Window
! Scroll
|-
| align="center" | Sprites, high priority
| ✔
|
|-
| align="center" | Screen 2
| ✔
| ✔
|-
| align="center" | Sprites, low priority
| ✔
|
|-
| align="center" | Screen 1
| 
| ✔
|-
| align="center" | Background color
| 
|
|-
! ↑ Back ↑
! Window
! Scroll
|}

== Features ==

Screens are 32x32 tile maps, for a total of 256x256 pixels; each map entry can use one of 512 (mono) or 1024 (color) tiles, one of sixteen distinct palettes, as well as be drawn mirrored or flipped. The screens can be scrolled horizontally and vertically.

The sprite layer consists of 128 distinct sprites. These can use any of the first 512 tiles, palettes 8 through 15, as well as be drawn over or under screen 2.

The window functionality can be used to restrict drawing of Screen 2's tiles, as well as the sprite layer, to a given pixel-perfect window. Individual sprites can be marked as being drawn inside or outside the window.

Each palette consists of four colors, of which the first entry - color zero - is opaque in palettes 0-3 and 8-11 and transparent otherwise. The color models additionally feature a sixteen-color palette mode, in which color zero is always considered transparent. The background color is displayed if no ''opaque'' pixel from any screens or sprites is drawn.

In addition, a set of LCD segment-based icons is provided to a side of the display which can be independently controlled as an indicator to the user.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== More information ==

* [[Display/Tile Data|Tile data]]
* [[Display/Palette|Color palette]]
* [[Display/Screens|Screen format]]
* [[Display/Sprites|Sprite format]]
* [[Display/Windows|Windows]]
* [[Display/LCD Icons|LCD icons]]
* [[Display/IO Ports|I/O ports]]</text>
    <sha1>d3f3c05eef37ed384ec9e32468700ffdd77bb341</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>502</id>
    <parentid>489</parentid>
    <timestamp>2025-02-22T15:23:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>fix links</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22028" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...v vvhs&lt;/tt&gt;
| RW8
| Volume icons (v), Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>5511f7e993d0ea33f729ee6b6b85982bbaf74723</sha1>
  </revision>
  <revision>
    <id>523</id>
    <parentid>502</parentid>
    <timestamp>2025-02-23T15:42:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document $1A bit 5</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22048" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| RW8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>18e04bf4202a962da730a1c6fe8ceb7c4ba19a6d</sha1>
  </revision>
  <revision>
    <id>526</id>
    <parentid>523</parentid>
    <timestamp>2025-02-23T16:05:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */ document port $18</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22207" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Current Line|LCD Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| RW8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>e8576c7b6c0ab50a135eb979f7666e75f2e69d34</sha1>
  </revision>
  <revision>
    <id>528</id>
    <parentid>526</parentid>
    <timestamp>2025-02-23T16:07:21Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22207" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="45" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| RW8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>3b610589c20ad464118e57c883aefa49c6feb0b9</sha1>
  </revision>
  <revision>
    <id>529</id>
    <parentid>528</parentid>
    <timestamp>2025-02-23T16:07:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22207" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="46" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| RW8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Sleep (s)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>258a463d8d2f8f51fc4f7eff2e7e031ce0b6b959</sha1>
  </revision>
  <revision>
    <id>531</id>
    <parentid>529</parentid>
    <timestamp>2025-02-23T20:08:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22425" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;t??? swcl&lt;/tt&gt;
| RW8
| Test OK (t), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>b8cbc9ef7e841cc990587ee615b5764400246e94</sha1>
  </revision>
  <revision>
    <id>533</id>
    <parentid>531</parentid>
    <timestamp>2025-02-23T20:13:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22430" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>2c5cfed0b0dbfa80c069add2cd83c205cf9412ed</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/LCD Icons</title>
  <ns>0</ns>
  <id>75</id>
  <revision>
    <id>503</id>
    <timestamp>2025-02-23T09:38:09Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:  * [[#LCD_Icon_Control_($15)|Six under control of software]] ** Large circle ** Medium circle ** Small circle ** Horizontal orientation ** Vertical orientation ** (Shooting) Star (Sleep)  * [[#LCD_Status_($1A)|Four software can query]] ** Speaker ** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="774" xml:space="preserve">The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* Two that are entirely invisible to software
** Power on ("Egg", resembles the mono power switch)
** Cartridge</text>
    <sha1>8b79cb7a16de9ec06ea7148e2f7c32c0e6bc149d</sha1>
  </revision>
  <revision>
    <id>524</id>
    <parentid>503</parentid>
    <timestamp>2025-02-23T15:42:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="773" xml:space="preserve">The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Four software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones
** Cartridge

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* One that is entirely invisible to software
** Power on ("Egg", resembles the mono power switch)</text>
    <sha1>22ecaa19c195e46a506d873cdfbc20f42260ab0f</sha1>
  </revision>
  <revision>
    <id>525</id>
    <parentid>524</parentid>
    <timestamp>2025-02-23T15:43:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="773" xml:space="preserve">The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[#LCD_Icon_Control_($15)|Six under control of software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[#LCD_Status_($1A)|Five software can query]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones
** Cartridge

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* One that is entirely invisible to software
** Power on ("Egg", resembles the mono power switch)</text>
    <sha1>1e7bb451d39b629f8b06f66fe49c43a827f8d4f7</sha1>
  </revision>
  <revision>
    <id>535</id>
    <parentid>525</parentid>
    <timestamp>2025-02-23T20:14:11Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1690" xml:space="preserve">The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[Display/IO Ports#LCD_Icon_Control_($15)|Six controlled by software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[Display/IO Ports#LCD Status|Five controlled by hardware latches]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones
** Cartridge

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* One that is entirely invisible to software
** Power on ("Egg", resembles the mono power switch)

== Hardware latch behaviour ==

There are two hardware latches: one controls the cartridge icon, while the other controls the sound icons. These latches are always displayed for an additional 128 ticks after their display condition stops being true.

=== Sound icons ===

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan. 

=== Cartridge icon ===

The cartridge icon is displayed for 128 ticks after the [[SoC#System Control|System Control]] cartridge test passes on console start.</text>
    <sha1>9a1f906d4191205c3ed0cf6bafb2e045703ab3c4</sha1>
  </revision>
  <revision>
    <id>540</id>
    <parentid>535</parentid>
    <timestamp>2025-02-24T18:30:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1700" xml:space="preserve">The WonderSwan features thirteen fixed LCD segments which are displayed to the right&lt;sup&gt;(color)&lt;/sup&gt; or below&lt;sup&gt;(mono)&lt;/sup&gt; the main display. These are:

* [[Display/IO Ports#LCD_Icon_Control_($15)|Six controlled by software]]
** Large circle
** Medium circle
** Small circle
** Horizontal orientation
** Vertical orientation
** (Shooting) Star (Sleep)

* [[Display/IO Ports#LCD Status|Five controlled by hardware latches]]
** Speaker
** Volume A (small wave&lt;sup&gt;(mono)&lt;/sup&gt;, center wave&lt;sup&gt;(color)&lt;/sup&gt;)
** Volume B (big wave&lt;sup&gt;(mono)&lt;/sup&gt;, outside two waves&lt;sup&gt;(color)&lt;/sup&gt;)
** Headphones
** Cartridge

* [[Interrupts#Interrupt_NMI_Control_($B7)|One that the software can infer]]
** Low battery

* One that is entirely invisible to software
** Power on ("Egg", resembles the mono power switch)

== Hardware latch behaviour ==

There are two hardware latches: one controls the cartridge icon, while the other controls the sound icons. These latches are always displayed for an additional 128 vertical blanks after their display condition stops being true.

=== Sound icons ===

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan. 

=== Cartridge icon ===

The cartridge icon is displayed for 128 ticks after the [[SoC#System Control|System Control]] cartridge test passes on console start.</text>
    <sha1>442e211eb498ec11ef51f991ef0239e3aab4e577</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/Tile Data</title>
  <ns>0</ns>
  <id>76</id>
  <revision>
    <id>504</id>
    <timestamp>2025-02-23T09:40:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "== Tile data ==  The tile data is stored at a fixed memory location:  * &lt;tt&gt;$2000&lt;/tt&gt; - &lt;tt&gt;$3FFF&lt;/tt&gt; for 2 bit per pixel tiles in "mono" mode, for a total of 512 tiles. * &lt;tt&gt;$2000&lt;/tt&gt; - &lt;tt&gt;$5FFF&lt;/tt&gt; for 2 bit per pixel tiles in "color" mode, for a total of 1024 tiles. * &lt;tt&gt;$4000&lt;/tt&gt; - &lt;tt&gt;$BFFF&lt;/tt&gt; for 4 bit per pixel tiles in "color" mode, for a total of 1024 tiles.  == Tile data formats ==  === 2 bits per pixel, planar ===  The tiles are stored in an interlea..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4271" xml:space="preserve">== Tile data ==

The tile data is stored at a fixed memory location:

* &lt;tt&gt;$2000&lt;/tt&gt; - &lt;tt&gt;$3FFF&lt;/tt&gt; for 2 bit per pixel tiles in "mono" mode, for a total of 512 tiles.
* &lt;tt&gt;$2000&lt;/tt&gt; - &lt;tt&gt;$5FFF&lt;/tt&gt; for 2 bit per pixel tiles in "color" mode, for a total of 1024 tiles.
* &lt;tt&gt;$4000&lt;/tt&gt; - &lt;tt&gt;$BFFF&lt;/tt&gt; for 4 bit per pixel tiles in "color" mode, for a total of 1024 tiles.

== Tile data formats ==

=== 2 bits per pixel, planar ===

The tiles are stored in an interleaved planar format, with two bits total for every pixel. Odd bytes store the first plane (bit 0 of each pixel), while even bytes store the second plane (bit 1 of each pixel).

&lt;pre&gt;
             tile data (16 bytes)
01 7C 01 FC 00 C0 18 D8 18 D8 00 C0 00 00 C0 00

                      ||
                      \/

 plane 0          plane 1
7  bit  0        7  bit  0            full tile
---- ----        ---- ----
.... ...1 = 01   .222 22.. = 7C       .22222.1
.... ...1 = 01   2222 22.. = FC       222222.1
.... .... = 00   22.. .... = C0       22......
...1 1... = 18   22.2 2... = D8  --\  22.33...
...1 1... = 18   22.2 2... = D8  --/  22.33...
.... .... = 00   22.. .... = C0       22......
.... .... = 00   .... .... = 00       ........
11.. .... = C0   .... .... = 00       11......
&lt;/pre&gt;

This matches the format used by the Game Boy.

=== 4 bits per pixel, planar ===

This mode is stored in a manner similar to the 2 bits per pixel mode, but with an additional two planes for bit 2 and bit 3 of each pixel's palette index, expanding the tile data to 32 bytes.


&lt;pre&gt;
                                      tile data (32 bytes)
54 32 01 00 54 32 F1 00 54 32 01 F0 54 32 F1 F0 04 02 01 00 F8 04 02 01 00 F8 04 02 00 00 F8 04

                                               ||
                                               \/

 plane 0          plane 1          plane 2          plane 3
7  bit  0        7  bit  0        7  bit  0        7  bit  0            full tile
---- ----        ---- ----        ---- ----        ---- ----
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   .... .... = 00       .123.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   .... .... = 00       4567.124
.1.1 .1.. = 54   ..22 ..2. = 32   .... ...4 = 01   8888 .... = F0       89AB.124
.1.1 .1.. = 54   ..22 ..2. = 32   4444 ...4 = F1   8888 .... = F0  --\  CDEF.124
.... .1.. = 04   .... ..2. = 02   .... ...4 = 01   .... .... = 00  --/  .....124
1111 1... = F8   .... .2.. = 04   .... ..4. = 02   .... ...8 = 01       11111248
.... .... = 00   2222 2... = F8   .... .4.. = 04   .... ..8. = 02       2222248.
.... .... = 00   .... .... = 00   4444 4... = F8   .... .8.. = 04       444448..
&lt;/pre&gt;

This format matches the one used by the Sega Master System and Game Gear family of consoles.

=== 4 bits per pixel, packed ===

Unlike the previous two formats, in the packed format each byte stores the complete palette index of two pixels - the high four bits store the left pixel, while the low four bits store the right pixel. Four such bytes make up a row of eight pixels from left to right.

&lt;pre&gt;
                                      tile data (32 bytes)
01 23 01 24 45 67 01 24 89 AB 01 24 CD EF 01 24 00 00 01 24 11 11 12 48 22 22 24 80 44 44 48 00

                                               ||
                                               \/

 byte     0            1          2          3
 bits  7-4 3-0      7-4 3-0    7-4 3-0    7-4 3-0
 pixel  0   1        2  3       4   5      6   7           full tile
       --- ---      --- ---    --- ---    --- ---
         . 1 = 01     2 3 = 23   . 1 = 01   2 4 = 24       .123.124 = 01 23 01 24
         4 5 = 45     6 7 = 67   . 1 = 01   2 4 = 24       4567.124 = 45 67 01 24
         8 9 = 89     A B = AB   . 1 = 01   2 4 = 24       89AB.124 = 89 AB 01 24
         C D = CD     E F = EF   . 1 = 01   2 4 = 24  --\  CDEF.124 = CD EF 01 24
         . . = 00     . . = 00   . 1 = 01   2 4 = 24  --/  .....124 = 00 00 01 24
         1 1 = 11     1 1 = 11   1 2 = 12   4 8 = 48       11111248 = 11 11 12 48
         2 2 = 22     2 2 = 22   2 4 = 24   8 . = 80       2222248. = 22 22 24 80
         4 4 = 44     4 4 = 44   4 8 = 48   . . = 00       444448.. = 44 44 48 00
&lt;/pre&gt;

This format matches the one used by the Mega Drive console.</text>
    <sha1>215afcb95d2c4b37a7f3e7d5d8510ba225c448f1</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/Palette</title>
  <ns>0</ns>
  <id>77</id>
  <revision>
    <id>505</id>
    <timestamp>2025-02-23T09:51:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The display system provides sixteen different palettes that can be used to color or shade tiles.  * Palettes 0-7 can be used for the two screens only; * Palettes 8-15 can be used for both screens and sprites.  == Palette format ==  === Mono ===  In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:  &lt;pre&gt;       Palette            Global shade LUT..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1974" xml:space="preserve">The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

== Palette format ==

=== Mono ===

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

=== Color ===

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

== Palette transparency ==

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.</text>
    <sha1>83e9ea732f979187791713772d6de41732e63caf</sha1>
  </revision>
  <revision>
    <id>510</id>
    <parentid>505</parentid>
    <timestamp>2025-02-23T10:01:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3028" xml:space="preserve">The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

== Palette format ==

=== Mono ===

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

=== Color ===

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

== Palette transparency ==

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

== Color reproduction ==

Different variants of the WonderSwan render colors differently.

=== WonderSwan "mono" ===

This model uses an FSTN display with an approximately linear gamma (~1.0) response for the shades 0 (brightest) through 15 (darkest). Its color reproduction characteristics are very similar to Nintendo's Game Boy Pocket, which uses the same technology.

=== WonderSwan Color ===

This model uses a CSTN display.

In "mono" compatibility mode on Color consoles, the linear gamma response is not retained; shade 0 is equivalent to color &lt;tt&gt;#FFF&lt;/tt&gt;, shade 1 to &lt;tt&gt;#EEE&lt;/tt&gt;, and shade 15 is equivalent to color &lt;tt&gt;#000&lt;/tt&gt;

=== SwanCrystal ===

This model uses a TFT LCD display. Its color reproduction characteristics are very similar to Nintendo's Game Boy Color, which uses the same technology. Its gamma is close to standard video (2.2).

=== Aftermarket/non-standard hardware ===

Generally, IPS mods, as well as both official and unofficial TV output kits, use standard video gamma throughout, even for the "mono" WonderSwan.</text>
    <sha1>0de97937009d342a9e697de562db35a136d4889d</sha1>
  </revision>
  <revision>
    <id>511</id>
    <parentid>510</parentid>
    <timestamp>2025-02-23T10:01:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Color reproduction */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3102" xml:space="preserve">The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

== Palette format ==

=== Mono ===

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

=== Color ===

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

== Palette transparency ==

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

== Color reproduction ==

Different variants of the WonderSwan have displays which reproduce colors differently. As such, there is no canon palette for the system.

=== WonderSwan "mono" ===

This model uses an FSTN display with an approximately linear gamma (~1.0) response for the shades 0 (brightest) through 15 (darkest). Its color reproduction characteristics are very similar to Nintendo's Game Boy Pocket, which uses the same technology.

=== WonderSwan Color ===

This model uses a CSTN display.

In "mono" compatibility mode on Color consoles, the linear gamma response is not retained; shade 0 is equivalent to color &lt;tt&gt;#FFF&lt;/tt&gt;, shade 1 to &lt;tt&gt;#EEE&lt;/tt&gt;, and shade 15 is equivalent to color &lt;tt&gt;#000&lt;/tt&gt;

=== SwanCrystal ===

This model uses a TFT LCD display. Its color reproduction characteristics are very similar to Nintendo's Game Boy Color, which uses the same technology. Its gamma is close to standard video (2.2).

=== Aftermarket/non-standard hardware ===

Generally, IPS mods, as well as both official and unofficial TV output kits, use standard video gamma throughout, even for the "mono" WonderSwan.</text>
    <sha1>df89da41beed47f3337b8c212f86becf812f8a3e</sha1>
  </revision>
  <revision>
    <id>514</id>
    <parentid>511</parentid>
    <timestamp>2025-02-23T10:05:32Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* WonderSwan Color */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3103" xml:space="preserve">The display system provides sixteen different palettes that can be used to color or shade tiles.

* Palettes 0-7 can be used for the two screens only;
* Palettes 8-15 can be used for both screens and sprites.

== Palette format ==

=== Mono ===

In ''mono'' modes, palettes are stored in I/O ports 0x20 through 0x3F. Each palette contains four three-bit entries, which are pointers into a global, four-bit shade lookup table:

&lt;pre&gt;
      Palette            Global shade LUT
 1  ===========&gt; 2 ==========================&gt; 5
 ^  (0, 2, 4, 6) ^ (1, 3, 5, 7, 9, 11, 13, 15) ^
 |               |                             |
Palette index   Value                         Displayed shade
&lt;/pre&gt;

The shade value corresponds to the darkness of the pixel: shade 0 is the brightest, while shade 15 is the darkest.

=== Color ===

In ''color'' modes, palettes are stored as 16-bit words in memory addresses 0xFE00 through 0xFFFF, without additional lookup tables:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 1111 111p  pppi iii.
         |  |||| |||
         |  |||+-+++-- Index in palette (0-15)
         +--+++------- Palette number (0-15)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... rrrr  gggg bbbb
      ||||  |||| ||||
      ||||  |||| ++++- Blue (0-15)
      ||||  ++++------ Green (0-15)
      ++++------------ Red (0-15)
&lt;/pre&gt;

In 2 bits per pixel color modes, palette entries 4 through 15 are not used.

== Palette transparency ==

In two bit per pixel modes:

* Palettes 0-3 and 8-11 are ''opaque''. For these, index zero is treated as opaque.
* Palettes 4-7 and 12-15 are ''translucent''. For these, index zero is treated as transparent. This means that the color/shade value set to it is ignored, and only three distinct colors/shades can be used for tiles.

In four bit per pixel modes, all palettes are ''translucent''. Index zero is always treated as transparent, and fifteen different colors/shades can be used for tiles.

== Color reproduction ==

Different variants of the WonderSwan have displays which reproduce colors differently. As such, there is no canon palette for the system.

=== WonderSwan "mono" ===

This model uses an FSTN display with an approximately linear gamma (~1.0) response for the shades 0 (brightest) through 15 (darkest). Its color reproduction characteristics are very similar to Nintendo's Game Boy Pocket, which uses the same technology.

=== WonderSwan Color ===

This model uses a CSTN display.

In "mono" compatibility mode on Color consoles, the linear gamma response is not retained; shade 0 is equivalent to color &lt;tt&gt;#FFF&lt;/tt&gt;, shade 1 to &lt;tt&gt;#EEE&lt;/tt&gt;, and shade 15 is equivalent to color &lt;tt&gt;#000&lt;/tt&gt;.

=== SwanCrystal ===

This model uses a TFT LCD display. Its color reproduction characteristics are very similar to Nintendo's Game Boy Color, which uses the same technology. Its gamma is close to standard video (2.2).

=== Aftermarket/non-standard hardware ===

Generally, IPS mods, as well as both official and unofficial TV output kits, use standard video gamma throughout, even for the "mono" WonderSwan.</text>
    <sha1>bfe8610ac0f1e8d7d505d404a2534292952d5cbc</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/Screens</title>
  <ns>0</ns>
  <id>78</id>
  <revision>
    <id>506</id>
    <timestamp>2025-02-23T09:54:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with " A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.  The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.  The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:  &lt;pre&gt;        Address 15  bit  8  7  bit  0  ---- ----  ---- ----  0bbb byyy  yyxx xxx.   ||| ||||  |||| |||   ||| ||||  ||++-+++-- X coord..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="977" xml:space="preserve">
A screen is a layout of tiles. Each cell in a screen controls one 8x8 tile.

The display system can show two distinct screens simultaneously. It also supports hardware flipping of tiles, both horizontally and vertically.

The size of each screen is fixed at 32x32 cells or 256x256 pixels, while each cell is stored as a two-byte word:

&lt;pre&gt;
       Address
15  bit  8  7  bit  0
 ---- ----  ---- ----
 0bbb byyy  yyxx xxx.
  ||| ||||  |||| |||
  ||| ||||  ||++-+++-- X coordinate (0-31)
  ||| |+++--++-------- Y coordinate (0-31)
  +++-+--------------- Base address (from I/O port)

         Data
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhbp pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511)
 |||+-+++------------- Palette (0-15)
 ||+------------------ Tile bank (0-1) - color only
 |+------------------- Horizontal flip
 +-------------------- Vertical flip
&lt;/pre&gt;

In ''color'' modes, the tile bank selects between tiles 0-511 and 512-1023.</text>
    <sha1>02d9d5f71ec4b25fec9ced51ac05f5c35e5e0216</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/Sprites</title>
  <ns>0</ns>
  <id>79</id>
  <revision>
    <id>507</id>
    <timestamp>2025-02-23T09:54:27Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with " The display system can show up to 128 sprites at once.  Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.  Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:  &lt;pre&gt;  (Byte 1)   (Byte 0) 15  bit  8  7  bit  0  ---- ----  ---- ----  vhPi pppt  tttt tttt  |||| ||||  |||| ||||  |||| |||+--++++-++++- Tile index (0-511..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1597" xml:space="preserve">
The display system can show up to 128 sprites at once.

Sprites are always drawn in front of Screen 1, but they can be drawn in front of or behind Screen 2.

Sprites are stored in a sprite table in the console's internal RAM. It consists of up to 128 four-byte entries, of which any sequential slice can be displayed:

&lt;pre&gt;
 (Byte 1)   (Byte 0)
15  bit  8  7  bit  0
 ---- ----  ---- ----
 vhPi pppt  tttt tttt
 |||| ||||  |||| ||||
 |||| |||+--++++-++++- Tile index (0-511) - only tile bank 0
 |||| +++------------- Palette (0-7) - mapped to screen palettes 8-15
 |||+----------------- Window location - 0 = inside, 1 = outside
 ||+------------------ Priority - 0 = behind Screen 2, 1 = in front of Screen 2
 |+------------------- Horizontal flip
 +-------------------- Vertical flip

 (Byte 2)
 7  bit  0
 ---- ----
 yyyy yyyy
 |||| ||||
 ++++-++++- Y coordinate

 (Byte 3)
 7  bit  0
 ---- ----
 xxxx xxxx
 |||| ||||
 ++++-++++- X coordinate
&lt;/pre&gt;

There is a sprite limit of 32 per scanline. This means that for each scanline, only the first 32 sprites will be drawn. Note that this includes sprites obscured by windows or outside of visible X coordinates; this list is determined solely by the Y coordinate. Between sprites themselves, earlier sprites in the list are always drawn on top of later sprites in the list.

The sprite table is copied from the console's RAM to a SoC-internal buffer every frame on line &lt;tt&gt;144&lt;/tt&gt;; one word for every clock of the line, totaling 256 words (512 bytes) for 256 clocks. This internal buffer is then used for reading sprite data on the next frame.</text>
    <sha1>72be2493c30b1fe73e5f8d01635facb7da4c398e</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>512</id>
    <parentid>484</parentid>
    <timestamp>2025-02-23T10:02:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Console components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2290" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
*** [[Display/Tile Data|Tile data]]
*** [[Display/Palette|Color palette]]
*** [[Display/Screens|Screen format]]
*** [[Display/Sprites|Sprite format]]
*** [[Display/LCD Icons|LCD icons]]
*** [[Display/IO Ports|I/O ports]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>ecce62f3de56d5dd631fea14885c65bf616b3a24</sha1>
  </revision>
  <revision>
    <id>518</id>
    <parentid>512</parentid>
    <timestamp>2025-02-23T11:06:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Console components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2322" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
*** [[Display/Tile Data|Tile data]]
*** [[Display/Palette|Color palette]]
*** [[Display/Screens|Screen format]]
*** [[Display/Sprites|Sprite format]]
*** [[Display/Windows|Windows]]
*** [[Display/LCD Icons|LCD icons]]
*** [[Display/IO Ports|I/O ports]]
** [[Sound]]
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>7b27a88f7498792cab06eda52149083363c364d5</sha1>
  </revision>
  <revision>
    <id>519</id>
    <parentid>518</parentid>
    <timestamp>2025-02-23T11:07:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Console components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2372" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
*** [[Display/Tile Data|Tile data]]
*** [[Display/Palette|Color palette]]
*** [[Display/Screens|Screen format]]
*** [[Display/Sprites|Sprite format]]
*** [[Display/Windows|Windows]]
*** [[Display/LCD Icons|LCD icons]]
*** [[Display/IO Ports|I/O ports]]
** [[Sound]]
*** [[DMA#Sound_DMA|Sound DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>969cce53fde0f2dd9d77c90b4798fd02f6e94aee</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Memory map</title>
  <ns>0</ns>
  <id>25</id>
  <revision>
    <id>513</id>
    <parentid>330</parentid>
    <timestamp>2025-02-23T10:04:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal */ add URLs to Display subpages</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="4038" xml:space="preserve">The WonderSwan's SoC uses a 20-bit physical memory map, split into three regions with distinct bus widths, timings, and access permissions;

{| class="wikitable"
|+ WonderSwan physical memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000&lt;br/&gt;0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000&lt;br/&gt;0xFFFFF
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| 8-bit
| 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
| RW
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0xFFFFF
| 8/16-bit (configurable)
| 1/2 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture. The CPU, [[Display]] and [[Sound]] components make use of data stored in a shared RAM in distinct segments of the 12.288 MHz SoC clock. This is in contrast to many other platforms which feature, for example, separate video memory. This allows the CPU to modify video and audio data without worrying about wait states or video timing; however, the video and audio components have location and alignment restrictions for data:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 4 bytes - far addresses)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''[[Display/Tile Data|Tile data]] (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
! rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''[[Display/Tile Data|Tile data]] (bank 1)'''
| rowspan="2" style="text-align: center;" | '''[[Display/Tile Data|Tile data]] (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''[[Display/Tile Data|Tile data]] (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| colspan="2" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''[[Display/Palette|Color palette]]'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| [[Display/Screens|Screen]]
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800&lt;br/&gt;0x7800&lt;sup&gt;(color)&lt;/sup&gt;
| 0x800 (2048) bytes
|-
| [[Display/Sprites|Sprite table]]
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00&lt;br/&gt;0x7E00&lt;sup&gt;(color)&lt;/sup&gt;
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

Note that an element being present on this map does not mean that the space cannot be utilized for other data. For example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space.

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper physical memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000&lt;br/&gt;0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000&lt;br/&gt;0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000&lt;br/&gt;0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000&lt;br/&gt;0xFFFFF
| ROM linear (EX) bank
|}</text>
    <sha1>719ee6d7ddab575f677256930561e756e100deba</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/Windows</title>
  <ns>0</ns>
  <id>80</id>
  <revision>
    <id>517</id>
    <timestamp>2025-02-23T11:06:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The Screen 2 and Sprite layers can optionally have their drawing restricted within or without specific rectangular windows.  In the case of Screen 2, one can use the Display Control port to configure if the window should render only the tiles inside of it. Alternatively, once can configure the window to only render tiles outside of it, in which case the window rectangle acts as a cut-out.  {| class="wikitable" ! ! Window inside ! Window outside |- ! Pixel inside | align=..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="790" xml:space="preserve">The Screen 2 and Sprite layers can optionally have their drawing restricted within or without specific rectangular windows.

In the case of Screen 2, one can use the Display Control port to configure if the window should render only the tiles inside of it. Alternatively, once can configure the window to only render tiles outside of it, in which case the window rectangle acts as a cut-out.

{| class="wikitable"
!
! Window inside
! Window outside
|-
! Pixel inside
| align="center" | ✔
|
|-
! Pixel outside
|
| align="center" | ✔
|}

In the case of the sprite layer, one can configure this individually for each sprite in its attributes.

{| class="wikitable"
!
! Sprite inside
! Sprite outside
|-
! Pixel inside
| align="center" | ✔
|
|-
! Pixel outside
|
| align="center" | ✔
|}</text>
    <sha1>08b2e8edf47a6c2ac953bece6a3aae7af9f1d1cd</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Boot ROM</title>
  <ns>0</ns>
  <id>81</id>
  <revision>
    <id>520</id>
    <timestamp>2025-02-23T11:11:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WonderSwan boot ROM is where the console begins execution on power on.  * On the "mono" model, it occupies an area from &lt;tt&gt;$FF000&lt;/tt&gt; to &lt;tt&gt;$FFFFF&lt;/tt&gt;, for a total of 4 KiB. * On the Color model, it occupies an area from &lt;tt&gt;$FE000&lt;/tt&gt; to &lt;tt&gt;$FFFFF&lt;/tt&gt;, for a total of 8 KiB.  It performs the following activities:  * checks if the cartridge self-test passed; * checks if the cartridge footer is valid; * if START is held when the console is turned on, enters the..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="666" xml:space="preserve">The WonderSwan boot ROM is where the console begins execution on power on.

* On the "mono" model, it occupies an area from &lt;tt&gt;$FF000&lt;/tt&gt; to &lt;tt&gt;$FFFFF&lt;/tt&gt;, for a total of 4 KiB.
* On the Color model, it occupies an area from &lt;tt&gt;$FE000&lt;/tt&gt; to &lt;tt&gt;$FFFFF&lt;/tt&gt;, for a total of 8 KiB.

It performs the following activities:

* checks if the cartridge self-test passed;
* checks if the cartridge footer is valid;
* if START is held when the console is turned on, enters the boot ROM menu;
* updates telemetry/diagnostics information in the internal EEPROM;
* displays the splash screen (optionally, a custom splash screen on Color models);
* jumps to the cartridge.</text>
    <sha1>b0854f5ba38da8a3fdda5bc6c7cc4091f0f5f705</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Display/IO Ports</title>
  <ns>0</ns>
  <id>74</id>
  <revision>
    <id>522</id>
    <parentid>500</parentid>
    <timestamp>2025-02-23T15:41:50Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Status ($1A) */ add bit 5</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8558" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhs
  || ||||
  || |||+- LCD sleep: 0 = no, 1 = sleep
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>b4afc078c7cb4006f30c6c91f2dd0a56375a17db</sha1>
  </revision>
  <revision>
    <id>527</id>
    <parentid>522</parentid>
    <timestamp>2025-02-23T16:06:59Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD internal I/O ports */ document port $18</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8878" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Status ($1A) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhs
  || ||||
  || |||+- LCD sleep: 0 = no, 1 = sleep
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

The LCD sleep bit is writable. The remaining bits are read-only.

The volume and headphone icon are enabled when pressing the SOUND button, according to this algorithm:

* If headphones are plugged in, show the Headphone icon.
* If headphones are not plugged in, show the Speaker icon and the following Volume icons:
** Volume level 0: None
** Volume level 1: A
** Volume level 2: B
** Volume level 3: A, B
* Hide all visible icons after 128 frames from the last press.

TODO: This documents the WonderSwan Color. The specifics probably work differently on the mono WonderSwan.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>8037c6aff452a61f9de9d252456ff9ec1650bcc0</sha1>
  </revision>
  <revision>
    <id>530</id>
    <parentid>527</parentid>
    <timestamp>2025-02-23T20:07:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Status ($1A) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9026" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- Latch override: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- Latch override: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Show sound segments
  +------- Show cartridge segment
&lt;/pre&gt;

This port allows overriding the default behaviour of the "cartridge segment" and "sound segment" display logic.

Note that other bits may only be written to when the latch override is enabled.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>a69890cc25407c9dcecf8ddb5a528f55fba52a3b</sha1>
  </revision>
  <revision>
    <id>532</id>
    <parentid>530</parentid>
    <timestamp>2025-02-23T20:09:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Control ($14) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9098" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

TODO: Bits 4-7 are writable, but only on WSC. Their effect is unknown.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- Latch override: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- Latch override: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Show sound segments
  +------- Show cartridge segment
&lt;/pre&gt;

This port allows overriding the default behaviour of the "cartridge segment" and "sound segment" display logic.

Note that other bits may only be written to when the latch override is enabled.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>9981b8d5bd9aa07c66a87056cc2e7d8f70860b54</sha1>
  </revision>
  <revision>
    <id>538</id>
    <parentid>532</parentid>
    <timestamp>2025-02-24T18:27:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Latched Icon Status ($1A read) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9168" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

TODO: Bits 4-7 are writable, but only on WSC. Their effect is unknown.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- LCD block disable: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

Bit 0 (LCD block disable) reflects the value written to the port.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- Latch override: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Show sound segments
  +------- Show cartridge segment
&lt;/pre&gt;

This port allows overriding the default behaviour of the "cartridge segment" and "sound segment" display logic.

Note that other bits may only be written to when the latch override is enabled.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>3de8efd972132fbf18e5931a609795c0cf91e151</sha1>
  </revision>
  <revision>
    <id>539</id>
    <parentid>538</parentid>
    <timestamp>2025-02-24T18:30:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Latched Icon Control ($1A write) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9567" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics; if sleeping, it displays nothing (all white). Note that icon segments continue displaying regardless of this configuration.

Note that port $1A provides a separate LCD sleep bit; the display will be disabled in the same way if any of those bits are set to "sleep".

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

TODO: Bits 4-7 are writable, but only on WSC. Their effect is unknown.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- LCD block disable: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

Bit 0 (LCD block disable) reflects the value written to the port.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- LCD block disable: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Latch sound segments
  +------- Latch cartridge segment
&lt;/pre&gt;

This port allows disabling the full LCD IP block; if bit 0 is set, all LCD panel control (including segments and sound/cartridge segment display timers) is disabled.

This port also allows manually latching the sound/cartridge segment display with their respective timers; however, this can only be done if bit 0 is set. For example, to latch the cartridge segment timer, one can write &lt;tt&gt;$21&lt;/tt&gt; to the port to disable the LCD block and latch the cartridge segment. Next, after re-enabling the LCD block by clearing bit 0, the cartridge segment will be shown for 128 vertical blanks.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>1ce31fbf36db5275e9af39bf7a374ce1035343cb</sha1>
  </revision>
  <revision>
    <id>544</id>
    <parentid>539</parentid>
    <timestamp>2025-02-24T18:43:21Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Control ($14) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9422" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics. When it is cleared, the pixel area acts as if it was powered off, but the segment area continues functioning as normal.

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

TODO: Bits 4-7 are writable, but only on WSC. Their effect is unknown.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- LCD block disable: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

Bit 0 (LCD block disable) reflects the value written to the port.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- LCD block disable: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Latch sound segments
  +------- Latch cartridge segment
&lt;/pre&gt;

This port allows disabling the full LCD IP block; if bit 0 is set, all LCD panel control (including segments and sound/cartridge segment display timers) is disabled.

This port also allows manually latching the sound/cartridge segment display with their respective timers; however, this can only be done if bit 0 is set. For example, to latch the cartridge segment timer, one can write &lt;tt&gt;$21&lt;/tt&gt; to the port to disable the LCD block and latch the cartridge segment. Next, after re-enabling the LCD block by clearing bit 0, the cartridge segment will be shown for 128 vertical blanks.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>a7dfe306ea73b6ff78b24a7040b3381f1f7d6854</sha1>
  </revision>
  <revision>
    <id>545</id>
    <parentid>544</parentid>
    <timestamp>2025-02-24T18:44:30Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* LCD Control ($14) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9429" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics. When it is cleared, the pixel area acts as if it was powered off, but the segment area continues functioning as normal.

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

TODO: Bits 4-7 are writable, but only on WS and WSC. Their effect is unknown.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- LCD block disable: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

Bit 0 (LCD block disable) reflects the value written to the port.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- LCD block disable: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Latch sound segments
  +------- Latch cartridge segment
&lt;/pre&gt;

This port allows disabling the full LCD IP block; if bit 0 is set, all LCD panel control (including segments and sound/cartridge segment display timers) is disabled.

This port also allows manually latching the sound/cartridge segment display with their respective timers; however, this can only be done if bit 0 is set. For example, to latch the cartridge segment timer, one can write &lt;tt&gt;$21&lt;/tt&gt; to the port to disable the LCD block and latch the cartridge segment. Next, after re-enabling the LCD block by clearing bit 0, the cartridge segment will be shown for 128 vertical blanks.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>dea4ac49803ffda5ea918811257f314e5cd04578</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>SoC</title>
  <ns>0</ns>
  <id>46</id>
  <revision>
    <id>534</id>
    <parentid>328</parentid>
    <timestamp>2025-02-23T20:13:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1780" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
t??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- Cartridge bus test OK
&lt;/pre&gt;

{{Anchor|System Control 2}}
=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>2034e42571522c49c98bc90bd5f9f696ab22c00f</sha1>
  </revision>
  <revision>
    <id>536</id>
    <parentid>534</parentid>
    <timestamp>2025-02-23T20:16:13Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* System Control ($A0) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1781" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
C??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- Cartridge bus test OK
&lt;/pre&gt;

{{Anchor|System Control 2}}

=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Power off system
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

== Notes ==
&lt;references /&gt;</text>
    <sha1>9075c576177a89fbd676c4feb1e470d751e28659</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>WonderWitch/Filesystem</title>
  <ns>0</ns>
  <id>59</id>
  <revision>
    <id>537</id>
    <parentid>365</parentid>
    <timestamp>2025-02-23T21:06:03Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1732" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || Location in CPU address space (segment:offset)
|-
| 44 || 4 || Total file size, in bytes, excluding the header.
|-
| 48 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time
|-
| 56 || 4 || TODO
|-
| 60 || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== Timestamp format ===

{| class="wikitable"
|+ Header contents
|-
! Bits !! Contents
|-
| 31 - 25 || Year, starting from 2000
|-
| 24 - 21 || Month
|-
| 20 - 16 || Day
|-
| 15 - 11 || Hour
|-
| 10 - 5 || Minute
|-
| 0 - 4 || Second, in two-second units
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>2559fafa1da69e189166ef4fd2bc76f8dd65b6bc</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>NEC V30MZ instruction set</title>
  <ns>0</ns>
  <id>68</id>
  <revision>
    <id>541</id>
    <parentid>481</parentid>
    <timestamp>2025-02-24T18:31:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>clarify register field</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57778" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below.

Some instructions define a second argument using the ''Register'' field. It is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt; and, as such, can refer to a register only.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH imm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>e5146544a960b0bb55423ba9858cf830f1112b3a</sha1>
  </revision>
  <revision>
    <id>542</id>
    <parentid>541</parentid>
    <timestamp>2025-02-24T18:32:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* PUSH */ use simm8</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57780" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below.

Some instructions define a second argument using the ''Register'' field. It is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt; and, as such, can refer to a register only.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH simm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}

=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>6107727191d4e552a94f26b13baf9cd1976a66a2</sha1>
  </revision>
  <revision>
    <id>543</id>
    <parentid>542</parentid>
    <timestamp>2025-02-24T18:33:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57779" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below.

Some instructions define a second argument using the ''Register'' field. It is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt; and, as such, can refer to a register only.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}
=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH simm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>d340101c9753781594599503b826d46efae592ac</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>Real-Time Clock</title>
  <ns>0</ns>
  <id>40</id>
  <revision>
    <id>546</id>
    <parentid>410</parentid>
    <timestamp>2025-02-24T19:02:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Reset RTC ($10, $11) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6170" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour &gt;= 12); however, writes to the bit are ignored.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>e12332fd16e5c3f28190b587deb25787f31fc8d2</sha1>
  </revision>
  <revision>
    <id>547</id>
    <parentid>546</parentid>
    <timestamp>2025-02-24T19:02:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Reset RTC ($10, $11) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6079" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour &gt;= 12); however, writes to the bit are ignored.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>166b32f1c2a400474f30c805b0721823ceb48c0a</sha1>
  </revision>
  <revision>
    <id>548</id>
    <parentid>547</parentid>
    <timestamp>2025-02-24T19:02:56Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Registers */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6342" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour &gt;= 12); however, writes to the bit are ignored.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

=== Initial power on state ===

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$82&lt;/tt&gt;
* Alarm = &lt;tt&gt;$8000&lt;/tt&gt;

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>9257554945dd3042f5dfc5e34a7b678d23da4bf1</sha1>
  </revision>
</page>
<page arvcontinue="20250222152141|501">
  <title>NEC V30MZ interrupts</title>
  <ns>0</ns>
  <id>58</id>
  <revision>
    <id>549</id>
    <parentid>346</parentid>
    <timestamp>2025-03-01T11:05:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Timing */ document IRQ acknowledgement timing</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2151" xml:space="preserve">The NEC V30MZ provides six of the eight interrupts provided by the 80186.

== Interrupts ==

=== INT 0 - Divide Error ===

This interrupt is emitted as the result of a DIV&lt;sup&gt;IDIV&lt;/sup&gt; or DIVU&lt;sup&gt;DIV&lt;/sup&gt; instruction.

=== INT 1 - Single Step/Break ===

This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interrupt, allowing the user to store state and perform debug activities; it is then restored when returning from the interrupt, by restoring the original processor flags stored on the stack.

=== INT 2 - Non-Maskable interrupt (NMI) ===

This interrupt is emitted when the SoC requests a non-maskable interrupt. On the WonderSwan, the condtions for emitting an NMI are configured by the relevant I/O port.

=== INT 3 - Breakpoint ===

This interrupt is emitted by the INT 3&lt;sup&gt;BRK&lt;/sup&gt; instruction. Unlike other unconditional interrupt instructions, it is encoded with only one byte.

=== INT 4 - Overflow ===

This interrupt is emitted by the INTO&lt;sup&gt;BRKV&lt;/sup&gt; instruction, if the overflow flag is set while it is being executed.

=== INT 5 - Array Bounds ===

This interrupt is emitted only by the BOUND&lt;sup&gt;CHKIND&lt;/sup&gt; instruction.

== Timing ==

Both non-maskable and maskable interrupts are acknowledged after the execution of an instruction is complete. However, under some conditions, interrupts may not be processed on a given instruction and delayed until the next one. This is the case for:

* instructions which change the stack segment register (MOV and POP),
* prefix instructions (LOCK, REP, segment prefixes),
* instructions which set the interrupt enable CPU flag (STI, POPF) if the flag was cleared prior to the instruction's execution (for maskable interrupts only).

TODO: Document how many cycles interrupt processing takes.

== Notes ==

* The following 80186 interrupts are not implemented:
** INT 6 - Unused Opcode - the V30MZ treats most unimplemented instructions as NOPs.
** INT 7 - ESC Opcode - the V30MZ, likewise, treats these instructions as NOPs.</text>
    <sha1>30f6d3d613d2fa77ef534d22ff2db46613cff761</sha1>
  </revision>
  <revision>
    <id>550</id>
    <parentid>549</parentid>
    <timestamp>2025-03-01T11:09:16Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2523" xml:space="preserve">== CPU interrupts ==

The NEC V30MZ implements six of the eight CPU interrupts provided by the 80186.

=== INT 0 - Divide Error ===

This interrupt is emitted as the result of a DIV&lt;sup&gt;IDIV&lt;/sup&gt; or DIVU&lt;sup&gt;DIV&lt;/sup&gt; instruction.

=== INT 1 - Single Step/Break ===

This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interrupt, allowing the user to store state and perform debug activities; it is then restored when returning from the interrupt, by restoring the original processor flags stored on the stack.

=== INT 2 - Non-Maskable interrupt (NMI) ===

This interrupt is emitted when the SoC requests a non-maskable interrupt. On the WonderSwan, the condtions for emitting an NMI are configured by the relevant I/O port.

=== INT 3 - Breakpoint ===

This interrupt is emitted by the INT 3&lt;sup&gt;BRK&lt;/sup&gt; instruction. Unlike other unconditional interrupt instructions, it is encoded with only one byte.

=== INT 4 - Overflow ===

This interrupt is emitted by the INTO&lt;sup&gt;BRKV&lt;/sup&gt; instruction, if the overflow flag is set while it is being executed.

=== INT 5 - Array Bounds ===

This interrupt is emitted only by the BOUND&lt;sup&gt;CHKIND&lt;/sup&gt; instruction.

== External interrupts ==

The NEC V30MZ distinguishes three sources of external interrupts - that is, interrupts not triggered by an instruction itself:

* Non-maskable interrupts:
** NMI - controlled by the NMI control I/O port on WS,
** BRK - controlled by the single-step flag.
* Maskable interrupts:
** IRQ - controlled by the IRQ control I/O ports on WS.

== Timing ==

Both non-maskable and maskable interrupts are acknowledged after the execution of an instruction is complete. However, under some conditions, interrupts may not be processed on a given instruction and delayed until the next one. This is the case for:

* instructions which change the stack segment register (MOV and POP),
* prefix instructions (LOCK, REP, segment prefixes),
* instructions which set the interrupt enable CPU flag (STI, POPF) if the flag was cleared prior to the instruction's execution (for maskable interrupts only).

TODO: Document how many cycles interrupt processing takes.

== Notes ==

* The following 80186 interrupts are not implemented:
** INT 6 - Unused Opcode - the V30MZ treats most unimplemented instructions as NOPs.
** INT 7 - ESC Opcode - the V30MZ, likewise, treats these instructions as NOPs.</text>
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  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>NEC V30MZ instruction set</title>
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  <id>68</id>
  <revision>
    <id>551</id>
    <parentid>543</parentid>
    <timestamp>2025-03-01T17:03:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* MOV */ fix encoding</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57780" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POLL|POLL]]
|-
| [[#POP|POP]] || [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]]
|-
| [[#RETF|RETF]] || [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]]
|-
| [[#STC|STC]] || [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POLL|POLL]]
| [[#POLL|POLL]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#POLL|POLL]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below.

Some instructions define a second argument using the ''Register'' field. It is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt; and, as such, can refer to a register only.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}

=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POLL}}
=== POLL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POLL || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH simm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>bda72248085fbadcb904b9e2d776d79f32971b73</sha1>
  </revision>
  <revision>
    <id>594</id>
    <parentid>551</parentid>
    <timestamp>2025-04-13T12:36:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>POLL -&gt; WAIT</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57960" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POP|POP]]
|-
| [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]] || [[#RETF|RETF]]
|-
| [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]] || [[#STC|STC]]
|-
| [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#WAIT|WAIT]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#WAIT|WAIT]]
| [[#WAIT|POLL]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#WAIT|WAIT]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below.

Some instructions define a second argument using the ''Register'' field. It is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt; and, as such, can refer to a register only.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}

=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT AX, DX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT AL, imm8 || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT AX, imm8 || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}
=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH simm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|WAIT}}
=== WAIT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| WAIT || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

Nominally, this instruction synchronizes the CPU with an external co-processor. However, as the WonderSwan does not feature one, this instruction simply becomes a (slower) no-op.

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>591c480a1e15b36b90ee7969bb8738aa03600586</sha1>
  </revision>
  <revision>
    <id>595</id>
    <parentid>594</parentid>
    <timestamp>2025-04-20T17:56:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* OUT */ Fix operand order (thanks PECO!)</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="57961" xml:space="preserve">__NOTOC__

Note that this page is a work in progress.

{| class="wikitable" style="text-align: center"
|+ Official V30MZ (80186) Instructions
|-
| [[#AAA|AAA]] || [[#AAD|AAD]] || [[#AAM|AAM]] || [[#AAS|AAS]] || [[#ADC|ADC]] || [[#ADD|ADD]] || [[#AND|AND]] || [[#BOUND|BOUND]] || [[#CALL|CALL]] || [[#CBW|CBW]] || [[#CLC|CLC]]
|-
| [[#CLD|CLD]] || [[#CLI|CLI]] || [[#CMC|CMC]] || [[#CMP|CMP]] || [[#CMPSB|CMPSB]] || [[#CMPSW|CMPSW]] || [[#CS|CS]] || [[#CWD|CWD]] || [[#DAA|DAA]] || [[#DAS|DAS]] || [[#DEC|DEC]]
|-
| [[#DIV|DIV]] || [[#DS|DS]] || [[#ENTER|ENTER]] || [[#ES|ES]] || [[#HLT|HLT]] || [[#IDIV|IDIV]] || [[#IMUL|IMUL]] || [[#IN|IN]] || [[#INC|INC]] || [[#INSB|INSB]] || [[#INSW|INSW]]
|-
| [[#INT|INT]] || [[#INTO|INTO]] || [[#IRET|IRET]] || [[#JA|JA]] || [[#JBE|JBE]] || [[#JC|JC]] || [[#JCXZ|JCXZ]] || [[#JG|JG]] || [[#JGE|JGE]] || [[#JL|JL]] || [[#JLE|JLE]]
|-
| [[#JMP|JMP]] || [[#JNC|JNC]] || [[#JNO|JNO]] || [[#JNP|JNP]] || [[#JNS|JNS]] || [[#JNZ|JNZ]] || [[#JO|JO]] || [[#JP|JP]] || [[#JS|JS]] || [[#JZ|JZ]] || [[#LAHF|LAHF]]
|-
| [[#LDS|LDS]] || [[#LEA|LEA]] || [[#LEAVE|LEAVE]] || [[#LES|LES]] || [[#LOCK|LOCK]] || [[#LODSB|LODSB]] || [[#LODSW|LODSW]] || [[#LOOP|LOOP]] || [[#LOOPE|LOOPE]] || [[#LOOPNE|LOOPNE]] || [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]] || [[#MOVSW|MOVSW]] || [[#MUL|MUL]] || [[#NEG|NEG]] || [[#NOP|NOP]] || [[#NOT|NOT]] || [[#OR|OR]] || [[#OUT|OUT]] || [[#OUTSB|OUTSB]] || [[#OUTSW|OUTSW]] || [[#POP|POP]]
|-
| [[#POPA|POPA]] || [[#POPF|POPF]] || [[#PUSH|PUSH]] || [[#PUSHA|PUSHA]] || [[#PUSHF|PUSHF]] || [[#RCL|RCL]] || [[#RCR|RCR]] || [[#REP|REP]] || [[#REPNE|REPNE]] || [[#RET|RET]] || [[#RETF|RETF]]
|-
| [[#ROL|ROL]] || [[#ROR|ROR]] || [[#SAHF|SAHF]] || [[#SAR|SAR]] || [[#SBB|SBB]] || [[#SCASB|SCASB]] || [[#SCASW|SCASW]] || [[#SHL|SHL]] || [[#SHR|SHR]] || [[#SS|SS]] || [[#STC|STC]]
|-
| [[#STD|STD]] || [[#STI|STI]] || [[#STOSB|STOSB]] || [[#STOSW|STOSW]] || [[#SUB|SUB]] || [[#TEST|TEST]] || [[#WAIT|WAIT]] || [[#XCHG|XCHG]] || [[#XLAT|XLAT]] || [[#XOR|XOR]]
|}

{| class="mw-collapsible mw-collapsed wikitable sortable" style="width: 340px;"
|+ style="white-space:nowrap; border:1px solid; padding:3px; border-color:rgb(162, 169, 177); background-color:rgb(234, 236, 240);" | Intel &lt;-&gt; NEC mnemonic translation table
!Intel
!NEC
|-
| [[#AAA|AAA]]
| [[#AAA|ADJBA]]
|-
| [[#AAD|AAD]]
| [[#AAD|CVTDB]]
|-
| [[#AAM|AAM]]
| [[#AAM|CVTBD]]
|-
| [[#AAS|AAS]]
| [[#AAS|ADJBS]]
|-
| [[#ADC|ADC]]
| [[#ADC|ADDC]]
|-
| [[#ADD|ADD]]
| [[#ADD|ADD]]
|-
| [[#AND|AND]]
| [[#AND|AND]]
|-
| [[#BOUND|BOUND]]
| [[#BOUND|CHKIND]]
|-
| [[#CALL|CALL]]
| [[#CALL|CALL]]
|-
| [[#CBW|CBW]]
| [[#CBW|CVTBW]]
|-
| [[#CLC|CLC]]
| [[#CLC|CLR1 CY]]
|-
| [[#CLD|CLD]]
| [[#CLD|CLR1 DIR]]
|-
| [[#CLI|CLI]]
| [[#CLI|DI]]
|-
| [[#CMC|CMC]]
| [[#CMC|NOT1 CY]]
|-
| [[#CMP|CMP]]
| [[#CMP|CMP]]
|-
| [[#CMPSB|CMPSB]]
| [[#CMPSB|CMPBKB]]
|-
| [[#CMPSW|CMPSW]]
| [[#CMPSW|CMPBKW]]
|-
| [[#CS|CS]]
| [[#CS|PS]]
|-
| [[#CWD|CWD]]
| [[#CWD|CVTWL]]
|-
| [[#DAA|DAA]]
| [[#DAA|ADJ4A]]
|-
| [[#DAS|DAS]]
| [[#DAS|ADJ4S]]
|-
| [[#DEC|DEC]]
| [[#DEC|DEC]]
|-
| [[#DIV|DIV]]
| [[#DIV|DIVU]]
|-
| [[#DS|DS]]
| [[#DS|DS0]]
|-
| [[#ENTER|ENTER]]
| [[#ENTER|PREPARE]]
|-
| [[#ES|ES]]
| [[#ES|DS1]]
|-
| [[#HLT|HLT]]
| [[#HLT|HALT]]
|-
| [[#IDIV|IDIV]]
| [[#IDIV|DIV]]
|-
| [[#IMUL|IMUL]]
| [[#IMUL|MUL]]
|-
| [[#IN|IN]]
| [[#IN|IN]]
|-
| [[#INC|INC]]
| [[#INC|INC]]
|-
| [[#INSB|INSB]]
| [[#INSB|INMB]]
|-
| [[#INSW|INSW]]
| [[#INSW|INMW]]
|-
| [[#INT|INT]]
| [[#INT|BRK]]
|-
| [[#INTO|INTO]]
| [[#INTO|BRKV]]
|-
| [[#IRET|IRET]]
| [[#IRET|RETI]]
|-
| [[#JA|JA]]
| [[#JA|BH]]
|-
| [[#JBE|JBE]]
| [[#JBE|BNH]]
|-
| [[#JC|JC/JB]]
| [[#JC|BC/BL]]
|-
| [[#JCXZ|JCXZ]]
| [[#JCXZ|BCWZ]]
|-
| [[#JG|JG]]
| [[#JG|BGT]]
|-
| [[#JGE|JGE]]
| [[#JGE|BGE]]
|-
| [[#JL|JL]]
| [[#JL|BLT]]
|-
| [[#JLE|JLE]]
| [[#JLE|BLE]]
|-
| [[#JMP|JMP]]
| [[#JMP|BR]]
|-
| [[#JNC|JNC/JAE]]
| [[#JNC|BNC/BNL]]
|-
| [[#JNO|JNO]]
| [[#JNO|BNV]]
|-
| [[#JNP|JNP]]
| [[#JNP|BPO]]
|-
| [[#JNS|JNS]]
| [[#JNS|BP]]
|-
| [[#JNZ|JNZ/JNE]]
| [[#JNZ|BNZ/BNE]]
|-
| [[#JO|JO]]
| [[#JO|BV]]
|-
| [[#JP|JP]]
| [[#JP|BPE]]
|-
| [[#JS|JS]]
| [[#JS|BN]]
|-
| [[#JZ|JZ/JE]]
| [[#JZ|BZ/BE]]
|-
| [[#LAHF|LAHF]]
| [[#LAHF|MOV]]
|-
| [[#LDS|LDS]]
| [[#LDS|MOV]]
|-
| [[#LEA|LEA]]
| [[#LEA|LDEA]]
|-
| [[#LEAVE|LEAVE]]
| [[#LEAVE|DISPOSE]]
|-
| [[#LES|LES]]
| [[#LES|MOV]]
|-
| [[#LOCK|LOCK]]
| [[#LOCK|BUSLOCK]]
|-
| [[#LODSB|LODSB]]
| [[#LODSB|LDMB]]
|-
| [[#LODSW|LODSW]]
| [[#LODSW|LDMW]]
|-
| [[#LOOP|LOOP]]
| [[#LOOP|DBNZ]]
|-
| [[#LOOPE|LOOPE]]
| [[#LOOPE|DBNZE]]
|-
| [[#LOOPNE|LOOPNE]]
| [[#LOOPNE|DBNZNE]]
|-
| [[#MOV|MOV]]
| [[#MOV|MOV]]
|-
| [[#MOVSB|MOVSB]]
| [[#MOVSB|MOVBKB]]
|-
| [[#MOVSW|MOVSW]]
| [[#MOVSW|MOVBKW]]
|-
| [[#MUL|MUL]]
| [[#MUL|MULU]]
|-
| [[#NEG|NEG]]
| [[#NEG|NEG]]
|-
| [[#NOP|NOP]]
| [[#NOP|NOP]]
|-
| [[#NOT|NOT]]
| [[#NOT|NOT]]
|-
| [[#OR|OR]]
| [[#OR|OR]]
|-
| [[#OUT|OUT]]
| [[#OUT|OUT]]
|-
| [[#OUTSB|OUTSB]]
| [[#OUTSB|OUTM]]
|-
| [[#OUTSW|OUTSW]]
| [[#OUTSW|OUTM]]
|-
| [[#POP|POP]]
| [[#POP|POP]]
|-
| [[#POPA|POPA]]
| [[#POPA|POP]]
|-
| [[#POPF|POPF]]
| [[#POPF|POP]]
|-
| [[#PUSH|PUSH]]
| [[#PUSH|PUSH]]
|-
| [[#PUSHA|PUSHA]]
| [[#PUSHA|PUSH]]
|-
| [[#PUSHF|PUSHF]]
| [[#PUSHF|PUSH]]
|-
| [[#RCL|RCL]]
| [[#RCL|ROLC]]
|-
| [[#RCR|RCR]]
| [[#RCR|RORC]]
|-
| [[#REP|REP/REPE/REPZ]]
| [[#REP|REP/REPE/REPZ]]
|-
| [[#REPNE|REPNE/REPNZ]]
| [[#REPNE|REPNE/REPNZ]]
|-
| [[#RET|RET]]
| [[#RET|RET]]
|-
| [[#RETF|RETF]]
| [[#RETF|RET]]
|-
| [[#ROL|ROL]]
| [[#ROL|ROL]]
|-
| [[#ROR|ROR]]
| [[#ROR|ROR]]
|-
| [[#SAHF|SAHF]]
| [[#SAHF|MOV]]
|-
| [[#SAR|SAR]]
| [[#SAR|SHRA]]
|-
| [[#SBB|SBB]]
| [[#SBB|SUBC]]
|-
| [[#SCASB|SCASB]]
| [[#SCASB|CMPMB]]
|-
| [[#SCASW|SCASW]]
| [[#SCASW|CMPMW]]
|-
| [[#SHL|SHL]]
| [[#SHL|SHL]]
|-
| [[#SHR|SHR]]
| [[#SHR|SHR]]
|-
| [[#SS|SS]]
| [[#SS|SS]]
|-
| [[#STC|STC]]
| [[#STC|SET1 CY]]
|-
| [[#STD|STD]]
| [[#STD|SET1 DIR]]
|-
| [[#STI|STI]]
| [[#STI|EI]]
|-
| [[#STOSB|STOSB]]
| [[#STOSB|STMB]]
|-
| [[#STOSW|STOSW]]
| [[#STOSW|STMW]]
|-
| [[#SUB|SUB]]
| [[#SUB|SUB]]
|-
| [[#TEST|TEST]]
| [[#TEST|TEST]]
|-
| [[#WAIT|WAIT]]
| [[#WAIT|POLL]]
|-
| [[#XCHG|XCHG]]
| [[#XCHG|XCH]]
|-
| [[#XLAT|XLAT]]
| [[#XLAT|TRANS]]
|-
| [[#XOR|XOR]]
| [[#XOR|XOR]]
|}

== Official instructions by type ==

{| class="wikitable sortable" style="text-align: center"
!Type
!colspan=16 class="unsortable" | Instructions
|-
| style="text-align:left;" | Memory
| style="" | [[#MOV|MOV]]
| style="" | [[#XCHG|XCHG]]
| style="" | [[#XLAT|XLAT]]
| style="" | [[#LEA|LEA]]
| style="border-right:none;" | [[#LDS|LDS]]
| style="border-left:none;" | [[#LES|LES]]
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| colspan="8" |
|-
| style="text-align:left;" | Ports
| style="border-right:none;" | [[#IN|IN]]
| style="border-left:none;" | [[#OUT|OUT]]
| style="border-right:none;" | [[#INSB|INSB]]
| style="border-left:none;" | [[#OUTSB|OUTSB]]
| style="border-right:none;" | [[#INSW|INSW]]
| style="border-left:none;" | [[#OUTSW|OUTSW]]
| colspan="10" |
|-
| style="text-align:left;" | Arithmetic
| style="border-right:none;" | [[#ADD|ADD]]
| style="border-left:none;" | [[#SUB|SUB]]
| style="border-right:none;" | [[#ADC|ADC]]
| style="border-left:none;" | [[#SBB|SBB]]
| style="border-right:none;" | [[#INC|INC]]
| style="border-left:none;" | [[#DEC|DEC]]
| style="border-right:none;" | [[#MUL|MUL]]
| style="border-left:none;" | [[#DIV|DIV]]
| style="border-right:none;" | [[#IMUL|IMUL]]
| style="border-left:none;" | [[#IDIV|IDIV]]
| style="" | [[#CMP|CMP]]
| style="" | [[#NEG|NEG]]
| colspan="4" |
|-
| style="text-align:left;" | Numeric
| style="" | [[#CBW|CBW]]
| style="" | [[#CWD|CWD]]
| style="" | [[#AAA|AAA]]
| style="" | [[#AAS|AAS]]
| style="" | [[#AAM|AAM]]
| style="" | [[#AAD|AAD]]
| style="" | [[#DAA|DAA]]
| style="" | [[#DAS|DAS]]
| colspan="8" |
|-
| style="text-align:left;" | Shift
| style="border-right:none;" | [[#ROL|ROL]]
| style="border-left:none;" | [[#ROR|ROR]]
| style="border-right:none;" | [[#RCL|RCL]]
| style="border-left:none;" | [[#RCR|RCR]]
| style="border-right:none;" | [[#SHL|SHL]]
| style="border-left:none;" | [[#SHR|SHR]]
| style="" | [[#SAR|SAR]]
| colspan="9" |
|-
| style="text-align:left;" | Bitwise
| style="" | [[#AND|AND]]
| style="" | [[#OR|OR]]
| style="" | [[#XOR|XOR]]
| style="" | [[#NOT|NOT]]
| style="" | [[#TEST|TEST]]
| colspan="11" |
|-
| style="text-align:left;" | Branch
| style="border-right:none;" | [[#JC|JC]]
| style="border-left:none;" | [[#JNC|JNC]]
| style="border-right:none;" | [[#JZ|JZ]]
| style="border-left:none;" | [[#JNZ|JNZ]]
| style="border-right:none;" | [[#JBE|JBE]]
| style="border-left:none;" | [[#JA|JA]]
| style="border-right:none;" | [[#JO|JO]]
| style="border-left:none;" | [[#JNO|JNO]]
| style="border-right:none;" | [[#JP|JP]]
| style="border-left:none;" | [[#JNP|JNP]]
| style="border-right:none;" | [[#JS|JS]]
| style="border-left:none;" | [[#JNS|JNS]]
| style="border-right:none;" | [[#JL|JL]]
| style="border-left:none;" | [[#JGE|JGE]]
| style="border-right:none;" | [[#JLE|JLE]]
| style="border-left:none;" | [[#JG|JG]]
|-
| style="text-align:left;" | Jump
| style="" | [[#JMP|JMP]]
| style="border-right:none;" | [[#CALL|CALL]]
| style="border-left:none;border-right:none;" | [[#RET|RET]]
| style="border-left:none;" | [[#RETF|RETF]]
| colspan="12" |
|-
| style="text-align:left;" | Loop
| style="" | [[#LOOP|LOOP]]
| style="" | [[#LOOPE|LOOPE]]
| style="" | [[#LOOPNE|LOOPNE]]
| colspan="13" |
|-
| style="text-align:left;" | Interrupt
| style="border-right:none;" | [[#INT|INT]]
| style="border-left:none;" | [[#IRET|IRET]]
| style="" | [[#INTO|INTO]]
| style="" | [[#HLT|HLT]]
| style="" | [[#BOUND|BOUND]]
| colspan="11" |
|-
| style="text-align:left;" | Stack
| style="border-right:none;" | [[#PUSH|PUSH]]
| style="border-left:none;" | [[#POP|POP]]
| style="border-right:none;" | [[#PUSHA|PUSHA]]
| style="border-left:none;" | [[#POPA|POPA]]
| style="border-right:none;" | [[#PUSHF|PUSHF]]
| style="border-left:none;" | [[#POPF|POPF]]
| colspan="10" |
|-
| style="text-align:left;" | Flags
| style="border-right:none;" | [[#CLC|CLC]]
| style="border-left:none;" | [[#STC|STC]]
| style="border-right:none;" | [[#CLD|CLD]]
| style="border-left:none;" | [[#STD|STD]]
| style="border-right:none;" | [[#CLI|CLI]]
| style="border-left:none;" | [[#STI|STI]]
| style="" | [[#CMC|CMC]]
| style="border-right:none;" | [[#LAHF|LAHF]]
| style="border-left:none;" | [[#SAHF|SAHF]]
| colspan="7" |
|-
| style="text-align:left;" | Prefix
| style="" | [[#CS|CS]]
| style="" | [[#DS|DS]]
| style="" | [[#ES|ES]]
| style="" | [[#SS|SS]]
| colspan="12" |
|-
| style="text-align:left;" | String
| style="border-right:none;" | [[#REP|REP]]
| style="border-left:none;border-right:none;" | [[#REP|REPE]]
| style="border-left:none;" | [[#REPNE|REPNE]]
| style="" | [[#MOVSB|MOVSB]]
| style="" | [[#MOVSW|MOVSW]]
| style="border-right:none;" | [[#LODSB|LODSB]]
| style="border-left:none;" | [[#STOSB|STOSB]]
| style="border-right:none;" | [[#LODSW|LODSW]]
| style="border-left:none;" | [[#STOSW|STOSW]]
| style="" | [[#CMPSB|CMPSB]]
| style="" | [[#SCASB|SCASB]]
| style="" | [[#CMPSW|CMPSW]]
| style="" | [[#SCASW|SCASW]]
| colspan="3" |
|-
| style="text-align:left;" | Other
| style="" | [[#NOP|NOP]]
| style="border-right:none;" | [[#ENTER|ENTER]]
| style="border-left:none;" | [[#LEAVE|LEAVE]]
| style="" | [[#LOCK|LOCK]]
| style="" | [[#WAIT|WAIT]]
| colspan="11" |
|}

== Instruction encoding ==

=== ModR/M byte ===

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

* &lt;tt&gt;oo&lt;/tt&gt; - M'''o'''de;
* &lt;tt&gt;rrr&lt;/tt&gt; - Two possible functions:
** '''R'''egister (for addressing modes which require both a register and a register/memory operand),
** Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
* &lt;tt&gt;mmm&lt;/tt&gt; - Register/'''M'''emory.

The ''Mode'' and ''Register/Memory'' bitfields can refer to a memory location or to a register, as shown in the table below.

Some instructions define a second argument using the ''Register'' field. It is always interpreted as if ''Mode'' was equal to &lt;tt&gt;11&lt;/tt&gt; and, as such, can refer to a register only.

{| class="wikitable" style="text-align: center"
! R/M \ Mode
! &lt;tt&gt;00&lt;/tt&gt;
! &lt;tt&gt;01&lt;/tt&gt;
! &lt;tt&gt;10&lt;/tt&gt;
! &lt;tt&gt;11&lt;/tt&gt; ''(byte)''
! &lt;tt&gt;11&lt;/tt&gt; ''(word)''
|-
| &lt;tt&gt;000&lt;/tt&gt;
| DS:[BX + SI]
| DS:[BX + SI + disp8]
| DS:[BX + SI + disp16]
| AL
| AX
|-
| &lt;tt&gt;001&lt;/tt&gt;
| DS:[BX + DI]
| DS:[BX + DI + disp8]
| DS:[BX + DI + disp16]
| CL
| CX
|-
| &lt;tt&gt;010&lt;/tt&gt;
| SS:[BP + SI]
| SS:[BP + SI + disp8]
| SS:[BP + SI + disp16]
| DL
| DX
|-
| &lt;tt&gt;011&lt;/tt&gt;
| SS:[BP + DI]
| SS:[BP + DI + disp8]
| SS:[BP + DI + disp16]
| BL
| BX
|-
| &lt;tt&gt;100&lt;/tt&gt;
| DS:[SI]
| DS:[SI + disp8]
| DS:[SI + disp16]
| AH
| SP
|-
| &lt;tt&gt;101&lt;/tt&gt;
| DS:[DI]
| DS:[DI + disp8]
| DS:[DI + disp16]
| CH
| BP
|-
| &lt;tt&gt;110&lt;/tt&gt;
| ''DS:[disp16]''
| SS:[BP + disp8]
| SS:[BP + disp16]
| DH
| SI
|-
| &lt;tt&gt;111&lt;/tt&gt;
| DS:[BX]
| DS:[BX + disp8]
| DS:[BX + disp16]
| BH
| DI
|}

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (&lt;tt&gt;oo&lt;/tt&gt; = &lt;tt&gt;00&lt;/tt&gt;, &lt;tt&gt;mmm&lt;/tt&gt; = &lt;tt&gt;110&lt;/tt&gt;) is a special case, in which the ''disp16'' value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as &lt;tt&gt;oorrrmmm&lt;/tt&gt; (binary), &lt;tt&gt;/r&lt;/tt&gt; (hexadecimal) or &lt;tt&gt;/0&lt;/tt&gt; (hexademical, &lt;tt&gt;rrr&lt;/tt&gt; used as function &lt;tt&gt;0&lt;/tt&gt;).

== Official instructions ==

{{Anchor|AAA}}
=== AAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAA || &lt;tt&gt;37&lt;/tt&gt; || &lt;tt&gt;00110111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|AAD}}
=== AAD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAD imm8 || &lt;tt&gt;B5 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|AAM}}
=== AAM ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAM imm8 || &lt;tt&gt;B4 ii&lt;/tt&gt; || &lt;tt&gt;11010100 iiiiiiii&lt;/tt&gt; || 2 || 17
|}

----
{{Anchor|AAS}}
=== AAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AAS || &lt;tt&gt;3F&lt;/tt&gt; || &lt;tt&gt;00111111&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ADC}}
=== ADC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADC AL, imm || &lt;tt&gt;14 ii&lt;/tt&gt; || &lt;tt&gt;00010100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADC AX, imm || &lt;tt&gt;15 ii ii&lt;/tt&gt; || &lt;tt&gt;00010101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC mem8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADC mem16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADC mem8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;00010000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC mem16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;00010001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADC reg8, imm8 || &lt;tt&gt;80 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg16, imm16 || &lt;tt&gt;81 /2 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11010mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADC reg16, simm8 || &lt;tt&gt;83 /2 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADC reg8, mem8 || &lt;tt&gt;12 /r&lt;/tt&gt; || &lt;tt&gt;00010010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg16, mem16 || &lt;tt&gt;13 /r&lt;/tt&gt; || &lt;tt&gt;00010011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADC reg8, reg8 || &lt;tt&gt;10 /r&lt;/tt&gt; || &lt;tt&gt;000100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADC reg16, reg16 || &lt;tt&gt;11 /r&lt;/tt&gt; || &lt;tt&gt;000100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|ADD}}
=== ADD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ADD AL, imm || &lt;tt&gt;04 ii&lt;/tt&gt; || &lt;tt&gt;00000100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| ADD AX, imm || &lt;tt&gt;05 ii ii&lt;/tt&gt; || &lt;tt&gt;00000101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD mem8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| ADD mem16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| ADD mem8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;00000000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD mem16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;00000001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| ADD reg8, imm8 || &lt;tt&gt;80 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg16, imm16 || &lt;tt&gt;81 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| ADD reg16, simm8 || &lt;tt&gt;83 /0 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| ADD reg8, mem8 || &lt;tt&gt;02 /r&lt;/tt&gt; || &lt;tt&gt;00000010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg16, mem16 || &lt;tt&gt;03 /r&lt;/tt&gt; || &lt;tt&gt;00000011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| ADD reg8, reg8 || &lt;tt&gt;00 /r&lt;/tt&gt; || &lt;tt&gt;000000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| ADD reg16, reg16 || &lt;tt&gt;01 /r&lt;/tt&gt; || &lt;tt&gt;000000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|AND}}
=== AND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| AND AL, imm || &lt;tt&gt;24 ii&lt;/tt&gt; || &lt;tt&gt;00100100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| AND AX, imm || &lt;tt&gt;25 ii ii&lt;/tt&gt; || &lt;tt&gt;00100101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND mem8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| AND mem16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| AND mem8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;00100000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND mem16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;00100001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| AND reg8, imm8 || &lt;tt&gt;80 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg16, imm16 || &lt;tt&gt;81 /4 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11100mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| AND reg16, simm8 || &lt;tt&gt;83 /4 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| AND reg8, mem8 || &lt;tt&gt;22 /r&lt;/tt&gt; || &lt;tt&gt;00100010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg16, mem16 || &lt;tt&gt;23 /r&lt;/tt&gt; || &lt;tt&gt;00100011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| AND reg8, reg8 || &lt;tt&gt;20 /r&lt;/tt&gt; || &lt;tt&gt;001000.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| AND reg16, reg16 || &lt;tt&gt;21 /r&lt;/tt&gt; || &lt;tt&gt;001000.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|BOUND}}
=== BOUND ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| BOUND reg16, mem16:16 || &lt;tt&gt;62 /r&lt;/tt&gt; || &lt;tt&gt;01100010 oorrrmmm&lt;/tt&gt; || 2+ || 13 (20 if condition met)
|}

----
{{Anchor|CALL}}
=== CALL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CALL ptr16:16 || &lt;tt&gt;CA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;10011010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 10
|-
| CALL mem16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 6
|-
| CALL mem16:16 || &lt;tt&gt;FF /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 12
|-
| CALL reg16 || &lt;tt&gt;FF /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 5
|-
| CALL rel16 || &lt;tt&gt;E8 ii ii&lt;/tt&gt; || &lt;tt&gt;11101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 5
|}

----
{{Anchor|CBW}}
=== CBW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CBW || &lt;tt&gt;98&lt;/tt&gt; || &lt;tt&gt;10011000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CLC}}
=== CLC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLC || &lt;tt&gt;F8&lt;/tt&gt; || &lt;tt&gt;11111000&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLD}}
=== CLD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLD || &lt;tt&gt;FC&lt;/tt&gt; || &lt;tt&gt;11111100&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CLI}}
=== CLI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 0
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CLI || &lt;tt&gt;FA&lt;/tt&gt; || &lt;tt&gt;11111010&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMC}}
=== CMC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || !CF
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMC || &lt;tt&gt;F5&lt;/tt&gt; || &lt;tt&gt;11110101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|CMP}}
=== CMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMP AL, imm || &lt;tt&gt;3C ii&lt;/tt&gt; || &lt;tt&gt;00111100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| CMP AX, imm || &lt;tt&gt;3D ii ii&lt;/tt&gt; || &lt;tt&gt;00111101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP mem8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| CMP mem16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| CMP mem8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;00111000 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP mem16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;00111001 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, imm8 || &lt;tt&gt;80 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg16, imm16 || &lt;tt&gt;81 /7 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11111mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| CMP reg16, simm8 || &lt;tt&gt;83 /7 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| CMP reg8, mem8 || &lt;tt&gt;3A /r&lt;/tt&gt; || &lt;tt&gt;00111010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg16, mem16 || &lt;tt&gt;3B /r&lt;/tt&gt; || &lt;tt&gt;00111011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| CMP reg8, reg8 || &lt;tt&gt;38 /r&lt;/tt&gt; || &lt;tt&gt;001110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| CMP reg16, reg16 || &lt;tt&gt;39 /r&lt;/tt&gt; || &lt;tt&gt;001110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|CMPSB}}
{{Anchor|CMPSW}}
=== CMPSB/CMPSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CMPSB || &lt;tt&gt;A6&lt;/tt&gt; || &lt;tt&gt;10100110&lt;/tt&gt; || 1 || 6
|-
| CMPSW || &lt;tt&gt;A7&lt;/tt&gt; || &lt;tt&gt;10100111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|CS}}
=== CS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CS || &lt;tt&gt;2E&lt;/tt&gt; || &lt;tt&gt;00101110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|CWD}}
=== CWD ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| CWD || &lt;tt&gt;99&lt;/tt&gt; || &lt;tt&gt;10011001&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DAA}}
=== DAA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAA || &lt;tt&gt;27&lt;/tt&gt; || &lt;tt&gt;00100111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DAS}}
=== DAS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DAS || &lt;tt&gt;2F&lt;/tt&gt; || &lt;tt&gt;00101111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|DEC}}
=== DEC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC mem16 || &lt;tt&gt;FF /1&lt;/tt&gt; || &lt;tt&gt;11111111 oo001mmm&lt;/tt&gt; || 2+ || 3
|-
| DEC reg8 || &lt;tt&gt;FE /1&lt;/tt&gt; || &lt;tt&gt;11111110 11001mmm&lt;/tt&gt; || 2+ || 1
|-
| DEC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01001rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|DIV}}
=== DIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11110110 oo110mmm&lt;/tt&gt; || 2+ || 16
|-
| DIV mem16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 24
|-
| DIV reg8 || &lt;tt&gt;F6 /6&lt;/tt&gt; || &lt;tt&gt;11111110 11110mmm&lt;/tt&gt; || 2 || 15
|-
| DIV reg16 || &lt;tt&gt;F7 /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 23
|}

----
{{Anchor|DS}}
=== DS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || &lt;tt&gt;3E&lt;/tt&gt; || &lt;tt&gt;00111110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|ENTER}}
=== ENTER ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ENTER imm16, imm8 || &lt;tt&gt;C8 ii ii jj&lt;/tt&gt; || &lt;tt&gt;11001000 iiiiiiii iiiiiiii jjjjjjjj&lt;/tt&gt; || 3 || 8 (imm8 = 0)&lt;br/&gt;14 (imm8 = 1)&lt;br/&gt;15 + imm8 * 4 (imm8 &gt;= 2)
|}

----
{{Anchor|ES}}
=== ES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || &lt;tt&gt;26&lt;/tt&gt; || &lt;tt&gt;00100110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|HLT}}
=== HLT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || &lt;tt&gt;F4&lt;/tt&gt; || &lt;tt&gt;11110100&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|IDIV}}
=== IDIV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11110110 oo111mmm&lt;/tt&gt; || 2+ || 18
|-
| IDIV mem16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 oo111mmm&lt;/tt&gt; || 2+ || 25
|-
| IDIV reg8 || &lt;tt&gt;F6 /7&lt;/tt&gt; || &lt;tt&gt;11111110 11111mmm&lt;/tt&gt; || 2 || 17
|-
| IDIV reg16 || &lt;tt&gt;F7 /7&lt;/tt&gt; || &lt;tt&gt;11111111 11111mmm&lt;/tt&gt; || 2 || 24
|}

----
{{Anchor|IMUL}}
=== IMUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IMUL mem8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11110110 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL mem16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 4
|-
| IMUL reg8 || &lt;tt&gt;F6 /5&lt;/tt&gt; || &lt;tt&gt;11111110 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16 || &lt;tt&gt;F7 /5&lt;/tt&gt; || &lt;tt&gt;11111111 11101mmm&lt;/tt&gt; || 2 || 3
|-
| IMUL reg16, mem16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 4
|-
| IMUL reg16, mem16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 oorrrmmm iiiiiiii&lt;/tt&gt; || 3 || 4
|-
| IMUL reg16, reg16, imm16 || &lt;tt&gt;69 /r ii ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 3
|-
| IMUL reg16, reg16, simm8 || &lt;tt&gt;6B /r ii&lt;/tt&gt; || &lt;tt&gt;11111111 11rrrmmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|IN}}
=== IN ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || &lt;tt&gt;EC&lt;/tt&gt; || &lt;tt&gt;11101100&lt;/tt&gt; || 1 || 6
|-
| IN AX, DX || &lt;tt&gt;ED&lt;/tt&gt; || &lt;tt&gt;11101101&lt;/tt&gt; || 1 || 6
|-
| IN AL, imm8 || &lt;tt&gt;E4 ii&lt;/tt&gt; || &lt;tt&gt;11100100 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| IN AX, imm8 || &lt;tt&gt;E5 ii&lt;/tt&gt; || &lt;tt&gt;11100101 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|INC}}
=== INC ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC mem16 || &lt;tt&gt;FF /0&lt;/tt&gt; || &lt;tt&gt;11111111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| INC reg8 || &lt;tt&gt;FE /0&lt;/tt&gt; || &lt;tt&gt;11111110 11000mmm&lt;/tt&gt; || 2+ || 1
|-
| INC reg16 || &lt;tt&gt;4x&lt;/tt&gt; || &lt;tt&gt;01000rrr&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|INSB}}
{{Anchor|INSW}}
=== INSB/INSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INSB || &lt;tt&gt;6C&lt;/tt&gt; || &lt;tt&gt;01101100&lt;/tt&gt; || 1 || 6
|-
| INSW || &lt;tt&gt;6D&lt;/tt&gt; || &lt;tt&gt;01101101&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|INT}}
=== INT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INT 3 || &lt;tt&gt;CC&lt;/tt&gt; || &lt;tt&gt;11001100&lt;/tt&gt; || 1 || 9
|-
| INT imm8 || &lt;tt&gt;CD ii&lt;/tt&gt; || &lt;tt&gt;11001101 iiiiiiii&lt;/tt&gt; || 2 || 10
|}

----
{{Anchor|INTO}}
=== INTO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INTO || &lt;tt&gt;CE&lt;/tt&gt; || &lt;tt&gt;11001110&lt;/tt&gt; || 1 || 6 (13 if OF = 1)
|}

----
{{Anchor|IRET}}
=== IRET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IRET || &lt;tt&gt;CF&lt;/tt&gt; || &lt;tt&gt;11001111&lt;/tt&gt; || 1 || 10
|}

----
{{Anchor|JA}}
=== JA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;77 ii&lt;/tt&gt; || &lt;tt&gt;01110111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JBE}}
=== JBE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JA rel8 || &lt;tt&gt;76 ii&lt;/tt&gt; || &lt;tt&gt;01110110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JC}}
=== JC/JB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JC rel8 || &lt;tt&gt;72 ii&lt;/tt&gt; || &lt;tt&gt;01110010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JCXZ}}
=== JCXZ ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JCXZ rel8 || &lt;tt&gt;E3 ii&lt;/tt&gt; || &lt;tt&gt;11100011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JG}}
=== JG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JG rel8 || &lt;tt&gt;7F ii&lt;/tt&gt; || &lt;tt&gt;01111111 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JGE}}
=== JGE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JGE rel8 || &lt;tt&gt;7D ii&lt;/tt&gt; || &lt;tt&gt;01111101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JL}}
=== JL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JL rel8 || &lt;tt&gt;7C ii&lt;/tt&gt; || &lt;tt&gt;01111100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JLE}}
=== JLE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JLE rel8 || &lt;tt&gt;7E ii&lt;/tt&gt; || &lt;tt&gt;01111110 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JMP}}
=== JMP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JMP ptr16:16 || &lt;tt&gt;EA oo oo ss ss&lt;/tt&gt; || &lt;tt&gt;11101010 oooooooo oooooooo ssssssss ssssssss&lt;/tt&gt; || 5 || 7
|-
| JMP mem16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 5
|-
| JMP mem16:16 || &lt;tt&gt;FF /5&lt;/tt&gt; || &lt;tt&gt;11111111 oo101mmm&lt;/tt&gt; || 2+ || 10
|-
| JMP reg16 || &lt;tt&gt;FF /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 4
|-
| JMP rel8 || &lt;tt&gt;EB ii&lt;/tt&gt; || &lt;tt&gt;11101011 iiiiiiii&lt;/tt&gt; || 2 || 4
|-
| JMP rel16 || &lt;tt&gt;E9 ii ii&lt;/tt&gt; || &lt;tt&gt;11101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 4
|}

----
{{Anchor|JNC}}
=== JNC/JAE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNC rel8 || &lt;tt&gt;73 ii&lt;/tt&gt; || &lt;tt&gt;01110011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNO}}
=== JNO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNO rel8 || &lt;tt&gt;71 ii&lt;/tt&gt; || &lt;tt&gt;01110001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNP}}
=== JNP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNP rel8 || &lt;tt&gt;7B ii&lt;/tt&gt; || &lt;tt&gt;01111011 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNS}}
=== JNS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNS rel8 || &lt;tt&gt;79 ii&lt;/tt&gt; || &lt;tt&gt;01111001 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JNZ}}
=== JNZ/JNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JNZ rel8 || &lt;tt&gt;75 ii&lt;/tt&gt; || &lt;tt&gt;01110101 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JO}}
=== JO ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JO rel8 || &lt;tt&gt;70 ii&lt;/tt&gt; || &lt;tt&gt;01110000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JP}}
=== JP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JP rel8 || &lt;tt&gt;7A ii&lt;/tt&gt; || &lt;tt&gt;01111010 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JS}}
=== JS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JS rel8 || &lt;tt&gt;78 ii&lt;/tt&gt; || &lt;tt&gt;01111000 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|JZ}}
=== JZ/JE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| JZ rel8 || &lt;tt&gt;74 ii&lt;/tt&gt; || &lt;tt&gt;01110100 iiiiiiii&lt;/tt&gt; || 2 || 1 (4 if branch taken)
|}

----
{{Anchor|LAHF}}
=== LAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LAHF || &lt;tt&gt;9F&lt;/tt&gt; || &lt;tt&gt;10011111&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LDS}}
=== LDS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LDS reg16, mem16 || &lt;tt&gt;C5 /r&lt;/tt&gt; || &lt;tt&gt;11000101 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LEA}}
=== LEA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEA reg16, mem16 || &lt;tt&gt;8D /r&lt;/tt&gt; || &lt;tt&gt;10001101 oorrrmmm&lt;/tt&gt; || 2+ || 1
|}

----
{{Anchor|LEAVE}}
=== LEAVE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || &lt;tt&gt;C9&lt;/tt&gt; || &lt;tt&gt;11001001&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|LES}}
=== LES ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LES reg16, mem16 || &lt;tt&gt;C4 /r&lt;/tt&gt; || &lt;tt&gt;11000100 oorrrmmm&lt;/tt&gt; || 2+ || 6
|}

----
{{Anchor|LOCK}}
=== LOCK ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOCK || &lt;tt&gt;F0&lt;/tt&gt; || &lt;tt&gt;11110000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|LODSB}}
{{Anchor|LODSW}}
=== LODSB/LODSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LODSB || &lt;tt&gt;AC&lt;/tt&gt; || &lt;tt&gt;10101100&lt;/tt&gt; || 1 || 3
|-
| LODSW || &lt;tt&gt;AD&lt;/tt&gt; || &lt;tt&gt;10101101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|LOOP}}
=== LOOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || &lt;tt&gt;E2 ii&lt;/tt&gt; || &lt;tt&gt;11100010 iiiiiiii&lt;/tt&gt; || 2 || 2 (5 if branch taken)
|}

----
{{Anchor|LOOPE}}
=== LOOPE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || &lt;tt&gt;E1 ii&lt;/tt&gt; || &lt;tt&gt;11100001 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|LOOPNE}}
=== LOOPNE ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || &lt;tt&gt;E0 ii&lt;/tt&gt; || &lt;tt&gt;11100000 iiiiiiii&lt;/tt&gt; || 2 || 3 (6 if branch taken)
|}

----
{{Anchor|MOV}}
=== MOV ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOV AL, ptr16 || &lt;tt&gt;A0 ii ii&lt;/tt&gt; || &lt;tt&gt;10100000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV AX, ptr16 || &lt;tt&gt;A1 ii ii&lt;/tt&gt; || &lt;tt&gt;10100001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV mem8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 1
|-
| MOV mem16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 1
|-
| MOV mem8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;10001000 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;10001001 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV mem16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 oo0rrmmm&lt;/tt&gt; || 2+ || 3
|-
| MOV ptr16, AL || &lt;tt&gt;A2 ii ii&lt;/tt&gt; || &lt;tt&gt;10100010 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV ptr16, AX || &lt;tt&gt;A3 ii ii&lt;/tt&gt; || &lt;tt&gt;10100011 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10110rrr iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| MOV reg8, imm8 || &lt;tt&gt;C6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;Bx ii&lt;/tt&gt; || &lt;tt&gt;10111rrr iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| MOV reg16, imm16 || &lt;tt&gt;C7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11000111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| MOV reg8, mem8 || &lt;tt&gt;8A /r&lt;/tt&gt; || &lt;tt&gt;10001010 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg16, mem16 || &lt;tt&gt;8B /r&lt;/tt&gt; || &lt;tt&gt;10001011 oorrrmmm&lt;/tt&gt; || 2+ || 1
|-
| MOV reg8, reg8 || &lt;tt&gt;88 /r&lt;/tt&gt; || &lt;tt&gt;100010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, reg16 || &lt;tt&gt;89 /r&lt;/tt&gt; || &lt;tt&gt;100010.1 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV reg16, sreg16 || &lt;tt&gt;8C /r&lt;/tt&gt; || &lt;tt&gt;10001100 110rrmmm&lt;/tt&gt; || 2 || 1
|-
| MOV sreg16, mem16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 oo0rrmmm&lt;/tt&gt; || 2 || 3
|-
| MOV sreg16, reg16 || &lt;tt&gt;8E /r&lt;/tt&gt; || &lt;tt&gt;10001110 110rrmmm&lt;/tt&gt; || 2+ || 2
|}

----
{{Anchor|MOVSB}}
{{Anchor|MOVSW}}

=== MOVSB/MOVSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MOVSB || &lt;tt&gt;A4&lt;/tt&gt; || &lt;tt&gt;10100100&lt;/tt&gt; || 1 || 5
|-
| MOVSW || &lt;tt&gt;A5&lt;/tt&gt; || &lt;tt&gt;10100101&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|MUL}}
=== MUL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| MUL mem8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11110110 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL mem16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 oo100mmm&lt;/tt&gt; || 2+ || 4
|-
| MUL reg8 || &lt;tt&gt;F6 /4&lt;/tt&gt; || &lt;tt&gt;11111110 11100mmm&lt;/tt&gt; || 2 || 3
|-
| MUL reg16 || &lt;tt&gt;F7 /4&lt;/tt&gt; || &lt;tt&gt;11111111 11100mmm&lt;/tt&gt; || 2 || 3
|}

----
{{Anchor|NEG}}
=== NEG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NEG mem8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11110110 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG mem16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 oo011mmm&lt;/tt&gt; || 2+ || 3
|-
| NEG reg8 || &lt;tt&gt;F6 /3&lt;/tt&gt; || &lt;tt&gt;11111110 11011mmm&lt;/tt&gt; || 2 || 1
|-
| NEG reg16 || &lt;tt&gt;F7 /3&lt;/tt&gt; || &lt;tt&gt;11111111 11011mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|NOP}}
=== NOP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOP || &lt;tt&gt;90&lt;/tt&gt; || &lt;tt&gt;10010000&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|NOT}}

=== NOT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| NOT mem8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11110110 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT mem16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 oo010mmm&lt;/tt&gt; || 2+ || 3
|-
| NOT reg8 || &lt;tt&gt;F6 /2&lt;/tt&gt; || &lt;tt&gt;11111110 11010mmm&lt;/tt&gt; || 2 || 1
|-
| NOT reg16 || &lt;tt&gt;F7 /2&lt;/tt&gt; || &lt;tt&gt;11111111 11010mmm&lt;/tt&gt; || 2 || 1
|}

----
{{Anchor|OR}}
=== OR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OR AL, imm || &lt;tt&gt;0C ii&lt;/tt&gt; || &lt;tt&gt;00001100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| OR AX, imm || &lt;tt&gt;0D ii ii&lt;/tt&gt; || &lt;tt&gt;00001101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| OR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| OR mem8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;00001000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR mem16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;00001001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| OR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11001mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| OR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| OR reg8, mem8 || &lt;tt&gt;0A /r&lt;/tt&gt; || &lt;tt&gt;00001010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg16, mem16 || &lt;tt&gt;0B /r&lt;/tt&gt; || &lt;tt&gt;00001011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| OR reg8, reg8 || &lt;tt&gt;08 /r&lt;/tt&gt; || &lt;tt&gt;000010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| OR reg16, reg16 || &lt;tt&gt;09 /r&lt;/tt&gt; || &lt;tt&gt;000010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|OUT}}
=== OUT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT DX, AL || &lt;tt&gt;EE&lt;/tt&gt; || &lt;tt&gt;11101110&lt;/tt&gt; || 1 || 6
|-
| OUT DX, AX || &lt;tt&gt;EF&lt;/tt&gt; || &lt;tt&gt;11101111&lt;/tt&gt; || 1 || 6
|-
| OUT imm8, AL || &lt;tt&gt;E6 ii&lt;/tt&gt; || &lt;tt&gt;11100110 iiiiiiii&lt;/tt&gt; || 2 || 6
|-
| OUT imm8, AX || &lt;tt&gt;E7 ii&lt;/tt&gt; || &lt;tt&gt;11100111 iiiiiiii&lt;/tt&gt; || 2 || 6
|}

----
{{Anchor|OUTSB}}
{{Anchor|OUTSW}}

=== OUTSB/OUTSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUTSB || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 6
|-
| OUTSW || &lt;tt&gt;6F&lt;/tt&gt; || &lt;tt&gt;01101111&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|POP}}
=== POP ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POP mem16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 oo000mmm&lt;/tt&gt; || 2+ || 3
|-
| POP reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01011xxx&lt;/tt&gt; || 1 || 1
|-
| POP reg16 || &lt;tt&gt;8F /0&lt;/tt&gt; || &lt;tt&gt;10001111 11000mmm&lt;/tt&gt; || 2 || 1
|-
| POP sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx111&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|POPA}}
=== POPA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPA || &lt;tt&gt;61&lt;/tt&gt; || &lt;tt&gt;01100001&lt;/tt&gt; || 1 || 8
|}

----
{{Anchor|POPF}}
=== POPF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| POPF || &lt;tt&gt;9D&lt;/tt&gt; || &lt;tt&gt;10011101&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|PUSH}}
=== PUSH ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSH simm8 || &lt;tt&gt;6A ii&lt;/tt&gt; || &lt;tt&gt;01101010 iiiiiiii&lt;/tt&gt; || 2 ||  1
|-
| PUSH imm16 || &lt;tt&gt;68 ii ii&lt;/tt&gt; || &lt;tt&gt;01101000 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| PUSH mem16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 oo110mmm&lt;/tt&gt; || 2+ || 2
|-
| PUSH reg16 || &lt;tt&gt;5x&lt;/tt&gt; || &lt;tt&gt;01010xxx&lt;/tt&gt; || 1 || 1
|-
| PUSH reg16 || &lt;tt&gt;FF /6&lt;/tt&gt; || &lt;tt&gt;11111111 11110mmm&lt;/tt&gt; || 2 || 1
|-
| PUSH sreg16 || &lt;tt&gt;xx&lt;/tt&gt; || &lt;tt&gt;000xx110&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|PUSHA}}
=== PUSHA ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHA || &lt;tt&gt;60&lt;/tt&gt; || &lt;tt&gt;01100000&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|PUSHF}}
=== PUSHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| PUSHF || &lt;tt&gt;9C&lt;/tt&gt; || &lt;tt&gt;10011100&lt;/tt&gt; || 1 || 2
|}

----
{{Anchor|RCL}}
=== RCL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCL mem8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL mem16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 oo010rm&lt;/tt&gt; || 2+ || 3
|-
| RCL mem16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 oo010rm&lt;/tt&gt; || 2+ || 5
|-
| RCL mem16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo010mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCL reg8, 1 || &lt;tt&gt;D0 /2&lt;/tt&gt; || &lt;tt&gt;11010000 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg8, CL || &lt;tt&gt;D2 /2&lt;/tt&gt; || &lt;tt&gt;11010010 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg8, imm8 || &lt;tt&gt;C0 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCL reg16, 1 || &lt;tt&gt;D1 /2&lt;/tt&gt; || &lt;tt&gt;11010001 11010rm&lt;/tt&gt; || 2 || 1
|-
| RCL reg16, CL || &lt;tt&gt;D3 /2&lt;/tt&gt; || &lt;tt&gt;11010011 11010rm&lt;/tt&gt; || 2 || 3
|-
| RCL reg16, imm8 || &lt;tt&gt;C1 /2 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11010mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|RCR}}
=== RCR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RCR mem8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR mem16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 oo011rm&lt;/tt&gt; || 2+ || 3
|-
| RCR mem16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 oo011rm&lt;/tt&gt; || 2+ || 5
|-
| RCR mem16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| RCR reg8, 1 || &lt;tt&gt;D0 /3&lt;/tt&gt; || &lt;tt&gt;11010000 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg8, CL || &lt;tt&gt;D2 /3&lt;/tt&gt; || &lt;tt&gt;11010010 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg8, imm8 || &lt;tt&gt;C0 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| RCR reg16, 1 || &lt;tt&gt;D1 /3&lt;/tt&gt; || &lt;tt&gt;11010001 11011rm&lt;/tt&gt; || 2 || 1
|-
| RCR reg16, CL || &lt;tt&gt;D3 /3&lt;/tt&gt; || &lt;tt&gt;11010011 11011rm&lt;/tt&gt; || 2 || 3
|-
| RCR reg16, imm8 || &lt;tt&gt;C1 /3 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|REP}}
=== REP/REPE/REPZ ===

----
{{Anchor|REPNE}}
=== REPNE/REPNZ ===

----
{{Anchor|RET}}
=== RET ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RET || &lt;tt&gt;C3&lt;/tt&gt; || &lt;tt&gt;11000011&lt;/tt&gt; || 1 || 6
|-
| RET imm16 || &lt;tt&gt;C2 ii ii&lt;/tt&gt; || &lt;tt&gt;11000010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 6
|}

----
{{Anchor|RETF}}
=== RETF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| RETF || &lt;tt&gt;CB&lt;/tt&gt; || &lt;tt&gt;11001011&lt;/tt&gt; || 1 || 8
|-
| RETF imm16 || &lt;tt&gt;CA ii ii&lt;/tt&gt; || &lt;tt&gt;11001010 iiiiiiii iiiiiiii&lt;/tt&gt; || 1 || 9
|}

----
{{Anchor|ROL}}

=== ROL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROL mem8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL mem16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 oo000rm&lt;/tt&gt; || 2+ || 3
|-
| ROL mem16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 oo000rm&lt;/tt&gt; || 2+ || 5
|-
| ROL mem16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROL reg8, 1 || &lt;tt&gt;D0 /0&lt;/tt&gt; || &lt;tt&gt;11010000 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg8, CL || &lt;tt&gt;D2 /0&lt;/tt&gt; || &lt;tt&gt;11010010 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg8, imm8 || &lt;tt&gt;C0 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROL reg16, 1 || &lt;tt&gt;D1 /0&lt;/tt&gt; || &lt;tt&gt;11010001 11000rm&lt;/tt&gt; || 2 || 1
|-
| ROL reg16, CL || &lt;tt&gt;D3 /0&lt;/tt&gt; || &lt;tt&gt;11010011 11000rm&lt;/tt&gt; || 2 || 3
|-
| ROL reg16, imm8 || &lt;tt&gt;C1 /0 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|ROR}}

=== ROR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ROR mem8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR mem16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 oo001rm&lt;/tt&gt; || 2+ || 3
|-
| ROR mem16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 oo001rm&lt;/tt&gt; || 2+ || 5
|-
| ROR mem16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo001mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| ROR reg8, 1 || &lt;tt&gt;D0 /1&lt;/tt&gt; || &lt;tt&gt;11010000 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg8, CL || &lt;tt&gt;D2 /1&lt;/tt&gt; || &lt;tt&gt;11010010 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg8, imm8 || &lt;tt&gt;C0 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| ROR reg16, 1 || &lt;tt&gt;D1 /1&lt;/tt&gt; || &lt;tt&gt;11010001 11001rm&lt;/tt&gt; || 2 || 1
|-
| ROR reg16, CL || &lt;tt&gt;D3 /1&lt;/tt&gt; || &lt;tt&gt;11010011 11001rm&lt;/tt&gt; || 2 || 3
|-
| ROR reg16, imm8 || &lt;tt&gt;C1 /1 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11001mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SAHF}}
=== SAHF ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAHF || &lt;tt&gt;9E&lt;/tt&gt; || &lt;tt&gt;10011110&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SAR}}
=== SAR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SAR mem8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR mem16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 oo111rm&lt;/tt&gt; || 2+ || 3
|-
| SAR mem16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 oo111rm&lt;/tt&gt; || 2+ || 5
|-
| SAR mem16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo111mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SAR reg8, 1 || &lt;tt&gt;D0 /7&lt;/tt&gt; || &lt;tt&gt;11010000 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg8, CL || &lt;tt&gt;D2 /7&lt;/tt&gt; || &lt;tt&gt;11010010 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg8, imm8 || &lt;tt&gt;C0 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SAR reg16, 1 || &lt;tt&gt;D1 /7&lt;/tt&gt; || &lt;tt&gt;11010001 11111rm&lt;/tt&gt; || 2 || 1
|-
| SAR reg16, CL || &lt;tt&gt;D3 /7&lt;/tt&gt; || &lt;tt&gt;11010011 11111rm&lt;/tt&gt; || 2 || 3
|-
| SAR reg16, imm8 || &lt;tt&gt;C1 /7 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11111mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SBB}}
=== SBB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SBB AL, imm || &lt;tt&gt;1C ii&lt;/tt&gt; || &lt;tt&gt;00011100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SBB AX, imm || &lt;tt&gt;1D ii ii&lt;/tt&gt; || &lt;tt&gt;00011101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB mem8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SBB mem16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo011mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SBB mem8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;00011000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB mem16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;00011001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SBB reg8, imm8 || &lt;tt&gt;80 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg16, imm16 || &lt;tt&gt;81 /3 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11011mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SBB reg16, simm8 || &lt;tt&gt;83 /3 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11011mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SBB reg8, mem8 || &lt;tt&gt;1A /r&lt;/tt&gt; || &lt;tt&gt;00011010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg16, mem16 || &lt;tt&gt;1B /r&lt;/tt&gt; || &lt;tt&gt;00011011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SBB reg8, reg8 || &lt;tt&gt;18 /r&lt;/tt&gt; || &lt;tt&gt;000110.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SBB reg16, reg16 || &lt;tt&gt;19 /r&lt;/tt&gt; || &lt;tt&gt;000110.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|SCASB}}
{{Anchor|SCASW}}
=== SCASB/SCASW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SCASB || &lt;tt&gt;AE&lt;/tt&gt; || &lt;tt&gt;10101110&lt;/tt&gt; || 1 || 4
|-
| SCASW || &lt;tt&gt;AF&lt;/tt&gt; || &lt;tt&gt;10101111&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|SHL}}
=== SHL ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHL mem8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL mem16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 oo100rm&lt;/tt&gt; || 2+ || 3
|-
| SHL mem16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 oo100rm&lt;/tt&gt; || 2+ || 5
|-
| SHL mem16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo100mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHL reg8, 1 || &lt;tt&gt;D0 /4&lt;/tt&gt; || &lt;tt&gt;11010000 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg8, CL || &lt;tt&gt;D2 /4&lt;/tt&gt; || &lt;tt&gt;11010010 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg8, imm8 || &lt;tt&gt;C0 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHL reg16, 1 || &lt;tt&gt;D1 /4&lt;/tt&gt; || &lt;tt&gt;11010001 11100rm&lt;/tt&gt; || 2 || 1
|-
| SHL reg16, CL || &lt;tt&gt;D3 /4&lt;/tt&gt; || &lt;tt&gt;11010011 11100rm&lt;/tt&gt; || 2 || 3
|-
| SHL reg16, imm8 || &lt;tt&gt;C1 /4 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11100mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SHR}}
=== SHR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SHR mem8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR mem16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 oo101rm&lt;/tt&gt; || 2+ || 3
|-
| SHR mem16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 oo101rm&lt;/tt&gt; || 2+ || 5
|-
| SHR mem16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 5
|-
| SHR reg8, 1 || &lt;tt&gt;D0 /5&lt;/tt&gt; || &lt;tt&gt;11010000 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg8, CL || &lt;tt&gt;D2 /5&lt;/tt&gt; || &lt;tt&gt;11010010 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg8, imm8 || &lt;tt&gt;C0 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|-
| SHR reg16, 1 || &lt;tt&gt;D1 /5&lt;/tt&gt; || &lt;tt&gt;11010001 11101rm&lt;/tt&gt; || 2 || 1
|-
| SHR reg16, CL || &lt;tt&gt;D3 /5&lt;/tt&gt; || &lt;tt&gt;11010011 11101rm&lt;/tt&gt; || 2 || 3
|-
| SHR reg16, imm8 || &lt;tt&gt;C1 /5 ii&lt;/tt&gt; || &lt;tt&gt;11000001 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 3
|}

----
{{Anchor|SS}}
=== SS ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SS || &lt;tt&gt;36&lt;/tt&gt; || &lt;tt&gt;00110110&lt;/tt&gt; || 1 || 1
|}

----
{{Anchor|STC}}
=== STC ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#CF|CF - Carry]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STC || &lt;tt&gt;F9&lt;/tt&gt; || &lt;tt&gt;11111001&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STD}}
=== STD ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#DF|DF - Direction]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STD || &lt;tt&gt;FD&lt;/tt&gt; || &lt;tt&gt;11111101&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STI}}
=== STI ===

{| class="wikitable"
! Flag !! New value
|-
| [[NEC_V30MZ_flags#IF|IF - Interrupt]] || 1
|}

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STI || &lt;tt&gt;FB&lt;/tt&gt; || &lt;tt&gt;11111011&lt;/tt&gt; || 1 || 4
|}

----
{{Anchor|STOSB}}
{{Anchor|STOSW}}
=== STOSB/STOSW ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| STOSB || &lt;tt&gt;AA&lt;/tt&gt; || &lt;tt&gt;10101010&lt;/tt&gt; || 1 || 3
|-
| STOSW || &lt;tt&gt;AB&lt;/tt&gt; || &lt;tt&gt;10101011&lt;/tt&gt; || 1 || 3
|}

----
{{Anchor|SUB}}
=== SUB ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| SUB AL, imm || &lt;tt&gt;28 ii&lt;/tt&gt; || &lt;tt&gt;00101100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| SUB AX, imm || &lt;tt&gt;29 ii ii&lt;/tt&gt; || &lt;tt&gt;00101101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB mem8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| SUB mem16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo101mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| SUB mem8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;00101000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB mem16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;00101001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| SUB reg8, imm8 || &lt;tt&gt;80 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg16, imm16 || &lt;tt&gt;81 /5 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11101mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| SUB reg16, simm8 || &lt;tt&gt;83 /5 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11101mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| SUB reg8, mem8 || &lt;tt&gt;2A /r&lt;/tt&gt; || &lt;tt&gt;00101010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg16, mem16 || &lt;tt&gt;2B /r&lt;/tt&gt; || &lt;tt&gt;00101011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| SUB reg8, reg8 || &lt;tt&gt;28 /r&lt;/tt&gt; || &lt;tt&gt;001010.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| SUB reg16, reg16 || &lt;tt&gt;29 /r&lt;/tt&gt; || &lt;tt&gt;001010.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|TEST}}
=== TEST ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| TEST AL, imm || &lt;tt&gt;A8 ii&lt;/tt&gt; || &lt;tt&gt;10101000 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| TEST AX, imm || &lt;tt&gt;A9 ii ii&lt;/tt&gt; || &lt;tt&gt;10101001 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST mem8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 oo000mmm iiiiiiii&lt;/tt&gt; || 3+ || 2
|-
| TEST mem16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 oo000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 2
|-
| TEST mem8, reg8&lt;br/&gt;TEST reg8, mem8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST mem16, reg16&lt;br/&gt;TEST reg16, mem16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| TEST reg8, imm8 || &lt;tt&gt;F6 /0 ii&lt;/tt&gt; || &lt;tt&gt;11110110 11000mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| TEST reg16, imm16 || &lt;tt&gt;F7 /0 ii ii&lt;/tt&gt; || &lt;tt&gt;11110111 11000mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| TEST reg8, reg8 || &lt;tt&gt;84 /r&lt;/tt&gt; || &lt;tt&gt;10000100 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| TEST reg16, reg16 || &lt;tt&gt;85 /r&lt;/tt&gt; || &lt;tt&gt;10000101 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

----
{{Anchor|WAIT}}
=== WAIT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| WAIT || &lt;tt&gt;6E&lt;/tt&gt; || &lt;tt&gt;01101110&lt;/tt&gt; || 1 || 9&lt;ref&gt;On the WonderSwan implementation, POLLB is always held low; on other implementations, POLL will wait for POLLB to be held low in 9-cycle intervals.&lt;/ref&gt;
|}

Nominally, this instruction synchronizes the CPU with an external co-processor. However, as the WonderSwan does not feature one, this instruction simply becomes a (slower) no-op.

----
{{Anchor|XCHG}}
=== XCHG ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XCHG AX, reg16&lt;br/&gt;XCHG reg16, AX || &lt;tt&gt;9x&lt;/tt&gt; || &lt;tt&gt;10010rrr&lt;/tt&gt; || 1 || 3
|-
| XCHG mem8, reg8&lt;br/&gt;XCHG reg8, mem8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG mem16, reg16&lt;br/&gt;XCHG reg16, mem16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 oorrrmmm&lt;/tt&gt; || 2+ || 5
|-
| XCHG reg8, reg8 || &lt;tt&gt;86 /r&lt;/tt&gt; || &lt;tt&gt;10000110 11rrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XCHG reg16, reg16 || &lt;tt&gt;87 /r&lt;/tt&gt; || &lt;tt&gt;10000111 11rrrmmm&lt;/tt&gt; || 2+ || 3
|}

----
{{Anchor|XLAT}}
=== XLAT ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XLAT || &lt;tt&gt;D7&lt;/tt&gt; || &lt;tt&gt;11010111&lt;/tt&gt; || 1 || 5
|}

----
{{Anchor|XOR}}
=== XOR ===

{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| XOR AL, imm || &lt;tt&gt;34 ii&lt;/tt&gt; || &lt;tt&gt;00110100 iiiiiiii&lt;/tt&gt; || 2 || 1
|-
| XOR AX, imm || &lt;tt&gt;35 ii ii&lt;/tt&gt; || &lt;tt&gt;00110101 iiiiiiii iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR mem8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 oo110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4+ || 3
|-
| XOR mem16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 oo110mmm iiiiiiii&lt;/tt&gt; || 3+ || 3
|-
| XOR mem8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;00110000 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR mem16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;00110001 oorrrmmm&lt;/tt&gt; || 2+ || 3
|-
| XOR reg8, imm8 || &lt;tt&gt;80 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000000 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg16, imm16 || &lt;tt&gt;81 /6 ii ii&lt;/tt&gt; || &lt;tt&gt;10000001 11110mmm iiiiiiii iiiiiiii&lt;/tt&gt; || 4 || 1
|-
| XOR reg16, simm8 || &lt;tt&gt;83 /6 ii&lt;/tt&gt; || &lt;tt&gt;10000011 11110mmm iiiiiiii&lt;/tt&gt; || 3 || 1
|-
| XOR reg8, mem8 || &lt;tt&gt;32 /r&lt;/tt&gt; || &lt;tt&gt;00110010 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg16, mem16 || &lt;tt&gt;33 /r&lt;/tt&gt; || &lt;tt&gt;00110011 oorrrmmm&lt;/tt&gt; || 2+ || 2
|-
| XOR reg8, reg8 || &lt;tt&gt;30 /r&lt;/tt&gt; || &lt;tt&gt;001100.0 11rrrmmm&lt;/tt&gt; || 2 || 1
|-
| XOR reg16, reg16 || &lt;tt&gt;31 /r&lt;/tt&gt; || &lt;tt&gt;001100.1 11rrrmmm&lt;/tt&gt; || 2 || 1	
|}

== Notes ==

&lt;references /&gt;</text>
    <sha1>314a1bbe36662854c5fc166ef7f7630703eab9be</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>NEC V30MZ interrupts</title>
  <ns>0</ns>
  <id>58</id>
  <revision>
    <id>552</id>
    <parentid>550</parentid>
    <timestamp>2025-03-02T13:31:00Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Timing */ BRK also has a latch</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2658" xml:space="preserve">== CPU interrupts ==

The NEC V30MZ implements six of the eight CPU interrupts provided by the 80186.

=== INT 0 - Divide Error ===

This interrupt is emitted as the result of a DIV&lt;sup&gt;IDIV&lt;/sup&gt; or DIVU&lt;sup&gt;DIV&lt;/sup&gt; instruction.

=== INT 1 - Single Step/Break ===

This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interrupt, allowing the user to store state and perform debug activities; it is then restored when returning from the interrupt, by restoring the original processor flags stored on the stack.

=== INT 2 - Non-Maskable interrupt (NMI) ===

This interrupt is emitted when the SoC requests a non-maskable interrupt. On the WonderSwan, the condtions for emitting an NMI are configured by the relevant I/O port.

=== INT 3 - Breakpoint ===

This interrupt is emitted by the INT 3&lt;sup&gt;BRK&lt;/sup&gt; instruction. Unlike other unconditional interrupt instructions, it is encoded with only one byte.

=== INT 4 - Overflow ===

This interrupt is emitted by the INTO&lt;sup&gt;BRKV&lt;/sup&gt; instruction, if the overflow flag is set while it is being executed.

=== INT 5 - Array Bounds ===

This interrupt is emitted only by the BOUND&lt;sup&gt;CHKIND&lt;/sup&gt; instruction.

== External interrupts ==

The NEC V30MZ distinguishes three sources of external interrupts - that is, interrupts not triggered by an instruction itself:

* Non-maskable interrupts:
** NMI - controlled by the NMI control I/O port on WS,
** BRK - controlled by the single-step flag.
* Maskable interrupts:
** IRQ - controlled by the IRQ control I/O ports on WS.

== Timing ==

Both non-maskable and maskable interrupts are acknowledged after the execution of an instruction is complete. However, under some conditions, interrupts may not be processed on a given instruction and delayed until the next one. This is the case for:

* instructions which change the stack segment register (MOV and POP),
* prefix instructions (LOCK, REP, segment prefixes),
* instructions which set the interrupt enable CPU flag (STI, POPF), if the flag was cleared prior to the instruction's execution (for IRQ interrupts only),
* instructions which set the single-step CPU flag, if the flag was cleared prior to the instruction's execution (for BRK interrupts only).

TODO: Document how many cycles interrupt processing takes.

== Notes ==

* The following 80186 interrupts are not implemented:
** INT 6 - Unused Opcode - the V30MZ treats most unimplemented instructions as NOPs.
** INT 7 - ESC Opcode - the V30MZ, likewise, treats these instructions as NOPs.</text>
    <sha1>c763c4e67bfb1d1227dafbd1218c4e3a4bc4229b</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Interrupts</title>
  <ns>0</ns>
  <id>22</id>
  <revision>
    <id>553</id>
    <parentid>352</parentid>
    <timestamp>2025-03-08T12:00:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupts */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3220" xml:space="preserve">== Interrupts ==
The WonderSwan features fourteen different interrupts:

* CPU interrupts - six provided by the V30MZ CPU ($00-$05),
* Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset &lt;code&gt;V&lt;/code&gt;):
** Level - will be constantly requested while enabled and the prerequisite condition is true,
** Edge - will only be requested while enabled the moment the prerequisite condition ''becomes'' true.

Interrupt requests happen when the condition is true and the interrupt is enabled. Note that edge interrupts are only requested once; level interrupts are requested constantly, making acknowledgements ineffective until the condition is cleared or the interrupt is disabled. However, neither disabling an interrupt nor satisfying the condition clears the acknowledgement bit.

The user can additionally make use of all 256 available interrupt vectors in their own code.

{| class="wikitable"
|+ List of WonderSwan interrupts
! Source
! Type
! Index
! Description
|-
! rowspan="6" | CPU
| rowspan="6" | N/A
| $00
| DIV or IDIV instruction divide error&lt;br/&gt;
(division by zero or result overflow)
|-
| $01
| Single-step (T flag)
|-
| $02
| NMI (non-maskable interrupt)
|-
| $03
| INT 3 opcode
|-
| $04
| INTO opcode (if V = 1)
|-
| $05
| BOUND opcode (if index out of bounds)
|-
! rowspan="8" | Hardware
| Level
| V + 0
| [[UART|UART Send Ready]]
|-
| Edge
| V + 1
| [[Keypad|Key Pressed]]
|-
| rowspan="2" | Level
| V + 2
| [[Cartridge|Cartridge IRQ]]
|-
| V + 3
| [[UART|UART Receive Ready]]
|-
| rowspan="4" | Edge
| V + 4
| [[Display|Display Interrupt Line Match]]
|-
| V + 5
| [[Timers|Vertical Blank Timer]]
|-
| V + 6
| [[Display|Display Vertical Blank]]
|-
| V + 7
| [[Timers|Horizontal Blank Timer]]
|}

== I/O ports ==

{{Anchor|Interrupt Vector Offset}}
=== Interrupt Vector Offset ($B0 write) ===

&lt;pre&gt;
7  bit  0
---- ----
VVVV V...
|||| |
++++-+---- Interrupt vector offset
&lt;/pre&gt;

{{Anchor|Interrupt Vector Request}}

=== Interrupt Vector Request ($B0 read) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.
&lt;/pre&gt;

* Bits &lt;code&gt;7 .. 3&lt;/code&gt; of this will always equal the user-provided vector offset.
* Bits &lt;code&gt;2 .. 0&lt;/code&gt; of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal &lt;code&gt;0&lt;/code&gt;.

{{Anchor|Interrupt Enable}}

=== Interrupt Enable ($B2) ===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)
&lt;/pre&gt;

Contrary to other systems, this also controls whether interrupts set the relevant bit in Interrupt Status.

{{Anchor|Interrupt Status}}

=== Interrupt Status ($B4 read)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested
&lt;/pre&gt;

{{Anchor|Interrupt Acknowledge}}
=== Interrupt Acknowledge ($B6 write)===

&lt;pre&gt;
7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request
&lt;/pre&gt;

{{Anchor|Interrupt NMI Control}}
=== Interrupt NMI Control ($B7)===

&lt;pre&gt;
7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection
&lt;/pre&gt;</text>
    <sha1>a3a659fa27ddb1e3a8fe91d5742963bf92d47eb2</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>UART</title>
  <ns>0</ns>
  <id>23</id>
  <revision>
    <id>554</id>
    <parentid>123</parentid>
    <timestamp>2025-03-08T12:00:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupts */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1757" xml:space="preserve">The WonderSwan's EXT port features an UART operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for an effective maximum transfer speed of 960 or 3840 bytes per second, respectively.

The hardware also features one-byte transmit and receive buffers, which allow for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly triggering (level interrupt) as long as the transmit buffer is empty (Serial Status bit 2),
* UART Receive Ready - constantly triggering (level interrupt) as long as the receive buffer contains a byte (Serial Status bit 0).

These interrupts are only triggering if the UART block is enabled.

== I/O ports ==

{{Anchor|Serial Receive Data}}
=== Serial Receive Data ($B1 read) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Receive buffer value
&lt;/pre&gt;

{{Anchor|Serial Transmit Data}}
=== Serial Transmit Data ($B1 write) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Transmit buffer value
&lt;/pre&gt;

{{Anchor|Serial Status}}
=== Serial Status ($B3 read) ===

&lt;pre&gt;
7  bit  0
---- ----
eb.. .tor
||    |||
||    ||+- 1 if the receive buffer contains a byte
||    |+-- 1 on overrun (receive buffer overflow)
||    +--- 1 if the transmit buffer is empty (can transmit another byte)
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;

{{Anchor|Serial Control}}
=== Serial Control ($B3 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. ....
|||
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>baaf6e2fdc043e9b5063291d88dfcdf936b6aa39</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Display</title>
  <ns>0</ns>
  <id>26</id>
  <revision>
    <id>555</id>
    <parentid>521</parentid>
    <timestamp>2025-03-08T13:13:01Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>document sprite drawing priority</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2613" xml:space="preserve">The WonderSwan features a 224x144 display capable of displaying up to 16 shades of gray (mono) or 4096 colors (color).

{| class="wikitable"
! ↑ Front ↑
! Window
! Scroll
|-
| align="center" | Sprites, high priority
| ✔
|
|-
| align="center" | Screen 2
| ✔
| ✔
|-
| align="center" | Sprites, low priority
| ✔
|
|-
| align="center" | Screen 1
| 
| ✔
|-
| align="center" | Background color
| 
|
|-
! ↑ Back ↑
! Window
! Scroll
|}

== Features ==

=== Screens ===

Screens are 32x32 tile maps, for a total of 256x256 pixels; each map entry can use one of 512 (mono) or 1024 (color) tiles, one of sixteen distinct palettes, as well as be drawn mirrored or flipped. The screens can be scrolled horizontally and vertically.

=== Sprites ===

The sprite layer consists of 128 distinct sprites. These can use any of the first 512 tiles, palettes 8 through 15, as well as be drawn over or under screen 2.

Each scanline can display up to 32 sprites at a time; these will be the first 32 sprites found on the list for the given scanline. Sprites are then drawn in order from last to first.

=== Windows ===

The window functionality can be used to restrict drawing of Screen 2's tiles, as well as the sprite layer, to a given pixel-perfect window. Individual sprites can be marked as being drawn inside or outside the window.

=== Palettes ===

Each palette consists of four colors, of which the first entry - color zero - is opaque in palettes 0-3 and 8-11 and transparent otherwise. The color models additionally feature a sixteen-color palette mode, in which color zero is always considered transparent. The background color is displayed if no ''opaque'' pixel from any screens or sprites is drawn.

=== Icons ===

In addition, a set of LCD segment-based icons is provided to a side of the display which can be independently controlled as an indicator to the user.

== Interrupts ==

The display circuit generates two interrupts of its own:

* Display Interrupt Line Match - when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;Display Interrupt Line&lt;/code&gt;, at the beginning of said line.
* Display Vertical Blank -  when &lt;code&gt;Display Current Line&lt;/code&gt; == &lt;code&gt;144&lt;/code&gt;, at the beginning of said line.

It also provides a timing source for the two Horizontal and Vertical Blank [[Timers]], which provide their own respective interrupts.

== More information ==

* [[Display/Tile Data|Tile data]]
* [[Display/Palette|Color palette]]
* [[Display/Screens|Screen format]]
* [[Display/Sprites|Sprite format]]
* [[Display/Windows|Windows]]
* [[Display/LCD Icons|LCD icons]]
* [[Display/IO Ports|I/O ports]]</text>
    <sha1>65203d5c8077bf8b8364261ef69cdee818cd22b1</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>WonderWitch/Filesystem</title>
  <ns>0</ns>
  <id>59</id>
  <revision>
    <id>556</id>
    <parentid>537</parentid>
    <timestamp>2025-03-09T17:34:56Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Timestamp format */ Ranges</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1785" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || Location in CPU address space (segment:offset)
|-
| 44 || 4 || Total file size, in bytes, excluding the header.
|-
| 48 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time
|-
| 56 || 4 || TODO
|-
| 60 || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== Timestamp format ===

{| class="wikitable"
|+ Header contents
|-
! Bits !! Contents
|-
| 31 - 25 || Year, 0 .. (starting from 2000)
|-
| 24 - 21 || Month, 1 .. 12
|-
| 20 - 16 || Day, 1 .. 31
|-
| 15 - 11 || Hour, 0 .. 23
|-
| 10 - 5 || Minute, 0 .. 59
|-
| 0 - 4 || Second, 0 .. 29 (in two-second units)
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>254d7cee908f619de9058c57e4d8b0c151ec5e86</sha1>
  </revision>
  <revision>
    <id>590</id>
    <parentid>556</parentid>
    <timestamp>2025-04-11T20:00:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Mount points */ /kern</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2270" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

=== /kern ===

The &lt;tt&gt;/kern&lt;/tt&gt; folder is provided by FreyaOS.

{| class="wikitable"
|-
! File !! Description
|-
| &lt;tt&gt;@ilib&lt;/tt&gt;
| [[WonderWitch/IL/IlibIL|IlibIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@proc&lt;/tt&gt;
| [[WonderWitch/IL/ProcIL|ProcIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@pfs&lt;/tt&gt;
| [[WonderWitch/IL/FsIL|FsIL]]
|-
| &lt;tt&gt;@shell&lt;/tt&gt;
| Shell program; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@aux&lt;/tt&gt;
|
|-
| &lt;tt&gt;about.txt&lt;/tt&gt;
| "About Freya"
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || Location in CPU address space (segment:offset)
|-
| 44 || 4 || Total file size, in bytes, excluding the header.
|-
| 48 || 2 || XMODEM chunk count - above file size divided by 128, then rounded up.
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time
|-
| 56 || 4 || TODO
|-
| 60 || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== Timestamp format ===

{| class="wikitable"
|+ Header contents
|-
! Bits !! Contents
|-
| 31 - 25 || Year, 0 .. (starting from 2000)
|-
| 24 - 21 || Month, 1 .. 12
|-
| 20 - 16 || Day, 1 .. 31
|-
| 15 - 11 || Hour, 0 .. 23
|-
| 10 - 5 || Minute, 0 .. 59
|-
| 0 - 4 || Second, 0 .. 29 (in two-second units)
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>3e2c0ccffc1d550799854b3030425322e2ae8c29</sha1>
  </revision>
  <revision>
    <id>591</id>
    <parentid>590</parentid>
    <timestamp>2025-04-11T20:23:23Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* File table entry format */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2339" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

=== /kern ===

The &lt;tt&gt;/kern&lt;/tt&gt; folder is provided by FreyaOS.

{| class="wikitable"
|-
! File !! Description
|-
| &lt;tt&gt;@ilib&lt;/tt&gt;
| [[WonderWitch/IL/IlibIL|IlibIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@proc&lt;/tt&gt;
| [[WonderWitch/IL/ProcIL|ProcIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@pfs&lt;/tt&gt;
| [[WonderWitch/IL/FsIL|FsIL]]
|-
| &lt;tt&gt;@shell&lt;/tt&gt;
| Shell program; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@aux&lt;/tt&gt;
|
|-
| &lt;tt&gt;about.txt&lt;/tt&gt;
| "About Freya"
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || Location in CPU address space (segment:offset)
|-
| 44 || 4 || Total file size, in bytes, excluding the header.
|-
| 48 || 2 || File: 128-byte (XMODEM) chunk count, rounded up
Directory: Number of entries
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time
|-
| 56 || 4 || File: TODO
Directory: Pointer to FsIL implementation for directory
|-
| 60 || 4 || Offset to resource data, bytes excluding header; -1 if not present.
|}

=== Timestamp format ===

{| class="wikitable"
|+ Header contents
|-
! Bits !! Contents
|-
| 31 - 25 || Year, 0 .. (starting from 2000)
|-
| 24 - 21 || Month, 1 .. 12
|-
| 20 - 16 || Day, 1 .. 31
|-
| 15 - 11 || Hour, 0 .. 23
|-
| 10 - 5 || Minute, 0 .. 59
|-
| 0 - 4 || Second, 0 .. 29 (in two-second units)
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>d1d08e65a05f228b9caba27ee2ce85fa7ea18ce2</sha1>
  </revision>
  <revision>
    <id>592</id>
    <parentid>591</parentid>
    <timestamp>2025-04-11T20:32:35Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* File table entry format */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2391" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

=== /kern ===

The &lt;tt&gt;/kern&lt;/tt&gt; folder is provided by FreyaOS.

{| class="wikitable"
|-
! File !! Description
|-
| &lt;tt&gt;@ilib&lt;/tt&gt;
| [[WonderWitch/IL/IlibIL|IlibIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@proc&lt;/tt&gt;
| [[WonderWitch/IL/ProcIL|ProcIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@pfs&lt;/tt&gt;
| [[WonderWitch/IL/FsIL|FsIL]]
|-
| &lt;tt&gt;@shell&lt;/tt&gt;
| Shell program; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@aux&lt;/tt&gt;
|
|-
| &lt;tt&gt;about.txt&lt;/tt&gt;
| "About Freya"
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || Location in CPU address space (segment:offset)
|-
| 44 || 4 || Total file size, in bytes, excluding the header.
|-
| 48 || 2 || File: 128-byte (XMODEM) chunk count, rounded up; &lt;tt&gt;0xFFFF&lt;/tt&gt; if deleted file.
Directory: Number of entries.
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time
|-
| 56 || 4 || File: TODO
Directory: Pointer to FsIL implementation for directory
|-
| 60 || 4 || Offset to resource data, bytes excluding header; &lt;tt&gt;0xFFFFFFFF&lt;/tt&gt; if not present.
|}

=== Timestamp format ===

{| class="wikitable"
|+ Header contents
|-
! Bits !! Contents
|-
| 31 - 25 || Year, 0 .. (starting from 2000)
|-
| 24 - 21 || Month, 1 .. 12
|-
| 20 - 16 || Day, 1 .. 31
|-
| 15 - 11 || Hour, 0 .. 23
|-
| 10 - 5 || Minute, 0 .. 59
|-
| 0 - 4 || Second, 0 .. 29 (in two-second units)
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>c572bce0a848c1d75487ed86427316e91071c0e6</sha1>
  </revision>
  <revision>
    <id>593</id>
    <parentid>592</parentid>
    <timestamp>2025-04-12T17:52:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* File table entry format */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2427" xml:space="preserve">== Mount points ==

{| class="wikitable"
|+ FreyaOS mount points
|-
! Path !! File data location !! File table location !! File table size (entries) !! Description
|-
| &lt;code&gt;/rom0&lt;/code&gt; || ROM (384 KB) || SRAM bank 3, $16F2 || 128 ||
|-
| &lt;code&gt;/ram0&lt;/code&gt; || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 ||
|-
| &lt;code&gt;/&lt;/code&gt; || || SRAM bank 3, $02F2 || 16 || 
|}

=== /kern ===

The &lt;tt&gt;/kern&lt;/tt&gt; folder is provided by FreyaOS.

{| class="wikitable"
|-
! File !! Description
|-
| &lt;tt&gt;@ilib&lt;/tt&gt;
| [[WonderWitch/IL/IlibIL|IlibIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@proc&lt;/tt&gt;
| [[WonderWitch/IL/ProcIL|ProcIL]]; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@pfs&lt;/tt&gt;
| [[WonderWitch/IL/FsIL|FsIL]]
|-
| &lt;tt&gt;@shell&lt;/tt&gt;
| Shell program; can be overridden in &lt;tt&gt;/rom0&lt;/tt&gt;
|-
| &lt;tt&gt;@aux&lt;/tt&gt;
|
|-
| &lt;tt&gt;about.txt&lt;/tt&gt;
| "About Freya"
|}

== File table entry format ==

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| 0 || 16 || File name; zero-terminated Shift-JIS string.
|-
| 16 || 24 || User-friendly file name; zero-terminated Shift-JIS string.

FreyaOS displays the first 12 characters in its file selector.
|-
| 40 || 4 || File: Location in CPU address space (segment:offset)
|-
| 44 || 4 || File: Total file size, in bytes, excluding the header.
|-
| 48 || 2 || File: 128-byte (XMODEM) chunk count, rounded up.
Directory: Number of total available entries.
&lt;tt&gt;0xFFFF&lt;/tt&gt; (-1): Unallocated entry.
|-
| 50 || 2 || File mode
|-
| 52 || 4 || Modification time
|-
| 56 || 4 || File: TODO
Directory: Pointer to FsIL implementation for directory
|-
| 60 || 4 || Offset to resource data, bytes excluding header; &lt;tt&gt;0xFFFFFFFF&lt;/tt&gt; if not present.
|}

=== Timestamp format ===

{| class="wikitable"
|+ Header contents
|-
! Bits !! Contents
|-
| 31 - 25 || Year, 0 .. (starting from 2000)
|-
| 24 - 21 || Month, 1 .. 12
|-
| 20 - 16 || Day, 1 .. 31
|-
| 15 - 11 || Hour, 0 .. 23
|-
| 10 - 5 || Minute, 0 .. 59
|-
| 0 - 4 || Second, 0 .. 29 (in two-second units)
|}

=== File modes ===
----
&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ???? ????  dlis mrwx
            |||| ||||
            |||| |||+- Execute
            |||| ||+-- Write
            |||| |+--- Read
            |||| +---- Prohibit mmap() use
            |||+------ StreamIL-related?
            ||+------- Intermediate library
            |+-------- Symbolic link
            +--------- Directory
&lt;/pre&gt;</text>
    <sha1>74f5ac6a48411a133177fa5a54c757d6817da93b</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Sound</title>
  <ns>0</ns>
  <id>27</id>
  <revision>
    <id>557</id>
    <parentid>359</parentid>
    <timestamp>2025-03-09T20:15:38Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="10828" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This frequency is used for wavetable output. It is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}
=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, all three of: the channel 4 enable bit, the channel 4 noise mode bit, and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>0853b2090060a9193baaa794899ce0e718eb03b9</sha1>
  </revision>
  <revision>
    <id>558</id>
    <parentid>557</parentid>
    <timestamp>2025-03-09T20:27:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11044" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This value controls the sample period counters. Every &lt;code&gt;2048 - divisor&lt;/code&gt; cycles, the index of the sample to be fetched from the wavetable is incremented; in addition, if noise is enabled, the state of the noise LFSR is advanced.

The resulting frequency is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}

=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, all three of: the channel 4 enable bit, the channel 4 noise mode bit, and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

The wavetable is 4 x 16 bytes long; each 16-byte block contains 32 4-bit samples for the relevant channel:

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>d6b191e7088bc82b3d596a34c0719c1522c7442d</sha1>
  </revision>
  <revision>
    <id>559</id>
    <parentid>558</parentid>
    <timestamp>2025-03-09T20:29:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11284" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== Wavetable RAM ==

The wavetable RAM is an user-configurable 64-byte area of memory which stores four 16-byte waveforms. Each waveform contains 32 4-bit samples for the respective channel (from 1 to 4):

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

The current sample to be played (from 0 to 31) is selected by an internal sample index counter; there is no known way to reset this counter.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This value controls the sample period counters. Every &lt;code&gt;2048 - divisor&lt;/code&gt; cycles, the index of the sample to be fetched from the wavetable is incremented; in addition, if noise is enabled, the state of the noise LFSR is advanced.

The resulting frequency is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}

=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for voice output.

{{Anchor|Sound Channel 3 Sweep Amount}}
=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, all three of: the channel 4 enable bit, the channel 4 noise mode bit, and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>4f91785701333edd4979836fadbca8f2b760b3f3</sha1>
  </revision>
  <revision>
    <id>560</id>
    <parentid>559</parentid>
    <timestamp>2025-03-09T20:31:39Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <comment>/* Sound Channel 2 Voice Sample ($89) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11302" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== Wavetable RAM ==

The wavetable RAM is an user-configurable 64-byte area of memory which stores four 16-byte waveforms. Each waveform contains 32 4-bit samples for the respective channel (from 1 to 4):

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

The current sample to be played (from 0 to 31) is selected by an internal sample index counter; there is no known way to reset this counter.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This value controls the sample period counters. Every &lt;code&gt;2048 - divisor&lt;/code&gt; cycles, the index of the sample to be fetched from the wavetable is incremented; in addition, if noise is enabled, the state of the noise LFSR is advanced.

The resulting frequency is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}

=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for channel 2's voice output mode.

{{Anchor|Sound Channel 3 Sweep Amount}}

=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, all three of: the channel 4 enable bit, the channel 4 noise mode bit, and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 mode: 0 = wavetable, 1 = voice
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}
=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>712b769bc0069fc7bbacb8a78dd3a305d69e7c2d</sha1>
  </revision>
  <revision>
    <id>561</id>
    <parentid>560</parentid>
    <timestamp>2025-03-09T20:32:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Channel Control ($90) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11314" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== Wavetable RAM ==

The wavetable RAM is an user-configurable 64-byte area of memory which stores four 16-byte waveforms. Each waveform contains 32 4-bit samples for the respective channel (from 1 to 4):

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

The current sample to be played (from 0 to 31) is selected by an internal sample index counter; there is no known way to reset this counter.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This value controls the sample period counters. Every &lt;code&gt;2048 - divisor&lt;/code&gt; cycles, the index of the sample to be fetched from the wavetable is incremented; in addition, if noise is enabled, the state of the noise LFSR is advanced.

The resulting frequency is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}

=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for channel 2's voice output mode.

{{Anchor|Sound Channel 3 Sweep Amount}}

=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, all three of: the channel 4 enable bit, the channel 4 noise mode bit, and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 voice enable (overrides wavetable enable)
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}

=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>0e4228265dedc14bf3dbcf5de50eefb199856fac</sha1>
  </revision>
  <revision>
    <id>572</id>
    <parentid>561</parentid>
    <timestamp>2025-03-16T17:22:43Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Channel 4 Noise Control ($8E) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11277" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== Wavetable RAM ==

The wavetable RAM is an user-configurable 64-byte area of memory which stores four 16-byte waveforms. Each waveform contains 32 4-bit samples for the respective channel (from 1 to 4):

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

The current sample to be played (from 0 to 31) is selected by an internal sample index counter; there is no known way to reset this counter.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This value controls the sample period counters. Every &lt;code&gt;2048 - divisor&lt;/code&gt; cycles, the index of the sample to be fetched from the wavetable is incremented; in addition, if noise is enabled, the state of the noise LFSR is advanced.

The resulting frequency is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}

=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for channel 2's voice output mode.

{{Anchor|Sound Channel 3 Sweep Amount}}

=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, two of: the channel 4 enable bit and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 voice enable (overrides wavetable enable)
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}

=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
??5? llsh
  |  ||||
  |  |||+- Hold Ch1-4 output updates
  |  ||+-- Use 3072000 Hz CPU clock for sweep
  |  ++--- Hold noise LFSR output
  |        (Differences between bit 2/3
  |        behavior are unknown)
  +------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>0f0ebf690689202908dfccf7c4083ed3e7d713ee</sha1>
  </revision>
  <revision>
    <id>596</id>
    <parentid>572</parentid>
    <timestamp>2025-04-20T18:15:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound Test ($95) */ bits 6-7</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="11453" xml:space="preserve">The WonderSwan features the following sound hardware:

* Four audio channels:
** channel 1 - wavetable (32 x 4-bit samples),
** channel 2 - wavetable or 8-bit unsigned PCM sample,
** channel 3 - wavetable with optional hardware sweep,
** channel 4 - wavetable or LFSR noise,
* [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt; - headphone output exclusive 16-bit stereo PCM output,
* 24000 Hz output:
** internal speaker - 8-bit, mono,
** headphone output - 16-bit, stereo.

[[Hyper Voice]] functionality is documented on its own sub-page.

== Mixing diagram == 

The sound is mixed as follows:

&lt;pre&gt;
      Ch1 Ch2 Ch3 Ch4                        Glossary: L = left, R = right, M = mono 
       |   |   |   |                                               Mnn = nn-bit mono
       8   8   8   8      port $98                            port $nn =  value port
       |   |   |   |       /
      _V___V___V___V_     /              _____          _____
     |               |--L10------+-----&gt;|     |        |     |
     |       +       |           |      |  +  |--M11--&gt;| &gt;&gt;r |--M8--&gt; Speaker output
     |_______________|--R10------|-+---&gt;|_____|  /     |_____|
                        /       _|_|_           /     (r=0...3)
                       /       |     |         /        \
                  port $96     | &lt;&lt;5 |      port $9A     \
                               |_____|                    \
                                 | |                    port $91
                                 | |
port $68            port $64     | |
 /    _______________   \      __V_V__                  _____
L8--&gt;| (Color only)  |--L16--&gt;|       |----------L16--&gt;|     |
     |  Hyper Voice  |        |  + +  |                | I2S |------&gt; Headphone output
R8--&gt;|_______________|--R16--&gt;|_______|----------R16--&gt;|_____|
 \                      /
port $69            port $66
&lt;/pre&gt;

== Wavetable RAM ==

The wavetable RAM is an user-configurable 64-byte area of memory which stores four 16-byte waveforms. Each waveform contains 32 4-bit samples for the respective channel (from 1 to 4):

&lt;pre&gt;
Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F
         98  CB  ED  FF  FF  EF  BD  8A  57  24  01  00  00  21  43  76
 Sample
     15  ..  ..  ..  ##  ##  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     14  ..  ..  .#  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..  ..
     13  ..  ..  #|  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     12  ..  .#  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..  ..
     11  ..  #|  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..  ..
     10  ..  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  ..  ..
      9  .#  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  ..  ..
      8  #|  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ..  ..
      7  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  ..  ..  .#
      6  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  ..  ..  #|
      5  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  ..  ..  ..  ||
      4  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  ..  ..  .#  ||
      3  ||  ||  ||  ||  ||  ||  ||  ||  ||  |.  ..  ..  ..  ..  #|  ||
      2  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ..  ..  ..  .#  ||  ||
      1  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  #.  ..  ..  #|  ||  ||
      0  ||  ||  ||  ||  ||  ||  ||  ||  ||  ||  |#  ##  ##  ||  ||  ||
&lt;/pre&gt;

Note that the ''higher'' bits - the first hexadecimal number - specify the ''later'' samples; that is to say, the nybbles of each sample are swapped relative to the wave drawing.

The current sample to be played (from 0 to 31) is selected by an internal sample index counter; there is no known way to reset this counter.

== I/O Ports ==

{{Anchor|Sound Channel Frequency}}
=== Sound Channel Frequency ($80, $81; $82, $83; $84, $85; $86, $87) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .ddd  dddd dddd
       |||  |||| ||||
       +++--++++-++++- Frequency divisor
&lt;/pre&gt;

This value controls the sample period counters. Every &lt;code&gt;2048 - divisor&lt;/code&gt; cycles, the index of the sample to be fetched from the wavetable is incremented; in addition, if noise is enabled, the state of the noise LFSR is advanced.

The resulting frequency is calculated as follows: &lt;code&gt;sample rate = 3072000 Hz / (2048 - divisor)&lt;/code&gt;.

Note that this refers to the sample rate of each sample in the ''wavetable'', and needs to be scaled accordingly for a given waveform. For example, a 50% duty square wave (16 samples of &lt;tt&gt;0&lt;/tt&gt; followed by 16 samples of &lt;tt&gt;15&lt;/tt&gt;) will have an effective sample rate of &lt;code&gt;(3072000 / 32) Hz / (2048 - divisor)&lt;/code&gt;, or &lt;code&gt; 96000 Hz / (2048 - divisor)&lt;/code&gt;.

{{Anchor|Sound Channel Volume}}

=== Sound Channel Volume ($88; $89; $8A; $8B) ===

&lt;pre&gt;
7  bit  0
---------
llll rrrr
|||| ||||
|||| ++++- Right channel volume (0-15)
++++------ Left channel volume (0-15)
&lt;/pre&gt;

This volume is used for wavetable output.

The calculation to get an unsigned 8-bit sample out of a 4-bit wavetable sample / 4-bit volume pair is simple: &lt;code&gt;out_sample = sample * volume&lt;/code&gt;. This means that the maximum sample in wavetable output mode is &lt;code&gt;15 * 15 = 225&lt;/code&gt;.

{{Anchor|Sound Channel 2 Voice Sample}}
=== Sound Channel 2 Voice Sample ($89) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Unsigned 8-bit PCM sample (0-255)
&lt;/pre&gt;

This sample is used for channel 2's voice output mode.

{{Anchor|Sound Channel 3 Sweep Amount}}

=== Sound Channel 3 Sweep Amount ($8C) ===

&lt;pre&gt;
7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Value; 8-bit, signed.
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

The signed value in this port will be added to the frequency divider for channel 3 every sweep step (as determined by the Sweep Ticks port). Wraparound is present - adding 1 to a frequency divider value of 2047 will cause it to roll over back to 0.

{{Anchor|Sound Channel 3 Sweep Ticks}}
=== Sound Channel 3 Sweep Ticks ($8D) ===

&lt;pre&gt;
7  bit  0
---- ----
...t tttt
   | ||||
   +-++++- Ticks per step - 1
&lt;/pre&gt;

This port is used for wavetable output with sweep enabled.

Every &lt;code&gt;ttttt + 1&lt;/code&gt; ticks, clocked at 375 Hz, the value in the Sweep Amount port will be added to the frequency divider for channel 3.

{{Anchor|Sound Channel 4 Noise Control}}
=== Sound Channel 4 Noise Control ($8E) ===

&lt;pre&gt;
7  bit  0
---- ----
...e rttt
   | ||||
   | |+++- LFSR tap mode
   | +---- LFSR reset: 1 = reset shift register
   +------ LFSR enabled: 0 = off, 1 = on
&lt;/pre&gt;

This port is used for noise output.

{| class="wikitable"
|+ List of LFSR tap modes
! Tap mode
! Tap bit
! Sequence length
|-
| 0
| 14
| 32767
|-
| 1
| 10
| 1953
|-
| 2
| 13
| 254
|-
| 3
| 4
| 217
|-
| 4
| 8
| 73
|-
| 5
| 6
| 63
|-
| 6
| 9
| 42
|-
| 7
| 11
| 28
|}

Noise output works using the following algorithm, performed once per sample generated:

# Create a new bit by inverting the XOR of bit 7 with the tap bit.
# Shift the LFSR register one bit to the left.
# Write the new bit as bit 0.
# Use the new bit as if it were a wavetable sample: 0 = 0, 1 = 15.

Note that, for the LFSR register to advance, two of: the channel 4 enable bit and the LFSR enable bit have to be set.

{{Anchor|Sound Wavetable Address}}

=== Sound Wavetable Address ($8F) ===

&lt;pre&gt;
7  bit  0
---- ----
wwww wwww
|||| ||||
++++-++++- Wavetable address (bits 6-13)
&lt;/pre&gt;

{{Anchor|Sound Channel Control}}
=== Sound Channel Control ($90) ===

&lt;pre&gt;
7  bit  0
---- ----
nsv. 4321
|||  ||||
|||  |||+- Channel 1 enable
|||  ||+-- Channel 2 enable
|||  |+--- Channel 3 enable
|||  +---- Channel 4 enable
||+------- Channel 2 voice enable (overrides wavetable enable)
|+-------- Channel 3 sweep: 0 = disable, 1 = enable
+--------- Channel 4 mode: 0 = wavetable, 1 = noise
&lt;/pre&gt;

Note that:

* Channel 1-4 enable bits also control whether or not the sample period counters are active.
* Channel 2's voice mode (bit 5) does not require channel 2's wavetable mode (bit 1) to be enabled.
* Conversely, Channel 4's noise mode (bit 7) ''does'' require channel 4's wavetable mode (bit 3) to be enabled.

{{Anchor|Sound Output Control}}

=== Sound Output Control ($91) ===

&lt;pre&gt;
7  bit  0
---- ----
H... hrrs
|    ||||
|    |||+- Internal speaker output enable
|    |++-- Internal speaker shift/volume:
|    |      0 = 100%   1 = 50%
|    |      2 = 25%    3 = 12.5%
|    +---- Headphone output enable
+--------- Headphones connected, 1 if true
&lt;/pre&gt;

For correct playback on the internal speaker, it is important to set the shift/volume correctly, to match the peak summed output of the first four channels. If the value is too low, music using multiple loud channels will wrap, causing audible distortion. If the value is too high, single-channel PCM sample playback will be very quiet.

{{Anchor|Sound Channel 4 LFSR Register}}

=== Sound Channel 4 LFSR Register ($92, $93 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .rrr rrrr  rrrr rrrr
  ||| ||||  |||| ||||
  +++-++++--++++-++++- Shift register value
&lt;/pre&gt;

{{Anchor|Sound Channel 2 Voice Volume}}
=== Sound Channel 2 Voice Volume ($94) ===

&lt;pre&gt;
7  bit  0
---- ----
.... lLrR
     ||||
     |||+- Right channel 100% volume
     ||+-- Right channel 50% volume
     |+--- Left channel 100% volume
     +---- Left channel 50% volume
&lt;/pre&gt;

This port is used for voice output.

The &lt;code&gt;50% volume&lt;/code&gt; have no effect if their respective &lt;code&gt;100% volume&lt;/code&gt; bits are set.

{{Anchor|Sound Test}}
=== Sound Test ($95) ===

&lt;pre&gt;
7  bit  0
---- ----
cc5? llsh
|||  ||||
|||  |||+- Hold Ch1-4 output updates
|||  ||+-- Use 3072000 Hz CPU clock for sweep
|||  ++--- Hold noise LFSR output
|||        (Differences between bit 2/3
|||        behavior are unknown)
||+------- Force L10/R10 outputs to (channel 2 voice output * 5) &amp; 0x3FF
++-------- Force wavetable for all wavetable inputs:
           00 - normal operation
           01 - Ch2 wavetable
           10 - Ch3 wavetable
           11 - Ch4 wavetable
&lt;/pre&gt;

{{Anchor|Sound Channel Output Right}}

=== Sound Channel Output Right ($96, $97 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Left}}
=== Sound Channel Output Left ($98, $99 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ..ss  ssss ssss
        ||  |||| ||||
        ++--++++-++++- Unsigned 10-bit sample
&lt;/pre&gt;

{{Anchor|Sound Channel Output Sum}}
=== Sound Channel Output Sum ($9A, $9B read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... .sss  ssss ssss
       |||  |||| ||||
       +++--++++-++++- Unsigned 11-bit sample
&lt;/pre&gt;

{{Anchor|Sound Speaker Main Volume}}
=== Sound Speaker Main Volume ($9E) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .... ....  .... ..vv
                   ||
                   ++- Built-in speaker output volume
&lt;/pre&gt;

Writing to this port changes the output volume of the built-in speaker.

While it functions the same way as the SOUND button (and affects the same internal register), pressing the SOUND button does ''not'' update this port's value. However, manual writes do, and those values can be read out.

This port does not affect the headphone output in any way, just like the SOUND button.

TODO: The exact volume levels have not been verified; it's probably either 0, 25, 50, 100% or 0, ~33, ~67, 100%.</text>
    <sha1>e1c200db16d798bf7c82a693addc15f943bea333</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>DMA</title>
  <ns>0</ns>
  <id>31</id>
  <revision>
    <id>562</id>
    <parentid>355</parentid>
    <timestamp>2025-03-11T17:04:59Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Sound DMA */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5275" xml:space="preserve">The WonderSwan Color introduced two DMA blocks:

* General DMA (GDMA) - allowing for fast IRAM/ROM -&gt; IRAM transfers,
* Sound DMA (SDMA) - allowing for IRAM/ROM -&gt; sound transfers in a much less CPU-intensive way than an interrupt.

== General DMA ==

The CPU is stalled immediately after General DMA is enabled; the enable bit is cleared after a completed GDMA operation.

General DMA takes &lt;code&gt;(5 + 2 * words)&lt;/code&gt; cycles to complete, where &lt;code&gt;words&lt;/code&gt; is the number of words (2-bytes) transferred.

General DMA allows source addresses which can be accessed with a 16-bit width and without waitstates; any attempt to access SRAM (8-bit width) or "slow" ROM ($A0 bit 3 set) will cause DMA to immediately return, even if in the middle of processing a transfer.

Note that the 5-cycle cost is not spent for DMA requests for invalid addresses or of length zero; such scenarios take up no cycles.

{{Anchor|GDMA Source Address Low}}
{{Anchor|GDMA Source Address High}}
=== GDMA Source Address ($40, $41, $42) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll lll.
      ||||   |||| ||||   |||| |||
      ++++---++++-++++---++++-++++- Linear source address
                                    ($00000 - $FFFFE)
&lt;/pre&gt;

{{Anchor|GDMA Destination Address}}
=== GDMA Destination Address ($44, $45) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaa.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Destination address in IRAM
&lt;/pre&gt;

GDMA allows destination addresses in IRAM.

{{Anchor|GDMA Length}}
=== GDMA Length ($46, $47) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbb.
 |||| ||||  |||| |||
 ++++-++++--++++-+++-- Transfer length, in words
                       (if including bit 0: in bytes)
&lt;/pre&gt;

{{Anchor|GDMA Control}}
=== GDMA Control ($48) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.. ....
||
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;

== Sound DMA ==

Sound DMA allows copying sample data to either Channel 2 or Hyper Voice automatically while incurring a much lower cost than that of a CPU interrupt.

Features:

* 4000, 6000, 12000, 24000 Hz sample rates.
* '''Auto-repeat''': If enabled, every time the length counter reaches 0, a shadowed copy of the offset and length as written to the I/O ports will be restored. If disabled, bit 7 will automatically clear on transfer completion, same as with General DMA.
* '''Holding''': If enabled, the offset/length counters will be paused, and $00 will be written on every Sound DMA tick as opposed to the value in memory. This does not impact the timing of Sound DMA.

When playing back sound, the visible ports ($4A-$4C, $4E-$50) are the ones updated live; any edits to them are reflected immediately, as well as written to the shadow copy used for auto-repeat.

The enable/disable bit of Sound DMA does not affect the offset/length counters in any way; for example, if a sample is stopped mid-playthrough, then started again, it will pick up right where it left off.

Unlike General DMA, Sound DMA copies data per byte. This means that SRAM is supported as an input source. Also unlike General DMA, streaming from "slow" (&gt;1 cycle) locations is supported; doing so lengthens the duration of Sound DMA. Due to its need to access the external cartridge bus, Sound DMA must use cycles normally reserved for the CPU; it uses &lt;code&gt;6 + N&lt;/code&gt; cycles every 128 cycles, always starting from cycle &lt;code&gt;117 mod 128&lt;/code&gt;. &lt;code&gt;N&lt;/code&gt; refers to the access time of the area from which audio is being streamed from, and is typically 1 cycle.

However, sound DMA enable will fail if the length is set to 0.

{{Anchor|SDMA Source Address Low}}
{{Anchor|SDMA Source Address High}}
=== SDMA Source Address ($4A, $4B, $4C) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Linear source address
                                  ($00000 - $FFFFF)
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Length}}
=== SDMA Length ($4E, $4F, $50) ===

&lt;pre&gt;
23  bit  16 15  bit  8   7  bit  0
 ---- ----   ---- ----   ---- ----
 .... hhhh   llll llll   llll llll
      ||||   |||| ||||   |||| ||||
      ++++---++++-++++---++++-++++- Transfer length, in bytes
&lt;/pre&gt;

Upon writing to any of the bytes, said byte (and only said byte) is copied to a shadow register, used for restoring the offset/length counter when auto-repeat is enabled.

{{Anchor|SDMA Control}}
=== SDMA Control ($52) ===

&lt;pre&gt;
7  bit  0
---- ----
ed.t rhff
|| | ||||
|| | ||++- Frequency/Rate:
|| | ||      0 = 24000/6 =  4000 Hz
|| | ||      1 = 24000/4 =  6000 Hz
|| | ||      2 = 24000/2 = 12000 Hz
|| | ||      3 = 24000/1 = 24000 Hz
|| | |+--- Hold: 0 = normal playback, 1 = hold
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>9cc3aaab0e383c22a5054709b363a587cd90f995</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>563</id>
    <parentid>499</parentid>
    <timestamp>2025-03-15T08:15:18Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Flags ($C) */ I was very wrong</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5200" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? SB?v
     || |
     || +- Starting screen orientation: 0 = horizontal, 1 = vertical
     ||    Controls the splash screen's orientation.
     |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
     +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 2 and 3 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>8bdfdd21764033cb4dcef9ab4ddd71a39b2a47a1</sha1>
  </revision>
  <revision>
    <id>564</id>
    <parentid>563</parentid>
    <timestamp>2025-03-15T08:17:44Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Flags ($C) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5312" xml:space="preserve">Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? SB?v
     || |
     || +- Starting orientation: 0 = horizontal, 1 = vertical
     |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
     +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 2 and 3 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

Bit 0 controls the splash screen's orientation, as well as the LCD segment (horizontal or vertical orientation) displayed during the first 128 ticks of the splash screen.

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>3ba9a19ccd43e29dcb916def3f20cd578dc561e0</sha1>
  </revision>
  <revision>
    <id>600</id>
    <parentid>564</parentid>
    <timestamp>2025-04-23T14:05:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>the ROM padding is still not obvious if it's not written anywhere, and at least two emulators got it wrong already</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5729" xml:space="preserve">Every WonderSwan cartridge ROM contains a header.

The header is stored at the end (the final sixteen bytes) of the ROM image. For this reason, it is also sometimes called a "footer".

A notable consequence of this is that, unlike most other platforms, non-power-of-two ROM images are expected to be padded to the last bank downwards, rather than the first bank upwards; for example, a 768 KiB ROM image will be padded to 1 MiB by appending 256 KiB of padding data to the ''beginning'', rather than the ''end'' of the ROM.

== ROM header ==

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? SB?v
     || |
     || +- Starting orientation: 0 = horizontal, 1 = vertical
     |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
     +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 2 and 3 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

Bit 0 controls the splash screen's orientation, as well as the LCD segment (horizontal or vertical orientation) displayed during the first 128 ticks of the splash screen.

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>1c4dfe0e03c24b47514afc800930c1233221d557</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Bandai 2003</title>
  <ns>0</ns>
  <id>13</id>
  <revision>
    <id>565</id>
    <parentid>396</parentid>
    <timestamp>2025-03-15T16:40:58Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>split out usage information from command notes, more compact command representation</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5413" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;D00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command to port &lt;tt&gt;$CA&lt;/tt&gt; will start a transaction.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access. It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear).

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes sent
! Bytes received
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the PSRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>7e935263ba9095575ea1b58e4ef281536ee44f41</sha1>
  </revision>
  <revision>
    <id>566</id>
    <parentid>565</parentid>
    <timestamp>2025-03-15T16:55:06Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5413" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;R00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command to port &lt;tt&gt;$CA&lt;/tt&gt; will start a transaction.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access. It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear).

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes sent
! Bytes received
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the PSRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>2cea834eb759cd7bc3d7d6aa2b3220cec98df414</sha1>
  </revision>
  <revision>
    <id>567</id>
    <parentid>566</parentid>
    <timestamp>2025-03-15T17:42:46Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5562" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;R00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command (see below) to port &lt;tt&gt;$CA&lt;/tt&gt; will start a command transaction.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access. It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear). Notably, this also means that the bit is set after the final byte is written, despite not requiring another write at that point.

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes sent
! Bytes received
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the PSRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>768fe8b88453637530be6f0790dd1389ea850f90</sha1>
  </revision>
  <revision>
    <id>569</id>
    <parentid>567</parentid>
    <timestamp>2025-03-16T07:13:49Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Commands */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5564" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;R00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command (see below) to port &lt;tt&gt;$CA&lt;/tt&gt; will start a command transaction.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access. It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear). Notably, this also means that the bit is set after the final byte is written, despite not requiring another write at that point.

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes to RTC
! Bytes from RTC
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the PSRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>3715d52040d2d80fe668793ad09932eb70cb9ad0</sha1>
  </revision>
  <revision>
    <id>570</id>
    <parentid>569</parentid>
    <timestamp>2025-03-16T07:32:42Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Real-Time Clock */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5740" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;R00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command (see below) to port &lt;tt&gt;$CA&lt;/tt&gt; will start a command transaction. The value of the command can be read from &lt;tt&gt;$CA&lt;/tt&gt;; for valid commands, bit 4 will be cleared once the command is completed; for invalid commands, bit 4 will remain as written.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access - both after each byte written or read, as well as at the end of a command (including zero-byte commands like &lt;tt&gt;$10&lt;/tt&gt;). It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear).

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes to RTC
! Bytes from RTC
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the PSRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>7485a84ebf82c05f0778a8405accd690678eb5f7</sha1>
  </revision>
  <revision>
    <id>576</id>
    <parentid>570</parentid>
    <timestamp>2025-03-29T11:19:43Z</timestamp>
    <contributor>
      <username>Generic</username>
      <id>362</id>
    </contributor>
    <comment>SRAM instead of PSRAM area (too much nileswan :) )</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5739" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;R00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command (see below) to port &lt;tt&gt;$CA&lt;/tt&gt; will start a command transaction. The value of the command can be read from &lt;tt&gt;$CA&lt;/tt&gt;; for valid commands, bit 4 will be cleared once the command is completed; for invalid commands, bit 4 will remain as written.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access - both after each byte written or read, as well as at the end of a command (including zero-byte commands like &lt;tt&gt;$10&lt;/tt&gt;). It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear).

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes to RTC
! Bytes from RTC
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the SRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>f64cb4c92f5c5b2c81dc8c8c92440c5be7812077</sha1>
  </revision>
  <revision>
    <id>578</id>
    <parentid>576</parentid>
    <timestamp>2025-04-03T16:47:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Usage */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5810" xml:space="preserve">The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="3" | RTC
! rowspan="2" | $CA
| RTC Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...1 CCCC&lt;/tt&gt;
| W8
| Command (C)
|-
| RTC Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;R00B CCCC&lt;/tt&gt;
| R8
| Busy (B), Command (C), Ready (R)
|-
! $CB
| RTC Payload
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| RW8
| Data (d)
|-
! rowspan="2" | GPO
! $CC
| GPO Data Direction
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 oooo&lt;/tt&gt;
| RW8
| 1 = output, 0 = high-impedance (weak pull-down)
|-
! $CD
| GPO Data
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 dddd&lt;/tt&gt;
| RW8
| 1 = 3V, if enabled by data direction
|-
! Self-Flash
! $CE
| Self-Flash Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 000r&lt;/tt&gt;
| RW8
| 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region.
|-
! rowspan="4" | Extended bankswitching
! $CF
| ROM Linear (EX) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;00bb bbbb&lt;/tt&gt;
| RW8
| Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port.
|-
! $D0
| RAM(/ROM) Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port.
|-
! $D2
| ROM0 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port.
|-
! $D4
| ROM1 Bank
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0000 00bb bbbb bbbb&lt;/tt&gt;
| RW16
| Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port.
|}

== Real-Time Clock ==

The 2003's RTC interface is a simple half-duplex SPI-like protocol.

For specifics of what the S-3511A expects to be done with these bytes, see [[Real-Time Clock]].

=== Usage ===

Writing a valid command (see below) to port &lt;tt&gt;$CA&lt;/tt&gt; will start a command transaction. The value of the command can be read from &lt;tt&gt;$CA&lt;/tt&gt;; for valid commands, bit 4 will be cleared once the command is completed; for invalid commands, bit 4 will remain as written.

The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.

The Ready bit is set when &lt;tt&gt;$CB&lt;/tt&gt; is ready for access - both after each byte written or read, as well as at the end of a command (including zero-byte commands like &lt;tt&gt;$10&lt;/tt&gt;). It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear). Writing a new command to port &lt;tt&gt;$CA&lt;/tt&gt; also clears the Ready bit. 

For commands which require bytes to be sent, the first byte should be written to port &lt;tt&gt;$CB&lt;/tt&gt; before starting the command with a port &lt;tt&gt;$CA&lt;/tt&gt; write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.

For commands which return bytes to be read, they can be accessed through port &lt;tt&gt;$CB&lt;/tt&gt; after the Ready bit is set or if the Busy bit is clear.

If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.

=== Commands ===

Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.

Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

{| class="wikitable"
! Command
! Command byte
! Bytes to RTC
! Bytes from RTC
|-
| &lt;tt&gt;$00&lt;/tt&gt; - &lt;tt&gt;$0F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|-
| &lt;tt&gt;$10&lt;/tt&gt;
| &lt;tt&gt;$60&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$11&lt;/tt&gt;
| &lt;tt&gt;$61&lt;/tt&gt;
| colspan="2" | None
|-
| &lt;tt&gt;$12&lt;/tt&gt;
| &lt;tt&gt;$62&lt;/tt&gt;
| style="text-align:right;" | 1
| 
|-
| &lt;tt&gt;$13&lt;/tt&gt;
| &lt;tt&gt;$63&lt;/tt&gt;
|
| style="text-align:right;" | 1
|-
| &lt;tt&gt;$14&lt;/tt&gt;
| &lt;tt&gt;$64&lt;/tt&gt;
| style="text-align:right;" | 7
| 
|-
| &lt;tt&gt;$15&lt;/tt&gt;
| &lt;tt&gt;$65&lt;/tt&gt;
|
| style="text-align:right;" | 7
|-
| &lt;tt&gt;$16&lt;/tt&gt;
| &lt;tt&gt;$66&lt;/tt&gt;
| style="text-align:right;" | 3
| 
|-
| &lt;tt&gt;$17&lt;/tt&gt;
| &lt;tt&gt;$67&lt;/tt&gt;
|
| style="text-align:right;" | 3
|-
| &lt;tt&gt;$18&lt;/tt&gt;
| &lt;tt&gt;$68&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$19&lt;/tt&gt;
| &lt;tt&gt;$69&lt;/tt&gt;
|
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1A&lt;/tt&gt;
| &lt;tt&gt;$6A&lt;/tt&gt;
| style="text-align:right;" | 2
| 
|-
| &lt;tt&gt;$1B&lt;/tt&gt;
| &lt;tt&gt;$6B&lt;/tt&gt;
| 
| style="text-align:right;" | 2
|-
| &lt;tt&gt;$1C&lt;/tt&gt; - &lt;tt&gt;$1F&lt;/tt&gt;
| colspan="3" style="text-align:center;" | N/A
|}

== Self-flashing ==

The 2003 mapper allows mapping the ROM chip in the SRAM area using the &lt;tt&gt;$CE&lt;/tt&gt; port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.

Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.

== Lockout ==

Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)</text>
    <sha1>2740b30b5a2b4270325af5c85851e78ac18d74c5</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>568</id>
    <parentid>407</parentid>
    <timestamp>2025-03-15T17:48:47Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>$C4 is separate for read and write</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1700" xml:space="preserve">The Bandai 2001 (LUXSOR) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="4" | External EEPROM
! rowspan="2" | $C4
| rowspan="2" | External EEPROM Data
| rowspan="2" style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| R16
| Data read (d)
|-
| W16
| Data to write (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;&lt;br/&gt;or &lt;tt style="white-space: nowrap"&gt;0000 01CC aaaa aaaa&lt;/tt&gt;&lt;br/&gt; or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ASWR ....&lt;/tt&gt;
| W8
| Abort (A), Short (S), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

== EEPROM ==

The 2001's EEPROM interface is similar to the internal EEPROM interface, as documented on [[EEPROM#I/O_ports|the EEPROM page]]. Differences include:

* Instead of the internal EEPROM interface's P(rotect) bit, the A(bort) bit is provided. When the A bit is set, the transaction immediately stops.
* The EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

(Upload logic analyzer traces here)</text>
    <sha1>d483574f7c004b3fd1f53432b89ecb121c9a953c</sha1>
  </revision>
  <revision>
    <id>571</id>
    <parentid>568</parentid>
    <timestamp>2025-03-16T08:24:07Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <minor/>
    <comment>forgot this</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1700" xml:space="preserve">The Bandai 2001 (LUXSOR) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="5" | External EEPROM
! rowspan="2" | $C4
| rowspan="2" | External EEPROM Data
| rowspan="2" style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| R16
| Data read (d)
|-
| W16
| Data to write (d)
|-
! $C6
| External EEPROM Command
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;&lt;br/&gt;or &lt;tt style="white-space: nowrap"&gt;0000 01CC aaaa aaaa&lt;/tt&gt;&lt;br/&gt; or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| External EEPROM Control
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ASWR ....&lt;/tt&gt;
| W8
| Abort (A), Short (S), Write (W), Read (R)
|-
| External EEPROM Status
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}

== EEPROM ==

The 2001's EEPROM interface is similar to the internal EEPROM interface, as documented on [[EEPROM#I/O_ports|the EEPROM page]]. Differences include:

* Instead of the internal EEPROM interface's P(rotect) bit, the A(bort) bit is provided. When the A bit is set, the transaction immediately stops.
* The EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).

(Upload logic analyzer traces here)</text>
    <sha1>f6ce0674399d0e5074cb484a759092e82983baf7</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Splash animation</title>
  <ns>0</ns>
  <id>34</id>
  <revision>
    <id>573</id>
    <parentid>165</parentid>
    <timestamp>2025-03-23T12:52:02Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Format */ Name color is not part of splash data; it's user-editable</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2564" xml:space="preserve">The WonderSwan Color upgraded the [[EEPROM|internal EEPROM]] from 128 bytes to 2 kilobytes; most of the additional space is utilized to allow for branding consoles in the form of unique, custom splash animations on console startup.

== Format ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $85 || 1 || Must be $00
|-
| $86 || 1 || Size; 0 = ends at &lt;= $3FF, 1 = ends at &lt;= $7FF
|-
| $87 || 1 || First frame
|-
| $88 || 1 || Last frame
|-
| $89 || 1 || Sprite count
|-
| $8A || 1 || Palette flags
|-
| $8B || 1 || Tile count
|-
| $8C || 2 || Palette location - $80
|-
| $8E || 2 || Tile data location - $80
|-
| $90 || 2 || Tilemap location - $80
|-
| $92 || 2 || Screen offset (Horizontal)
|-
| $94 || 2 || Screen offset (Vertical)
|-
| $96 || 1 || Tilemap width
|-
| $97 || 1 || Tilemap height
|-
| $98 || 2 || VBlank IRQ handler offset
|-
| $9A || 2 || VBlank IRQ handler segment, must be $0600
|-
| $9C || 1 || Owner name X (horizontal)
|-
| $9D || 1 || Owner name Y (horizontal)
|-
| $9E || 1 || Owner name X (vertical)
|-
| $9F || 1 || Owner name Y (vertical)
|-
| $A0 || 2 || Padding, unused
|-
| $A2 || 2 || Sound wavetable location - $80
|-
| $A4 || 2 || Sound channel 1 data offset - $80
|-
| $A6 || 2 || Sound channel 2 data offset - $80
|-
| $A8 || 2 || Sound channel 3 data offset - $80
|-
| $AA || 2 || Sound channel 4 data offset - $80
|-
| $AC || 10 || SwanCrystal TFT LCD configuration
|-
| $B6 || 10 || Padding, unused
|-
| $C0 || ... || Arbitrary data - palettes, tilemaps, etc.
|}

=== Palette flags ===

&lt;pre&gt;
7  bit  0
---- ----
b..p pppp
|  +-++++- Palette count (0-16)
+--------- Tile/palette bits per pixel:
             0 = 1 bit per pixel
             1 = 2 bits per pixel
&lt;/pre&gt;

=== Name colors ===

{| class="wikitable"
|-
! Value !! RGB code
|-
| 0 || #000
|-
| 1 || #f00
|-
| 2 || #f70
|-
| 3 || #ff0
|-
| 4 || #7f0
|-
| 5 || #0f0
|-
| 6 || #0f7
|-
| 7 || #0ff
|-
| 8 || #07f
|-
| 9 || #00f
|-
| 10 || #70f
|-
| 11 || #f0f
|-
| 12 || #f07
|}

=== VBlank IRQ handler ===

A custom splash animation ''must'' provide a valid VBlank IRQ handler, with the following rules:

* The segment must be ''0x0600''; the offset is provided relative to ''$80'', as with other data offsets.
* The code must end with a ''retf'' opcode, or equivalent.

=== Horizontal/Vertical orientation handling ===

The splash animation loader will automatically rotate the tile data and tilemap when booting a cartridge whose [[ROM header|header]] declares vertical orientation as its startup orientation.

=== Sound channel data format ===

TODO</text>
    <sha1>4b652cb09cdf4d0c2ea0dce11eb0d39d2563c0e9</sha1>
  </revision>
  <revision>
    <id>574</id>
    <parentid>573</parentid>
    <timestamp>2025-03-23T12:52:53Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Format */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2297" xml:space="preserve">The WonderSwan Color upgraded the [[EEPROM|internal EEPROM]] from 128 bytes to 2 kilobytes; most of the additional space is utilized to allow for branding consoles in the form of unique, custom splash animations on console startup.

== Format ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $85 || 1 || Must be $00
|-
| $86 || 1 || Size; 0 = ends at &lt;= $3FF, 1 = ends at &lt;= $7FF
|-
| $87 || 1 || First frame
|-
| $88 || 1 || Last frame
|-
| $89 || 1 || Sprite count
|-
| $8A || 1 || Palette flags
|-
| $8B || 1 || Tile count
|-
| $8C || 2 || Palette location - $80
|-
| $8E || 2 || Tile data location - $80
|-
| $90 || 2 || Tilemap location - $80
|-
| $92 || 2 || Screen offset (Horizontal)
|-
| $94 || 2 || Screen offset (Vertical)
|-
| $96 || 1 || Tilemap width
|-
| $97 || 1 || Tilemap height
|-
| $98 || 2 || VBlank IRQ handler offset
|-
| $9A || 2 || VBlank IRQ handler segment, must be $0600
|-
| $9C || 1 || Owner name X (horizontal)
|-
| $9D || 1 || Owner name Y (horizontal)
|-
| $9E || 1 || Owner name X (vertical)
|-
| $9F || 1 || Owner name Y (vertical)
|-
| $A0 || 2 || Padding, unused
|-
| $A2 || 2 || Sound wavetable location - $80
|-
| $A4 || 2 || Sound channel 1 data offset - $80
|-
| $A6 || 2 || Sound channel 2 data offset - $80
|-
| $A8 || 2 || Sound channel 3 data offset - $80
|-
| $AA || 2 || Sound channel 4 data offset - $80
|-
| $AC || 10 || SwanCrystal TFT LCD configuration
|-
| $B6 || 10 || Padding, unused
|-
| $C0 || ... || Arbitrary data - palettes, tilemaps, etc.
|}

=== Palette flags ===

&lt;pre&gt;
7  bit  0
---- ----
b..p pppp
|  +-++++- Palette count (0-16)
+--------- Tile/palette bits per pixel:
             0 = 1 bit per pixel
             1 = 2 bits per pixel
&lt;/pre&gt;

=== VBlank IRQ handler ===

A custom splash animation ''must'' provide a valid VBlank IRQ handler, with the following rules:

* The segment must be ''0x0600''; the offset is provided relative to ''$80'', as with other data offsets.
* The code must end with a ''retf'' opcode, or equivalent.

=== Horizontal/Vertical orientation handling ===

The splash animation loader will automatically rotate the tile data and tilemap when booting a cartridge whose [[ROM header|header]] declares vertical orientation as its startup orientation.

=== Sound channel data format ===

TODO</text>
    <sha1>39a6f2560d6dea6ce50c52e602a45dce6aba957b</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>575</id>
    <parentid>408</parentid>
    <timestamp>2025-03-23T12:55:37Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Internal EEPROM Layout */ Move name color information, add missing color 13</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9752" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

The WRAL command erases the word at all address of the EEPROM, setting them to 0xFFFF.

This command is not guaranteed to be present on all EEPROMs.

=== ERAL - Erase All ===

The WRAL command takes a word and writes it to all addresses of the EEPROM.

This command is not guaranteed to be present on all EEPROMs.

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Internal EEPROM Layout ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - 0&lt;br/&gt;
4 - AB
|-
| $76 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID)
|-
| $77 || 1 || Last booted [[ROM header]] byte 7 (color)
|-
| $78 || 1 || Last booted [[ROM header]] byte 8 (game ID)
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $80 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID) - only changed if byte 7 (color) != 0
|-
| $81 || 1 || Last booted [[ROM header]] byte 7 (color) - only changed if byte 7 (color) != 0
|-
| $82 || 1 || Last booted [[ROM header]] byte 8 (game ID) - only changed if byte 7 (color) != 0
|-
| $83 || 1 || Color model configuration
|-
| $84 || 1 || Name color
|-
| $85 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color model configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

=== Name colors ===

{| class="wikitable"
|-
! Value !! RGB code
|-
| 0 || #000
|-
| 1 || #f00
|-
| 2 || #f70
|-
| 3 || #ff0
|-
| 4 || #7f0
|-
| 5 || #0f0
|-
| 6 || #0f7
|-
| 7 || #0ff
|-
| 8 || #07f
|-
| 9 || #00f
|-
| 10 || #70f
|-
| 11 || #f0f
|-
| 12 || #f07
|-
| 13 || #fff
|}

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>a92da19fd6123c51381f5e4e7468811f1fc7cdd0</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>SoC</title>
  <ns>0</ns>
  <id>46</id>
  <revision>
    <id>577</id>
    <parentid>536</parentid>
    <timestamp>2025-03-30T10:58:40Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* System Control 3 ($62, color) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1947" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
C??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- Cartridge bus test OK
&lt;/pre&gt;

{{Anchor|System Control 2}}

=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Request power off
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

After setting the "request power off" bit to 1, halting the CPU will cause the console to shut down.

TODO: &lt;tt&gt;$AC&lt;/tt&gt; bit 0 seems to also shut down the console.

== Notes ==
&lt;references /&gt;</text>
    <sha1>1bb73bcf72d3dd12d046bc365cbe176c3b2d5632</sha1>
  </revision>
  <revision>
    <id>586</id>
    <parentid>577</parentid>
    <timestamp>2025-04-08T19:51:08Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O ports */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2483" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
C??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- Cartridge bus test OK
&lt;/pre&gt;

{{Anchor|System Control 2}}

=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i?sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Request power off
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

After setting the "request power off" bit to 1, halting the CPU will cause the console to shut down.

TODO: &lt;tt&gt;$AC&lt;/tt&gt; bit 0 seems to also shut down the console.

{{Anchor|System Test}}
=== System Test ($A3) ===

Note that this port is only writable as a byte - writing a word to &lt;tt&gt;$A2&lt;/tt&gt; does not write to this byte.

&lt;pre&gt;
7  bit  0
---- ----
.... u?vh
     | |+- Enable HBlank Timer test
     | +-- Enable VBlank Timer test
     +---- Enable UART test
&lt;/pre&gt;

The timer tests ignore the reload value and clock the timers at 3072000? Hz. The enable bit is still respected.

The UART test disables the 9600/38400 baud clock divider, instead operating the EXT port's UART lines at 192000 baud.

== Notes ==
&lt;references /&gt;</text>
    <sha1>882227f0af58d4bdad1977deb018a75002bbe342</sha1>
  </revision>
  <revision>
    <id>587</id>
    <parentid>586</parentid>
    <timestamp>2025-04-09T15:53:19Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* System Control 2 ($60, color) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2483" xml:space="preserve">The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.

There exist three variants of the SoC:

* ASWAN, used in the WonderSwan,
* SPHINX, used in the WonderSwan Color,
* SPHINX2, used in the SwanCrystal.

A fourth variant, CAIRO, was planned&lt;ref&gt;[https://web.archive.org/web/20071023111112/http://www.koto.co.jp/products/mono_sp.html CAIRO グラフィックス機能内蔵ローコストSoC - Wayback Machine]&lt;/ref&gt;. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.

== I/O ports ==

{{Anchor|System Control}}
=== System Control ($A0) ===

&lt;pre&gt;
7  bit  0
---- ----
C??? swcl
|    ||||
|    |||+- Boot ROM lockout: 0 = off, 1 = on
|    ||+-- Color model: 0 = no, 1 = yes
|    |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
|    +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
+--------- Cartridge bus test OK
&lt;/pre&gt;

{{Anchor|System Control 2}}

=== System Control 2 ($60, color) ===

&lt;pre&gt;
7  bit  0
---- ----
c4C. i.sl
|||  | ||
|||  | |+- Cartridge clock speed?
|||  | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1
|||  +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1
||+------- 1 = 4bpp "chunky"; requires all previous
|+-------- 1 = 4bpp; requires all previous
+--------- 0 = mono, 1 = color; also controls access
           to WSC-specific features (extra RAM, DMA, etc.)
&lt;/pre&gt;

{{Anchor|System Control 3}}

=== System Control 3 ($62, color) ===

&lt;pre&gt;
7  bit  0
---- ----
S... ...p
|       |
|       +- 1 = Request power off
+--------- 0 = WonderSwan Color (SPHINX)
           1 = SwanCrystal (SPHINX2)
&lt;/pre&gt;

After setting the "request power off" bit to 1, halting the CPU will cause the console to shut down.

TODO: &lt;tt&gt;$AC&lt;/tt&gt; bit 0 seems to also shut down the console.

{{Anchor|System Test}}
=== System Test ($A3) ===

Note that this port is only writable as a byte - writing a word to &lt;tt&gt;$A2&lt;/tt&gt; does not write to this byte.

&lt;pre&gt;
7  bit  0
---- ----
.... u?vh
     | |+- Enable HBlank Timer test
     | +-- Enable VBlank Timer test
     +---- Enable UART test
&lt;/pre&gt;

The timer tests ignore the reload value and clock the timers at 3072000? Hz. The enable bit is still respected.

The UART test disables the 9600/38400 baud clock divider, instead operating the EXT port's UART lines at 192000 baud.

== Notes ==
&lt;references /&gt;</text>
    <sha1>1a6546b17338d56187e46ca85e1b974452052127</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Real-Time Clock</title>
  <ns>0</ns>
  <id>40</id>
  <revision>
    <id>579</id>
    <parentid>548</parentid>
    <timestamp>2025-04-07T13:54:24Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Time */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6727" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values; however, writes to the bit are ignored.

Writing invalid hour values (larger than &lt;tt&gt;$11&lt;/tt&gt; or &lt;tt&gt;$23&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

Writing invalid minute values (larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

Writing invalid second values (larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) stores the value, but forces a rollover after one second has passed.

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

=== Initial power on state ===

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$82&lt;/tt&gt;
* Alarm = &lt;tt&gt;$8000&lt;/tt&gt;

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>c2f4b4c7489a97946375f405796527dd7c91f4fd</sha1>
  </revision>
  <revision>
    <id>580</id>
    <parentid>579</parentid>
    <timestamp>2025-04-07T13:54:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Time */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6742" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, the AM/PM bit is set for values larger than or equal to &lt;tt&gt;$12&lt;/tt&gt;. Writes to the bit are ignored.

Writing invalid hour values (larger than &lt;tt&gt;$11&lt;/tt&gt; or &lt;tt&gt;$23&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

Writing invalid minute values (larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

Writing invalid second values (larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) stores the value, but forces a rollover after one second has passed.

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

=== Initial power on state ===

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$82&lt;/tt&gt;
* Alarm = &lt;tt&gt;$8000&lt;/tt&gt;

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>a66307d77a442be79dd3c038e6a6c5e76cd47471</sha1>
  </revision>
  <revision>
    <id>583</id>
    <parentid>580</parentid>
    <timestamp>2025-04-08T18:50:15Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Interrupt mode: Alarm */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6748" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, the AM/PM bit is set for values larger than or equal to &lt;tt&gt;$12&lt;/tt&gt;. Writes to the bit are ignored.

Writing invalid hour values (larger than &lt;tt&gt;$11&lt;/tt&gt; or &lt;tt&gt;$23&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

Writing invalid minute values (larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

Writing invalid second values (larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) stores the value, but forces a rollover after one second has passed.

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must have the AM/PM bit set correctly, even in 24-hour mode.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

=== Initial power on state ===

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$82&lt;/tt&gt;
* Alarm = &lt;tt&gt;$8000&lt;/tt&gt;

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>18e53acbace084e1d118a51793425bb62cc70da9</sha1>
  </revision>
  <revision>
    <id>598</id>
    <parentid>583</parentid>
    <timestamp>2025-04-21T09:58:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Registers */ document date boundary conditions</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="7441" xml:space="preserve">The [[Bandai 2003|2003]] mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

== Registers ==

=== Configuration ===

 7  bit  0
 ---- ----
 p2a0 m0f0
 |||  | | 
 ||+--+-+-- Interrupt mode; see below
 |+-------- 12/24 hour mode
 |          - 0: 12 hour mode
 |          - 1: 24 hour mode
 +--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

==== Interrupt mode ====

{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}

=== Date/Time ===

The date and time is stored using seven bytes, of which the latter three correspond to the time.

==== Date ====

 7  bit  0
 ---- ----  Byte 0
 yyyy yyyy
 |||| ||||
 ++++-++++- Year (00 - 99, BCD)

Writing invalid year values (non-BCD) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 1
 ...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)

Writing invalid month values (non-BCD, &lt;tt&gt;$00&lt;/tt&gt;, or larger than &lt;tt&gt;$12&lt;/tt&gt;) writes &lt;tt&gt;$01&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 2
 ..dd dddd
   || ||||
   ++-++++- Day of month (01 - 31, BCD)

Writing invalid day of month values (non-BCD, &lt;tt&gt;$00&lt;/tt&gt;, or larger than &lt;tt&gt;$31&lt;/tt&gt;) writes &lt;tt&gt;$01&lt;/tt&gt; instead.

If the day of month is smaller than or equal to &lt;tt&gt;$31&lt;/tt&gt;, but larger than the maximum day of month in a given year/month pair, the year/month is automatically incremented and the month is set to &lt;tt&gt;$01&lt;/tt&gt;

 7  bit  0
 ---- ----  Byte 3
 .... .www
       |||
       +++- Day of week (0 - 6)

Writing invalid day of week values (non-BCD or larger than &lt;tt&gt;$06&lt;/tt&gt;) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

==== Time ====

 7  bit  0
 ---- ----  Byte 4
 p.hh hhhh
 | || ||||
 | ++-++++- Hour (00 - 11 or 23, BCD)
 +--------- 0 = AM, 1 = PM

In the 24-hour mode, the AM/PM bit is set for values larger than or equal to &lt;tt&gt;$12&lt;/tt&gt;. Writes to the bit are ignored.

Writing invalid hour values (non-BCD or larger than &lt;tt&gt;$11 &amp; $1F&lt;/tt&gt; in 12-hour mode, or &lt;tt&gt;$23 &amp; $3F&lt;/tt&gt; in 24-hour mode, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 5
 .mmm mmmm
  ||| ||||
  +++-++++- Minute (00 - 59, BCD)

Writing invalid minute values (non-BCD or larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) writes &lt;tt&gt;$00&lt;/tt&gt; instead.

 7  bit  0
 ---- ----  Byte 6
 .sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)

Writing invalid second values (non-BCD or larger than &lt;tt&gt;$59&lt;/tt&gt;, or with an invalid low digit) stores the value, but forces a rollover after one second has passed.

=== Alarm configuration ===

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

==== Interrupt mode: Alarm ====

 7  bit  0
 ---- ----  Byte 0
 p.hh hhhh
 | || ||||
 | ++-++++- Hour to match for the alarm (BCD)
 +--------- AM/PM bit to match for the alarm

 7  bit  0
 ---- ----  Byte 1
 .mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must have the AM/PM bit set correctly, even in 24-hour mode.

==== Interrupt mode: Frequency ====

 7  bit  0
 ---- ----  Byte 0
 abcd efgh
 |||| ||||
 |||| |||+- 32768 Hz
 |||| ||+-- 16384 Hz
 |||| |+---  8192 Hz
 |||| +----  4096 Hz
 |||+------  2048 Hz
 ||+-------  1024 Hz
 |+--------   512 Hz
 +---------   256 Hz

 7  bit  0
 ---- ----  Byte 1
 abcd efgh
 |||| ||||
 |||| |||+-   128 Hz
 |||| ||+--    64 Hz
 |||| |+---    32 Hz
 |||| +----    16 Hz
 |||+------     8 Hz
 ||+-------     4 Hz
 |+--------     2 Hz
 +---------     1 Hz

=== Initial power on state ===

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$82&lt;/tt&gt;
* Alarm = &lt;tt&gt;$8000&lt;/tt&gt;

== Commands ==

=== Reset RTC ($10, $11) ===
Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the following registers:

* Year = &lt;tt&gt;$00&lt;/tt&gt;
* Month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of month = &lt;tt&gt;$01&lt;/tt&gt;
* Day of week = &lt;tt&gt;$00&lt;/tt&gt;
* Hour = &lt;tt&gt;$00&lt;/tt&gt;
* Minute = &lt;tt&gt;$00&lt;/tt&gt;
* Second = &lt;tt&gt;$00&lt;/tt&gt;
* Configuration = &lt;tt&gt;$00&lt;/tt&gt;
* Alarm = &lt;tt&gt;$0000&lt;/tt&gt;

It is unknown if it resets the sub-second prescaler.

=== Write Configuration ($12) ===
Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

=== Read Configuration ($13) ===
Writing $13 to port $CA will send the "get configuration" command to the RTC.

=== Write current YMDdHMS ($14) ===
Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Read current YMDdHMS ($15) ===
Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

=== Write current HMS ($16) ===
Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

=== Read current HMS ($17) ===
Writing $17 will get the current Hour, Minute, and Second.

=== Write alarm configuration ($18) ===
Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

=== Nonsense alarm configuration ($19) ===
Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees.
$FFFF will be read back by the 2003.

=== Write nonsense ($1A) ===
Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

=== Read nonsense ($1B) ===
Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

== Interrupts ==
The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:
* all communication to the 2003 happens while cartridge IRQs are disabled, or
* the only thing the interrupt handler can do is [[Interrupts#Interrupt_Enable|mask]] the interrupt and then [[Interrupts#Interrupt_Acknowledge|acknowledge]] it, and only afterwards handle any subsequent communication.</text>
    <sha1>d9929b306e2af96fd36e57fc4d482c80d82f43e0</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>581</id>
    <parentid>533</parentid>
    <timestamp>2025-04-08T15:33:05Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */ bits 0-2 on translucent mono palettes are always 0 - thanks, FluBBa!</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22430" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! rowspan="5" | [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>cd1b703f0f763ddee3531a7048ced3449f43c1ec</sha1>
  </revision>
  <revision>
    <id>584</id>
    <parentid>581</parentid>
    <timestamp>2025-04-08T19:49:04Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22641" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! [[SoC]]
! $A3
| [[SoC#System Test|System Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... u?vh&lt;/tt&gt;
| RW8
| UART test (u), VBlank Timer test (v), HBlank Timer test (h)
|-
! rowspan="4" | [[Timers]]
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! ?
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>c4485579c02dc8a21e66eb6f95ffb5acd99eb17e</sha1>
  </revision>
  <revision>
    <id>585</id>
    <parentid>584</parentid>
    <timestamp>2025-04-08T19:49:21Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22647" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i?sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! [[SoC]]
! $A3
| [[SoC#System Test|System Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... u?vh&lt;/tt&gt;
| RW8
| UART test (u), VBlank Timer test (v), HBlank Timer test (h)
|-
! rowspan="4" | [[Timers]]
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[SoC]]
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>e4242fa517af23ae9cb649598cf0f0ab3ddfcdc2</sha1>
  </revision>
  <revision>
    <id>588</id>
    <parentid>585</parentid>
    <timestamp>2025-04-09T15:53:41Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22647" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i.sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;425? ???h&lt;/tt&gt;
| RW8
|
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! [[SoC]]
! $A3
| [[SoC#System Test|System Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... u?vh&lt;/tt&gt;
| RW8
| UART test (u), VBlank Timer test (v), HBlank Timer test (h)
|-
! rowspan="4" | [[Timers]]
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[SoC]]
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>a7b2424416f99e50d10425815c41ba3f8e4a96bf</sha1>
  </revision>
  <revision>
    <id>597</id>
    <parentid>588</parentid>
    <timestamp>2025-04-20T18:16:51Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22648" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i.sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mask (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cc5? ??sh&lt;/tt&gt;
| RW8
| 
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! [[SoC]]
! $A3
| [[SoC#System Test|System Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... u?vh&lt;/tt&gt;
| RW8
| UART test (u), VBlank Timer test (v), HBlank Timer test (h)
|-
! rowspan="4" | [[Timers]]
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[SoC]]
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>43c3c8ad0999a682ba5994e11de3947205661e2f</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>Display/IO Ports</title>
  <ns>0</ns>
  <id>74</id>
  <revision>
    <id>582</id>
    <parentid>545</parentid>
    <timestamp>2025-04-08T15:33:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Mono Palette 0..15 ($20, $21 .. $3E, $3F) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="9503" xml:space="preserve">== Graphics I/O ports ==

{{Anchor|Display Control}}
=== Display Control ($00) ===

&lt;pre&gt;
7  bit  0
---- ----
..wo Ws21
  || ||||
  || |||+- Enable Screen 1 layer
  || ||+-- Enable Screen 2 layer
  || |+--- Enable Sprite layer
  || +---- Enable Sprite window
  |+------ Screen 2 tiles are drawn (if window enabled):
  |        0 = inside window,
  |        1 = outside window.
  +------- Enable Screen 2 window
&lt;/pre&gt;

{{Anchor|Display Background}}

=== Display Background Color ($01) ===

&lt;pre&gt;
  (mono)             (color)
7  bit  0           7  bit  0
---- ----           ---- ----
.... .sss           pppp iiii
      |||           |||| ||||
      +++- Value    |||| ++++- Index in palette (0-15)
           (0-7)    ++++------ Color palette (0-15)
&lt;/pre&gt;

{{Anchor|Display Current Line}}
=== Display Current Line ($02 read) ===

The current line being drawn by the display.

Note that lines are sent to the display with a one-line delay. This matters for color palette or shade LUT manipulation; changing these values when &lt;code&gt;current line == 1&lt;/code&gt; will actually affect line 0.

{{Anchor|Display Interrupt Line}}
=== Display Interrupt Line ($03) ===

The line to emit an interrupt on.

{{Anchor|Sprite Table Address}}
=== Sprite Table Address ($04) ===

&lt;pre&gt;
7  bit  0
---- ----
..Aa aaaa
  || ||||
  |+-++++- Address (bits 9-13)
  +------- Address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Sprite Table First}}
=== Sprite Table First ($05) ===

&lt;pre&gt;
7  bit  0
---- ----
.iii iiii
 ||| ||||
 +++-++++- Index of first sprite entry to draw (0-127)
&lt;/pre&gt;

{{Anchor|Sprite Table Count}}
=== Sprite Table Count ($06) ===

&lt;pre&gt;
7  bit  0
---- ----
cccc cccc
|||| ||||
++++-++++- Count of sprite entries to draw (1-128)
&lt;/pre&gt;

{{Anchor|Screen Address}}
=== Screen Address ($07) ===

&lt;pre&gt;
7  bit  0
---- ----
2222 1111
|||| ||||
|||| |+++- Screen 1 address (bits 11-13)
|||| +---- Screen 1 address (bit 14) - color only
|+++------ Screen 2 address (bits 11-13)
+--------- Screen 2 address (bit 14) - color only
&lt;/pre&gt;

{{Anchor|Screen 2 Window}}
=== Screen 2 Window Left ($08) ===
=== Screen 2 Window Top ($09) ===
=== Screen 2 Window Right ($0A) ===
=== Screen 2 Window Bottom ($0B) ===

The X and Y coordinates of the Screen 2 window.

Note that all coordinates are inclusive; for example, for a 200x100 window in the top-left corner, the values should be set as follows:

* Left - 0,
* Top - 0,
* Right - 199,
* Bottom - 99.

{{Anchor|Sprite Window}}

=== Sprite Window Left ($0C) ===
=== Sprite Window Top ($0D) ===
=== Sprite Window Right ($0E) ===
=== Sprite Window Bottom ($0F) ===

The X and Y coordinates of the Sprite window.

Note that all coordinates are inclusive.

{{Anchor|Screen Scroll}}

=== Screen 1 Scroll X ($10) ===
=== Screen 1 Scroll Y ($11) ===

The X and Y coordinates that Screen 1 is scrolled by.

For example, setting Scroll X to 24 and Scroll Y to 8 will omit, in 8x8 tile units, the first three rows and the first two columns of the 32x32 screen.

=== Screen 2 Scroll X ($12) ===
=== Screen 2 Scroll Y ($13) ===

The X and Y coordinates that Screen 2 is scrolled by.

== Palette I/O ports ==

These I/O ports are only used in the monochrome display mode. Color display modes use the memory locations &lt;tt&gt;$FE00&lt;/tt&gt; - &lt;tt&gt;$FFFF&lt;/tt&gt; to store the color palette.

{{Anchor|LCD Mono Shade LUT}}

=== Mono Shade LUT ($1C, $1D, $1E, $1F) ===

&lt;pre&gt;
   $1C         $1D         $1E         $1F
7  bit  0   7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----   ---- ----
1111 0000   3333 2222   5555 4444   7777 6666
|||| ||||   |||| ||||   |||| ||||   |||| ||||
|||| ||||   |||| ||||   |||| ||||   |||| ++++- Shade for LUT index 6
|||| ||||   |||| ||||   |||| ||||   ++++------ Shade for LUT index 7
|||| ||||   |||| ||||   |||| ++++------------- Shade for LUT index 4
|||| ||||   |||| ||||   ++++------------------ Shade for LUT index 5
|||| ||||   |||| ++++------------------------- Shade for LUT index 2
|||| ||||   ++++------------------------------ Shade for LUT index 3
|||| ++++------------------------------------- Shade for LUT index 0
++++------------------------------------------ Shade for LUT index 1
&lt;/pre&gt;

{{Anchor|LCD Mono Palette}}
=== Mono Palette 0..15 ($20, $21 .. $3E, $3F) ===

The monochrome palette is laid out as sixteen words:

&lt;pre&gt;
    N+1         N
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .333 .222  .111 .000
  |||  |||   |||  |||
  |||  |||   |||  +++- Shade LUT index for color 0
  |||  |||   |||       (non-writable/always zero for palettes 4-7, 12-15)
  |||  |||   +++------ Shade LUT index for color 1
  |||  +++------------ Shade LUT index for color 2
  +++----------------- Shade LUT index for color 3
&lt;/pre&gt;

== LCD I/O ports ==

{{Anchor|LCD Control}}

=== LCD Control ($14) ===

&lt;pre&gt;
7  bit  0
---- ----
.... ..Ce
       ||
       |+- LCD enable: 0 = sleep, 1 = enabled
       +-- Contrast (WSC): 0 = low, 1 = high
&lt;/pre&gt;

The enable bit controls whether or not the LCD screen is displaying graphics. When it is cleared, the pixel area acts as if it was powered off, but the segment area continues functioning as normal.

The contrast bit allows enabling a "high contrast" mode: this works by having the LCD drive two lines with data received from the SoC - so the first line of the LCD is driven by the first line from the SoC, then additionally by the second line from the SoC.

TODO: Bits 4-7 are writable, but only on WS and WSC. Their effect is unknown.

{{Anchor|LCD Icon Control}}

=== LCD Icon Control ($15) ===

&lt;pre&gt;
7  bit  0
---- ----
..32 1hvs
  || ||||
  || |||+- Sleep (Star)
  || ||+-- Vertical orientation
  || |+--- Horizontal orientation
  || +---- Etc. 1 (Small circle)
  |+------ Etc. 2 (Medium circle)
  +------- Etc. 3 (Large circle)
&lt;/pre&gt;

== LCD internal I/O ports ==

These I/O ports are not used and most likely not intended for use by commercial games.

{{Anchor|LCD Final Line}}
=== LCD Final Line ($16) ===

The final line preceding line counter restart and the beginning of active display. By default, this is set to 158, which equals 159 total lines per frame.

It is said setting this register to an odd value on SwanCrystal has an adverse effect to the LCD panel,&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VTOTAL REG_LCD_VTOTAL - WSMan]&lt;/ref&gt; but the exact mechanism is unknown. A starting point for research is that an even value, or odd total line count, is needed to balance positive and negative charges on the LCD.&lt;ref&gt;W.A. Steer. "[http://www.techmind.org/lcd/ LCD monitor technology and tests]". Techmind, 2011-12-03. Accessed 2024-11-19.&lt;/ref&gt;

{{Anchor|LCD Back Porch Line}}

=== LCD Back Porch Line ($17, WSC only) ===

This port is available on the WonderSwan Color only - not the SwanCrystal!

The final line preceding the vertical back porch; by default, this should be set to 155.

The vertical back porch of the LCD is assumed to be 4 lines by some hardware, including IPS mods, as well as the official "TV Swan" capture device. Given that the first visible line is sent to the LCD on the display's line 1, this should be generally set to &lt;code&gt;LCD Final Line - 3&lt;/code&gt;.

Conversely, it is said moving this value closer to vertical blank improves LCD visibility&lt;ref&gt;[http://daifukkat.su/docs/wsman/#REG_LCD_VSYNC REG_LCD_VSYNC - WSMan]&lt;/ref&gt;, but the exact mechanism is unknown.

{{Anchor|LCD Line Counter}}
=== LCD Line Counter ($18) ===

This write-only port can be written to in order to change the next line to be drawn on the LCD.

For out of range values (higher than the final line), the LCD panel is not driven, but the line counter continues increasing until it rolls over to &lt;tt&gt;$00&lt;/tt&gt;.

{{Anchor|LCD Status}}
=== LCD Latched Icon Status ($1A read) ===

&lt;pre&gt;
7  bit  0
---- ----
..cv vvhl
  || ||||
  || |||+- LCD block disable: 0 = no, 1 = yes
  || ||+-- Headphone icon
  || ||
  || ||    Volume icons:
  || |+--- - Volume B (medium, high)
  || +---- - Volume A (low, high)
  |+------ - Speaker
  |
  +------- Cartridge icon
&lt;/pre&gt;

This port shows the state of latched LCD icons; these are displayed for an additional 128 ticks, counting from the last time they were enabled.

Bit 0 (LCD block disable) reflects the value written to the port.

TODO: This documents the WonderSwan Color. The specifics may work differently on the mono WonderSwan.

=== LCD Latched Icon Control ($1A write) ===

&lt;pre&gt;
7  bit  0
---- ----
..cs ...l
  ||    |
  ||    +- LCD block disable: 0 = no, 1 = yes
  ||       (disables LCD panel, including all segments)
  |+------ Latch sound segments
  +------- Latch cartridge segment
&lt;/pre&gt;

This port allows disabling the full LCD IP block; if bit 0 is set, all LCD panel control (including segments and sound/cartridge segment display timers) is disabled.

This port also allows manually latching the sound/cartridge segment display with their respective timers; however, this can only be done if bit 0 is set. For example, to latch the cartridge segment timer, one can write &lt;tt&gt;$21&lt;/tt&gt; to the port to disable the LCD block and latch the cartridge segment. Next, after re-enabling the LCD block by clearing bit 0, the cartridge segment will be shown for 128 vertical blanks.

=== TFT LCD Configuration ($70, $71, $72, $73, $74, $75, $76, $77 SwanCrystal only) ===

These eight bytes are read from internal EEPROM and configure unknown aspects of the console's TFT LCD panel.

They are only writable while the [[Boot ROM]] is unlocked - locking has the side effect of making them read-only.

== Notes ==
&lt;references /&gt;</text>
    <sha1>5d70fcbed1a864a3f3b52151094f652ce20a0626</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>WonderWitch/IL/ProcIL</title>
  <ns>0</ns>
  <id>82</id>
  <revision>
    <id>589</id>
    <timestamp>2025-04-11T18:24:36Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "ProcIL is a library used to manage processes on the system.  The Freya environment supports up to three concurrent processes at once, of which the first one is typically the operating system.  == Functions ==  === load ===  &lt;code&gt;void __far* load(const char far *cmdline);&lt;/code&gt;  Runs the load routine of the program specified on the command line, returning its entrypoint.  === run ===  &lt;code&gt;int run(void far *entrypoint, int argc, const char far * far *argv);&lt;/code&gt;  Run..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="923" xml:space="preserve">ProcIL is a library used to manage processes on the system.

The Freya environment supports up to three concurrent processes at once, of which the first one is typically the operating system.

== Functions ==

=== load ===

&lt;code&gt;void __far* load(const char far *cmdline);&lt;/code&gt;

Runs the load routine of the program specified on the command line, returning its entrypoint.

=== run ===

&lt;code&gt;int run(void far *entrypoint, int argc, const char far * far *argv);&lt;/code&gt;

Runs the passed entrypoint of the program.

=== exec ===

&lt;code&gt;int exec(const char far *cmdline, int argc, const char far * far *argv);&lt;/code&gt;

Combines &lt;tt&gt;load(...)&lt;/tt&gt; and &lt;tt&gt;run(...)&lt;/tt&gt;.

=== exit ===

&lt;code&gt;void exit(int code);&lt;/code&gt;

Exits the program, returning the specified code; finishes with a &lt;tt&gt;$10&lt;/tt&gt; interrupt call.

=== yield ===

&lt;code&gt;void yield(void);&lt;/code&gt;

=== suspend ===

TODO

=== resume ===

TODO

=== swap ===

TODO</text>
    <sha1>fa00fde68f0f265dcfd91782dce4620acbf193b0</sha1>
  </revision>
</page>
<page arvcontinue="20250301170301|551">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>599</id>
    <parentid>519</parentid>
    <timestamp>2025-04-23T14:03:59Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Reference */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2383" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header|ROM format]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
*** [[Display/Tile Data|Tile data]]
*** [[Display/Palette|Color palette]]
*** [[Display/Screens|Screen format]]
*** [[Display/Sprites|Sprite format]]
*** [[Display/Windows|Windows]]
*** [[Display/LCD Icons|LCD icons]]
*** [[Display/IO Ports|I/O ports]]
** [[Sound]]
*** [[DMA#Sound_DMA|Sound DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[EEPROM|Internal EEPROM]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>1d3f959f6c17340bd0182d09e720a5ac9aa91838</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>Internal EEPROM</title>
  <ns>0</ns>
  <id>83</id>
  <revision>
    <id>601</id>
    <timestamp>2025-04-23T18:38:22Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The internal EEPROM is 128 bytes on the mono model, and 2048 bytes on Color models. It is absent on the Pocket Challenge V2.  The first 96 bytes are used for software data, and can be written to even after the protection bit has been enabled. This is intended for transferring save data between cartridges.  == Contents ==  {| class="wikitable" |- ! Offset !! Length !! Contents |- | $00 || 96 || Program data. Can be written by programs even if write protection has been ena..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2832" xml:space="preserve">The internal EEPROM is 128 bytes on the mono model, and 2048 bytes on Color models. It is absent on the Pocket Challenge V2.

The first 96 bytes are used for software data, and can be written to even after the protection bit has been enabled. This is intended for transferring save data between cartridges.

== Contents ==

{| class="wikitable"
|-
! Offset !! Length !! Contents
|-
| $00 || 96 || Program data. Can be written by programs even if write protection has been enabled. 
|-
| $60 || 16 || Owner name, custom character set.
|-
| $70 || 1 || Owner birthday year, BCD, first/higher two digits
|-
| $71 || 1 || Owner birthday year, BCD, last/lower two digits
|-
| $72 || 1 || Owner birthday month, BCD
|-
| $73 || 1 || Owner birthday day, BCD
|-
| $74 || 1 || Owner gender:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - Male&lt;br/&gt;
2 - Female
|-
| $75 || 1 || Owner blood type:&lt;br/&gt;
0 - ?&lt;br/&gt;
1 - A&lt;br/&gt;
2 - B&lt;br/&gt;
3 - 0&lt;br/&gt;
4 - AB
|-
| $76 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID)
|-
| $77 || 1 || Last booted [[ROM header]] byte 7 (color)
|-
| $78 || 1 || Last booted [[ROM header]] byte 8 (game ID)
|-
| $7C || 1 || Stored cartridge ID/version change counter
|-
| $7D || 1 || Owner name change counter
|-
| $7E || 2 || System startup counter
|-
| $80 || 1 || Last booted [[ROM header]] byte 6 (developer/publisher ID) - only changed if byte 7 (color) != 0
|-
| $81 || 1 || Last booted [[ROM header]] byte 7 (color) - only changed if byte 7 (color) != 0
|-
| $82 || 1 || Last booted [[ROM header]] byte 8 (game ID) - only changed if byte 7 (color) != 0
|-
| $83 || 1 || Color model configuration
|-
| $84 || 1 || Name color
|-
| $85 || ? || [[Splash animation|Custom splash animation]], if present
|}

=== Owner name character set ===

{| class="wikitable"
|-
!
! &lt;code&gt;.0&lt;/code&gt;
! &lt;code&gt;.1&lt;/code&gt;
! &lt;code&gt;.2&lt;/code&gt;
! &lt;code&gt;.3&lt;/code&gt;
! &lt;code&gt;.4&lt;/code&gt;
! &lt;code&gt;.5&lt;/code&gt;
! &lt;code&gt;.6&lt;/code&gt;
! &lt;code&gt;.7&lt;/code&gt;
! &lt;code&gt;.8&lt;/code&gt;
! &lt;code&gt;.9&lt;/code&gt;
! &lt;code&gt;.A&lt;/code&gt;
! &lt;code&gt;.B&lt;/code&gt;
! &lt;code&gt;.C&lt;/code&gt;
! &lt;code&gt;.D&lt;/code&gt;
! &lt;code&gt;.E&lt;/code&gt;
! &lt;code&gt;.F&lt;/code&gt;
|-
! &lt;code&gt;0.&lt;/code&gt;
| || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || A || B || C || D || E
|-
! &lt;code&gt;1.&lt;/code&gt;
| F || G || H || I || J || K || L || M || N || O || P || Q || R || S || T || U
|-
! &lt;code&gt;2.&lt;/code&gt;
| V || W || X || Y || Z || ♥ || ♪ || + || - || ? || .
!
!
!
!
!
|}

=== Color model configuration ===

&lt;pre&gt;
7  bit  0
---- ----
sc.. ..vv
||     ||
||     ++- Volume level
|+-------- Contrast (WSC): 0 = Low, 1 = High
+--------- Custom splash animation enabled
&lt;/pre&gt;

=== Name colors ===

{| class="wikitable"
|-
! Value !! RGB code
|-
| 0 || #000
|-
| 1 || #f00
|-
| 2 || #f70
|-
| 3 || #ff0
|-
| 4 || #7f0
|-
| 5 || #0f0
|-
| 6 || #0f7
|-
| 7 || #0ff
|-
| 8 || #07f
|-
| 9 || #00f
|-
| 10 || #70f
|-
| 11 || #f0f
|-
| 12 || #f07
|-
| 13 || #fff
|}</text>
    <sha1>a154a3282b3c81e83f67358b34505ff40e8213eb</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>WSdev Wiki</title>
  <ns>0</ns>
  <id>1</id>
  <revision>
    <id>602</id>
    <parentid>599</parentid>
    <timestamp>2025-04-23T18:38:52Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Console components */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2407" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[ROM header|ROM format]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== Console components ===

* [[SoC]]
** [[Display]]
*** [[Display/Tile Data|Tile data]]
*** [[Display/Palette|Color palette]]
*** [[Display/Screens|Screen format]]
*** [[Display/Sprites|Sprite format]]
*** [[Display/Windows|Windows]]
*** [[Display/LCD Icons|LCD icons]]
*** [[Display/IO Ports|I/O ports]]
** [[Sound]]
*** [[DMA#Sound_DMA|Sound DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[Internal EEPROM]]
** [[EEPROM|EEPROM interface]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>c09fc7df46410423d0c7eeeb96460c473b177054</sha1>
  </revision>
  <revision>
    <id>605</id>
    <parentid>602</parentid>
    <timestamp>2025-04-23T18:51:33Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* General */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2444" xml:space="preserve">'''WonderSwan Development Wiki'''

== Reference ==

=== General ===

* [[Memory map]]
* [[I/O port map]]
* [[NEC V30MZ]] - the WonderSwan CPU (80186-compatible)
* [[Timing]]

=== File formats ===

* [[ROM header|ROM images]]
* [[WSR|WSR]]

=== Console components ===

* [[SoC]]
** [[Display]]
*** [[Display/Tile Data|Tile data]]
*** [[Display/Palette|Color palette]]
*** [[Display/Screens|Screen format]]
*** [[Display/Sprites|Sprite format]]
*** [[Display/Windows|Windows]]
*** [[Display/LCD Icons|LCD icons]]
*** [[Display/IO Ports|I/O ports]]
** [[Sound]]
*** [[DMA#Sound_DMA|Sound DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
*** [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
** [[Keypad]]
** [[Timers]]
** [[Interrupts]]
** [[UART]]
** [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
* [[Boot ROM]]
* [[Internal EEPROM]]
** [[EEPROM|EEPROM interface]]
** [[Splash animation]]&lt;sup&gt;(color)&lt;/sup&gt;

=== Cartridge components ===

* [[Cartridge connector]]
* [[Mapper]]
** [[Bandai 2001]]
** [[Bandai 2003]]
** [[KARNAK]]
* Mapper-specific components
** [[EEPROM]] (2001)
** [[Real-Time Clock]] (2003)
* Cartridge-specific components
** [[WonderWitch/Flash|WonderWitch NOR flash]]
** [[Handy Sonar]]
** [[mama Mitte]] (IR transceiver)
** [[Robot Works]] (IR transmitter)

=== Pinouts ===

* [[Cartridge connector#Pinout|Cartridge pinout]]
* [[Accessory port pinout]]
* [[2001 Mapper pinout]]
* [[2003 Mapper pinout]]
* [[KARNAK pinout]]
* [[GIZA pinout]]
* [[S-3511A pinout]]

=== Accessories ===

* [[WonderBeat 9480]] headphone adapter
* [[WonderBorg]] robot
* [[WonderGate]] mobile adapter
* [[WonderWave]] infrared adapter

=== WonderWitch ===

* [[WonderWitch]]
** [[WonderWitch/Flash|NOR flash]]
** [[WonderWitch/Memory map|Memory map]]
** [[WonderWitch/FreyaBIOS|FreyaBIOS]]
** [[WonderWitch/FreyaOS|FreyaOS]]
** [[WonderWitch/Filesystem|File system]]
** [[WonderWitch/Process|Process]]
** [[WonderWitch/IL|Indirect Library (IL)]]
** [[WonderWitch .fx files|.fx file format]]

== Links ==

* [https://wonderful.asie.pl/wiki/doku.php?id=wswan:index#guides Wonderful Toolchain Wiki] - gcc-ia16-based homebrew toolchain guides and documentation
* [https://github.com/WonderfulToolchain/awesome-wsdev awesome-wsdev] - curated documentation/tools/source code link list

== MediaWiki ==

* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]</text>
    <sha1>c23ff6cc211c432f1a9ec162eb0d4f0f527f9ef2</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>EEPROM</title>
  <ns>0</ns>
  <id>35</id>
  <revision>
    <id>603</id>
    <parentid>575</parentid>
    <timestamp>2025-04-23T18:42:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="8843" xml:space="preserve">The WonderSwan utilizes M93LCx6-compatible EEPROMs:

* in the SoC:
** 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
** 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
* on cartridges:
** 1 Kbit cartridge EEPROM (M93LC46-compatible)
** 8 Kbit cartridge EEPROM (M93LC76-compatible)
** 16 Kbit cartridge EEPROM (M93LC86-compatible)

Additional variants exists which were not seen on any production cartridge:

* 256 bit EEPROM (M93LC06-compatible)
* 2 Kbit EEPROM (M93LC56-compatible)
* 4 Kbit EEPROM (M93LC66-compatible)

== Commands ==

=== READ - Read Word ===

The READ command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and returns the word at that address.

=== WRITE - Write Word ===

The WRITE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and the word to write to it, then writes the word.

=== ERASE - Erase Word ===

The ERASE command takes an address of a word (address 0 =&gt; bytes 0, 1; address 1 =&gt; bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.

=== WDS - Write Disable ===

The WDS command prevents issued write and erase commands from having an effect on the EEPROM.

=== WRAL - Write All ===

The WRAL command erases the word at all address of the EEPROM, setting them to 0xFFFF.

This command is not guaranteed to be present on all EEPROMs.

=== ERAL - Erase All ===

The WRAL command takes a word and writes it to all addresses of the EEPROM.

This command is not guaranteed to be present on all EEPROMs.

=== WEN - Write Enable ===

The WEN command restores the effect of issued write and erase commands on the EEPROM disabled using WDS.

== I/O ports ==

The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the [[Bandai 2001|mapper documentation]].

It is recommended to only access the data and command ports with aligned word reads/writes; see the ''Errata'' section for more information.

{{Anchor|Internal EEPROM Data}}
=== Internal EEPROM Data ($BA, $BB read) ===

{{Anchor|Cartridge EEPROM Data}}

=== Cartridge EEPROM Data ($C4, $C5 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data read from the EEPROM.
&lt;/pre&gt;

The read buffer's value changes only once the Read command is completed.

=== Internal EEPROM Data ($BA, $BB write) ===

=== Cartridge EEPROM Data ($C4, $C5 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 dddd dddd  dddd dddd
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Data to write to the EEPROM.
&lt;/pre&gt;

The write buffer is latched when a Write command is initiated; further writes to it do not affect the value written by that specific command.

The two EEPROM data buffers are not shared; neither writes to the write buffer nor the execution of non-read commands affect the contents of the read buffer.

{{Anchor|Internal EEPROM Command}}

=== Internal EEPROM Command ($BC, $BD) ===

{{Anchor|Cartridge EEPROM Command}}

=== Cartridge EEPROM Command ($C6, $C7) ===

&lt;pre&gt;
  Command Pattern 1

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  ooaa aaaa  (¼, 1 Kbit - M93LC06/46)
 0000 01oo  aaaa aaaa  (2, 4 Kbit - M93LC56/66)
 0001 ooaa  aaaa aaaa (8, 16 Kbit - M93LC76/86)
      ||||  |||| ||||
      ||++--++++-++++- Address (MSb .. LSb)
      ++-------------- Opcode:
                         01 - WRITE
                         10 - READ
                         11 - ERASE
&lt;/pre&gt;

&lt;pre&gt;
  Command Pattern 2

15  bit  8  7  bit  0 
 ---- ----  ---- ----
 0000 0001  00ss ....  (¼, 1 Kbit - M93LC06/46)
 0000 0100  ss.. ....  (2, 4 Kbit - M93LC56/66)
 0001 00ss  .... .... (8, 16 Kbit - M93LC76/86)
      ||||
      ||++------------ Sub-Opcode:
      ||                 00 - WDS
      ||                 01 - WRAL
      ||                 10 - ERAL
      ||                 11 - WEN
      ++-------------- Opcode:
                         00
&lt;/pre&gt;

The value written to this port can be read back; it is not affected by ''EEPROM Control''.

{{Anchor|Internal EEPROM Control}}

=== Internal EEPROM Control ($BE, $BF write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  PSWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Protection: 1 to enable internal EEPROM write protection.
                                   Cannot be cleared once set. 
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.
* Protection: Enables internal EEPROM write protection (addresses &gt;= 0x30, or anything after the first 96 bytes, can no longer be written to).

If more than one of the Read, Write, Short, Protect bits are set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM). Notably, this means that writing, for example, 0x90 does not protect the internal EEPROM if it wasn't already protected, but writing 0x80 does.

The command requested here should match the command sent to the EEPROM in port ''$BC''.

{{Anchor|Cartridge EEPROM Control}}

=== Cartridge EEPROM Control ($C8, $C9 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  ASWR ....
            ||||
            |||+------ Read operation:  1 for READ command, 0 otherwise
            ||+------- Write operation: 1 for WRITE and WRAL command, 0 otherwise
            |+-------- Short operation: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
            +--------- Abort operation
&lt;/pre&gt;

* Read operation: Sends 16 bits from Command, then reads 16 bits to Data.
* Write operation: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
* Short operation: Sends 16 bits from Command, de-asserts Microwire chip select.

If more than one of the Read, Write, Short bits are set, or if the Abort bit is set, the operation is treated as invalid (all four operation bits are cleared and no communication is done with the EEPROM).

{{Anchor|Internal EEPROM Status}}

=== Internal EEPROM Status ($BE, $BF read) ===

{{Anchor|Cartridge EEPROM Status}}

=== Cartridge EEPROM Status ($C8, $C9 read) ===

&lt;pre&gt;
15  bit  8  7  bit  0 
 ---- ----  ---- ----
 .... ....  P... ..rd
            |      ||
            |      |+- 0 after a Read command is initiated,
            |      |   1 once a Read command is completed.
            |      |   Unaffected by Write/Erase commands.
            |      +-- 0 if the EEPROM is busy,
            |          1 if a command can be accepted (idle).
            +--------- Internal EEPROM write protection:
                       0 = disabled, 1 = enabled
&lt;/pre&gt;

== Hardware notes ==

EEPROM command bits are shifted out starting from the ''most'' significant bit of the port.

&lt;pre&gt;
    +----&gt; EEPROM Serial Data
    |
   [0] &lt;= [0000 0001 ooaa aaaa]
           EEPROM Command Port
&lt;/pre&gt;

While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.

The SPHINX SoC family emulates a 93C46 in ASWAN compatibility mode by manipulating the shifted out command value when sending it to the EEPROM (TODO: How exactly?).

== Errata ==

=== Cartridge: Buggy Done bit ===

On the cartridge implementation in the 2001 mapper, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started.)

=== Internal: Non-word access on ASWAN ===

On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.

It is recommended to only use aligned word port accesses to talk to the internal EEPROM.

This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode. It is also not present on the cartridge impelmentation in the 2001 mapper.

== Links ==

* [https://www.st.com/resource/en/datasheet/m93c46-w.pdf STMicroelectronics M93LCx6 datasheet]</text>
    <sha1>ca62018f72b26d6efe11a190e9f973b037782a52</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>Bandai 2001</title>
  <ns>0</ns>
  <id>12</id>
  <revision>
    <id>604</id>
    <parentid>571</parentid>
    <timestamp>2025-04-23T18:44:07Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1315" xml:space="preserve">The Bandai 2001 (LUXSOR) is one of the two mappers used in WonderSwan cartridges.

In addition to the normal [[Mapper]] banking interface, the 2001 adds three registers for interacting with a Microwire [[EEPROM]] which may optionally be present on the cartridge board:

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="5" | External EEPROM
! rowspan="2" | $C4
| rowspan="2" | [[EEPROM#Cartridge EEPROM Data|External EEPROM Data]]
| rowspan="2" style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| R16
| Data read (d)
|-
| W16
| Data to write (d)
|-
! $C6
| [[EEPROM#Cartridge EEPROM Command|External EEPROM Command]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;0001 CCaa aaaa aaaa&lt;/tt&gt;&lt;br/&gt;or &lt;tt style="white-space: nowrap"&gt;0000 01CC aaaa aaaa&lt;/tt&gt;&lt;br/&gt; or &lt;tt style="white-space: nowrap"&gt;0000 0001 CCaa aaaa&lt;/tt&gt;
| RW16
| Command and address
|-
! rowspan=2|$C8
| [[EEPROM#Cartridge EEPROM Control|External EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ASWR ....&lt;/tt&gt;
| W8
| Abort (A), Short (S), Write (W), Read (R)
|-
| [[EEPROM#Cartridge EEPROM Status|External EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..rd&lt;/tt&gt;
| R8
| Ready (r), Done (d)
|-
|}</text>
    <sha1>1c48f389f97ae1e82f6ea47b0ee18a4b0a11400f</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>ROM header</title>
  <ns>0</ns>
  <id>5</id>
  <revision>
    <id>606</id>
    <parentid>600</parentid>
    <timestamp>2025-04-23T18:52:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5894" xml:space="preserve">The file extensions used to mark WS cartridge files are typically:

* ''.ws'' - "mono" WonderSwan,
* ''.wsc'' - WonderSwan Color,
* ''.pc2'' - Pocket Challenge V2.

== ROM header ==

Every WonderSwan cartridge ROM contains a header.

The header is stored at the end (the final sixteen bytes) of the ROM image. For this reason, it is also sometimes called a "footer".

A notable consequence of this is that, unlike most other platforms, non-power-of-two ROM images are expected to be padded to the last bank downwards, rather than the first bank upwards; for example, a 768 KiB ROM image will be padded to 1 MiB by appending 256 KiB of padding data to the ''beginning'', rather than the ''end'' of the ROM.

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? SB?v
     || |
     || +- Starting orientation: 0 = horizontal, 1 = vertical
     |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
     +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 2 and 3 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

Bit 0 controls the splash screen's orientation, as well as the LCD segment (horizontal or vertical orientation) displayed during the first 128 ticks of the splash screen.

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>dac0f384a2e4398bd89b202296b972614de82923</sha1>
  </revision>
  <revision>
    <id>607</id>
    <parentid>606</parentid>
    <timestamp>2025-04-23T18:52:40Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="5909" xml:space="preserve">The file extensions used to mark WS cartridge files are typically:

* &lt;tt&gt;.ws&lt;/tt&gt; - "mono" WonderSwan,
* &lt;tt&gt;.wsc&lt;/tt&gt; - WonderSwan Color,
* &lt;tt&gt;.pc2&lt;/tt&gt; - Pocket Challenge V2.

== ROM header ==

Every WonderSwan cartridge ROM contains a header.

The header is stored at the end (the final sixteen bytes) of the ROM image. For this reason, it is also sometimes called a "footer".

A notable consequence of this is that, unlike most other platforms, non-power-of-two ROM images are expected to be padded to the last bank downwards, rather than the first bank upwards; for example, a 768 KiB ROM image will be padded to 1 MiB by appending 256 KiB of padding data to the ''beginning'', rather than the ''end'' of the ROM.

Parts of this header are validated or otherwise used by the console's [[boot ROM]] - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| $D || 1 || Mapper
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? SB?v
     || |
     || +- Starting orientation: 0 = horizontal, 1 = vertical
     |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
     +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 2 and 3 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

Bit 0 controls the splash screen's orientation, as well as the LCD segment (horizontal or vertical orientation) displayed during the first 128 ticks of the splash screen.

=== Mapper ($D) ===
----
{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>1a64a91ef75b58d5cf8ae838e960260e71585760</sha1>
  </revision>
  <revision>
    <id>610</id>
    <parentid>607</parentid>
    <timestamp>2025-04-26T16:09:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="6094" xml:space="preserve">The file extensions used to mark WS cartridge files are typically:

* &lt;tt&gt;.ws&lt;/tt&gt; - "mono" WonderSwan,
* &lt;tt&gt;.wsc&lt;/tt&gt; - WonderSwan Color,
* &lt;tt&gt;.pc2&lt;/tt&gt; - Pocket Challenge V2.

== ROM header ==

Every WonderSwan cartridge ROM contains a header.

The header is stored at the end (the final sixteen bytes) of the ROM image. For this reason, it is also sometimes called a "footer".

A notable consequence of this is that, unlike most other platforms, non-power-of-two ROM images are expected to be padded to the last bank downwards, rather than the first bank upwards; for example, a 768 KiB ROM image will be padded to 1 MiB by appending 256 KiB of padding data to the ''beginning'', rather than the ''end'' of the ROM.

Parts of this header are validated or otherwise used by the [[boot ROM]] on Color models - they are marked in '''bold'''.

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment.
|-
| '''$5''' || '''1''' || '''Maintenance'''
|-
| $6 || 1 || Developer/Publisher ID
|-
| $7 || 1 || Color
|-
| $8 || 1 || Game ID (binary-coded decimal)
|-
| '''$9''' || '''1''' || '''Game version? / Safe mode'''
|-
| $A || 1 || ROM size
|-
| $B || 1 || Save type/size
|-
| '''$C''' || '''1''' || '''Flags'''
|-
| '''$D''' || '''1''' || '''Mapper'''
|-
| $E || 2 || Checksum (sum of all ROM bytes excluding the checksum)
|}

=== Maintenance ($5) ===
----
&lt;pre&gt;
7  bit  0
---- ----
s... 0000
|    ||||
|    ++++- Must be zero; otherwise the console will prohibit execution.
|          Purpose unknown.
+--------- (Color) Splash bypass: 0 = Disable, 1 = Enable.
           Bypasses the custom boot splash stored in the console's
           internal EEPROM; presumably used for bricked console recovery.
&lt;/pre&gt;

=== Developer/Publisher ID ($6) ===
----
{| class="wikitable"
|+ Known official developer/publisher IDs
|-
! ID !! Publisher code !! Publisher
|-
| $01 || BAN || Bandai
|-
| $02 || TAT || Taito
|-
| $03 || TMY || Tomy
|-
| $04 || KEX || Koei
|-
| $05 || DTE || Data East
|-
| $06 || AAE || Asmik Ace
|-
| $07 || MDE || Media Entertainment
|-
| $08 || NHB || Nichibutsu
|-
| $0A || CCJ || Coconuts Japan
|-
| $0B || SUM || Sammy
|-
| $0C || SUN || Sunsoft
|-
| $0D || PAW || Mebius
|-
| $0E || BPR || Banpresto
|-
| $10 || JLC || Jaleco
|-
| $11 || MGA || Imagineer
|-
| $12 || KNM || Konami
|-
| $16 || KBS || Kobunsha
|-
| $17 || BTM || Bottom Up
|-
| $18 || KGT || Kaga Tech
|-
| $19 || SRV || Sunrise
|-
| $1A || CFT || Cyber Front
|-
| $1B || MGH || Megahouse
|-
| $1D || BEC || Interbec
|-
| $1E || NAP || Nihon Application
|-
| $1F || BVL || Bandai Visual
|-
| $20 || ATN || Athena
|-
| $21 || KDX || KID
|-
| $22 || HAL || HAL Corporation
|-
| $23 || YKE || Yuki Enterprise
|-
| $24 || OMN || Omega Micott
|-
| $25 || LAY || Layup
|-
| $26 || KDK || Kadokawa Shoten
|-
| $27 || SHL || Shall Luck
|-
| $28 || SQR || Squaresoft
|-
| $2A || SCC || ? (SUNCORPORATION?)
|-
| $2B || TMC || Tom Create
|-
| $2D || NMC || Namco
|-
| $2E || SES || Soeishinsha
|-
| $2F || HTR || Hearty Robin
|-
| $31 || VGD || Vanguard
|-
| $32 || MGT || Megatron
|-
| $33 || WIZ || Wiz
|-
| $35 || TAN || Tanita
|-
| $36 || CPC || Capcom
|}

Note that IDs $00 and $01 are used across a variety of commercial games. Homebrew is known to use arbitrary values in this field.

=== Color ($7) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? ???c
        |
        +- 0 = Monochrome only, 1 = Supports Color mode.
&lt;/pre&gt;

=== Game version? / Safe mode ($9) ===
----
&lt;pre&gt;
7  bit  0
---- ----
pvvv vvvv
|||| ||||
|+++ ++++- Game version?
+--------- Internal EEPROM write protect: 0 = Enable, 1 = Disable.
           This prohibits writing to the internal EEPROM for addresses
           0x60 and above (user settings, custom splash screen).
           Games are expected to enable write protection; however, the
           WonderWitch is factory configured with it disabled.
&lt;/pre&gt;

=== ROM size ($A) ===
----
Unofficial/inferred ROM size values are marked in ''italic''.

{| class="wikitable"
|+ ROM size values
|-
! ID !! Size
|-
| ''$00'' || ''1 Mbit (128 KiB)''
|-
| ''$01'' || ''2 Mbit (256 KiB)''
|-
| $02 || 4 Mbit (512 KiB)
|-
| $03 || 8 Mbit (1 MiB)
|-
| $04 || 16 Mbit (2 MiB)
|-
| ''$05'' || ''24 Mbit (3 MiB)''
|-
| $06 || 32 Mbit (4 MiB)
|-
| ''$07'' || ''48 Mbit (6 MiB)''
|-
| $08 || 64 Mbit (8 MiB)
|-
| $09 || 128 Mbit (16 MiB)
|-
| ''$0A'' || ''256 Mbit (32 MiB)''
|-
| ''$0B'' || ''512 Mbit (64 MiB)''
|}

Note that ROM sizes over 16 MiB are not supported by the [[Bandai 2001]] mapper. The [[Bandai 2003]] mapper is limited to 64 MiB.

=== Save type/size ($B) ===
----
{| class="wikitable"
|+ Save type values
|-
! ID !! Type !! Size
|-
| $00 || colspan="2" style="text-align:center;" | None 
|-
| $01 || rowspan="5" | SRAM || rowspan="2" | 256 Kbit (32 KiB)
|-
| $02
|-
| $03 || 1 Mbit (128 KiB)
|-
| $04 || 2 Mbit (256 KiB)
|-
| $05 || 4 Mbit (512 KiB)
|-
| $10 || rowspan="3" | EEPROM || 1 Kbit (128 B)
|-
| $20 || 16 Kbit (2 KiB)
|-
| $50 || 8 Kbit (1 KiB)
|}

Note that while ID &lt;code&gt;$01&lt;/code&gt; is commonly documented as &lt;code&gt;64 Kbit&lt;/code&gt;, all known cartridges using that value come with &lt;code&gt;256 Kbit&lt;/code&gt; SRAM chips. This requires further investigation.

=== Flags ($C) ===
----
&lt;pre&gt;
7  bit  0
---- ----
???? SB?v
     || |
     || +- Starting orientation: 0 = horizontal, 1 = vertical
     |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit
     +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1
&lt;/pre&gt;

Flag bits 2 and 3 correspond to [[SoC#System Control|System Control]] bits 2 and 3.

Bit 0 controls the splash screen's orientation, as well as the LCD segment (horizontal or vertical orientation) displayed during the first 128 ticks of the splash screen.

=== Mapper ($D) ===
----
&lt;pre&gt;
7  bit  0
---- ----
0000 mmmm
|||| ||||
|||| ++++- Mapper type; see below.
++++------ Must be zero; otherwise the console will prohibit execution.
&lt;/pre&gt;

{| class="wikitable"
|+ Known mapper types
|-
! ID !! Mapper
|-
| $00 || [[Bandai 2001]] or [[KARNAK]]
|-
| $01 || [[Bandai 2003]]
|}</text>
    <sha1>58314ca6a4fd8dd5fdcc9f225da64b66a0dd6fad</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>WSR</title>
  <ns>0</ns>
  <id>84</id>
  <revision>
    <id>608</id>
    <timestamp>2025-04-23T18:56:57Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>Created page with "The WSR file format is used for storing music routines from WonderSwan software, not unlike the NSF format. It was initally defined and implemented by the &lt;tt&gt;in_wsr&lt;/tt&gt; Winamp plugin.  Its format is based on the [[ROM header]] format, with files expected to be a multiple of 64 KiB in size. However, the footer at the end of the file is 32 bytes long, not 16:  {| class="wikitable" |+ Header contents |- ! Offset !! Length !! Contents |- | $00 || 4 || Magic string: &lt;tt&gt;WSR..."</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="762" xml:space="preserve">The WSR file format is used for storing music routines from WonderSwan software, not unlike the NSF format. It was initally defined and implemented by the &lt;tt&gt;in_wsr&lt;/tt&gt; Winamp plugin.

Its format is based on the [[ROM header]] format, with files expected to be a multiple of 64 KiB in size. However, the footer at the end of the file is 32 bytes long, not 16:

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-
| $00 || 4 || Magic string: &lt;tt&gt;WSRF&lt;/tt&gt;
|-
| $04 || 1 || Version number; currently &lt;tt&gt;$00&lt;/tt&gt;
|-
| $05 || 1 || Starting song number
|-
| $06 || 10 || Reserved
|-
| $10 || 16 || [[ROM header]]
|}

The &lt;tt&gt;JMP&lt;/tt&gt; instruction in the ROM header points to the song playback routine; &lt;tt&gt;AX&lt;/tt&gt; is set to the song number.</text>
    <sha1>1b412673debb207a58cee9530b5f6aeacb59465a</sha1>
  </revision>
  <revision>
    <id>609</id>
    <parentid>608</parentid>
    <timestamp>2025-04-23T18:57:45Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="921" xml:space="preserve">The WSR file format is used for storing music routines from WonderSwan software, not unlike the NSF format. It was initally defined and implemented by the &lt;tt&gt;in_wsr&lt;/tt&gt; Winamp plugin.

Its format is based on the [[ROM header]] format, with files expected to be a multiple of 64 KiB in size. However, the footer at the end of the file is 32 bytes long, not 16:

{| class="wikitable"
|+ Header contents
|-
! Offset !! Length !! Contents
|-Q
| $00 || 4 || Magic string: &lt;tt&gt;WSRF&lt;/tt&gt;
|-
| $04 || 1 || Version number; currently &lt;tt&gt;$00&lt;/tt&gt;
|-
| $05 || 1 || Starting song number
|-
| $06 || 10 || Reserved
|-
| $10 || 16 || [[ROM header]]
|}

The &lt;tt&gt;JMP&lt;/tt&gt; instruction in the ROM header points to the song playback routine; &lt;tt&gt;AX&lt;/tt&gt; is set to the song number.

== References ==

* [https://github.com/WonderfulToolchain/awesome-wsdev/blob/main/archive/in_wsr.txt in_wsr.txt] - the original specification
&lt;references/&gt;</text>
    <sha1>5959647a12399e9cf9c6c5b3e7c923cdecf017d1</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>Boot ROM</title>
  <ns>0</ns>
  <id>81</id>
  <revision>
    <id>611</id>
    <parentid>520</parentid>
    <timestamp>2025-04-26T17:01:42Z</timestamp>
    <contributor>
      <username>Lidnariq</username>
      <id>7</id>
    </contributor>
    <comment>only color model validates the footer</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="686" xml:space="preserve">The WonderSwan boot ROM is where the console begins execution on power on.

* On the "mono" model, it occupies an area from &lt;tt&gt;$FF000&lt;/tt&gt; to &lt;tt&gt;$FFFFF&lt;/tt&gt;, for a total of 4 KiB.
* On the Color model, it occupies an area from &lt;tt&gt;$FE000&lt;/tt&gt; to &lt;tt&gt;$FFFFF&lt;/tt&gt;, for a total of 8 KiB.

It performs the following activities:

* checks if the cartridge self-test passed;
* If the color model, checks if the cartridge footer is valid;
* if START is held when the console is turned on, enters the boot ROM menu;
* updates telemetry/diagnostics information in the internal EEPROM;
* displays the splash screen (optionally, a custom splash screen on Color models);
* jumps to the cartridge.</text>
    <sha1>5bcf659214acd96cdb5eae9d07d309e71be6a10c</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>I/O port map</title>
  <ns>0</ns>
  <id>8</id>
  <revision>
    <id>612</id>
    <parentid>597</parentid>
    <timestamp>2025-05-04T08:46:48Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22648" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i.sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.mmc ???? errr ffss&lt;/tt&gt;
| RW16
| Mode (m), Channel reset (c), Enable (e),
Rate (r), Format (f), Shift (s)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cc5? ??sh&lt;/tt&gt;
| RW8
| 
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! [[SoC]]
! $A3
| [[SoC#System Test|System Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... u?vh&lt;/tt&gt;
| RW8
| UART test (u), VBlank Timer test (v), HBlank Timer test (h)
|-
! rowspan="4" | [[Timers]]
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[SoC]]
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>666b0e36fe29ef4049a489332cded28246595ff8</sha1>
  </revision>
  <revision>
    <id>614</id>
    <parentid>612</parentid>
    <timestamp>2025-05-04T08:50:00Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* I/O port map */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="22650" xml:space="preserve">The WonderSwan SoC has three general blocks of I/O port accesses:

{| class="wikitable"
! From !! To !! Holder !! Width !! Speed
|-
| $00 || $B7 || WonderSwan SoC || 16-bit || 1 cycle
|-
| $B8 || $BF || Internal EEPROM control || 16-bit || 1 cycle
|-
| $C0 || $FF || Cartridge bus || 8-bit || 1&lt;sup&gt;(color)&lt;/sup&gt;/2 cycles (configurable)
|}

With the exception of internal EEPROM on the ASWAN, all unaligned 16-bit accesses can be converted to two 8-bit accesses with a 1-cycle penalty.

== I/O port map ==

* Superscripts are used to mark ports specific to a given mode or platform:
** Color mode: &lt;sup&gt;(color)&lt;/sup&gt;. Such ports are only accessible when color mode is enabled through port &lt;code&gt;$60&lt;/code&gt;.
** WS/WSC/SC console: &lt;sup&gt;(WS)&lt;/sup&gt;, &lt;sup&gt;(WSC)&lt;/sup&gt;, &lt;sup&gt;(SC)&lt;/sup&gt;.
* If two Bits rows are provided, the second one refers to the "Color" mode.
* The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word).

{| class="wikitable"
! Category
! Port
! Description
! Bits
! Type
! Notes
|-
! rowspan="47" | [[Display]] 
! $00
| [[Display/IO Ports#Display Control|Display Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..wo Ws21&lt;/tt&gt;
| RW8
| 
|-
! $01
| [[Display/IO Ports#Display Background|Display Background]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;pppp iiii&lt;/tt&gt;
| RW8
| Shade (s)
Palette (p), Index (i)
|-
! $02
| [[Display/IO Ports#Current Line|Display Current Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| R8
| Line (l)
|-
! $03
| [[Display/IO Ports#Interrupt Line|Display Interrupt Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $04
| [[Display/IO Ports#Sprite Table Address|Sprite Table Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...a aaaa&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;..aa aaaa&lt;/tt&gt;
| RW8
| Address &gt;&gt; 9 (a)
|-
! $05
| [[Display/IO Ports#Sprite Table First|Sprite Table First]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii iiii&lt;/tt&gt;
| RW8
| Index (i)
|-
! $06
| [[Display/IO Ports#Sprite Table Count|Sprite Table Count]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cccc cccc&lt;/tt&gt;
| RW8
| Count (c)
|-
! $07
| [[Display/IO Ports#Screen Address|Screen Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.222 .111&lt;/tt&gt;
&lt;tt style="white-space: nowrap"&gt;2222 1111&lt;/tt&gt;
| RW8
| Screen 1 address &gt;&gt; 11 (1)
Screen 2 address &gt;&gt; 11 (2)
|-
! $08
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $09
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0A
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0B
| [[Display/IO Ports#Screen 2 Window|Screen 2 Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0C
| [[Display/IO Ports#Sprite Window|Sprite Window Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0D
| [[Display/IO Ports#Sprite Window|Sprite Window Top]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $0E
| [[Display/IO Ports#Sprite Window|Sprite Window Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $0F
| [[Display/IO Ports#Sprite Window|Sprite Window Bottom]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $10
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $11
| [[Display/IO Ports#Screen Scroll|Screen 1 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $12
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll X]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;xxxx xxxx&lt;/tt&gt;
| RW8
| Coordinate (x)
|-
! $13
| [[Display/IO Ports#Screen Scroll|Screen 2 Scroll Y]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;yyyy yyyy&lt;/tt&gt;
| RW8
| Coordinate (y)
|-
! $14
| [[Display/IO Ports#LCD Control|LCD Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..Ce&lt;/tt&gt;
| RW8
| Contrast (C)&lt;sup&gt;(WSC)&lt;/sup&gt;, Enable (e)
|-
! $15
| [[Display/IO Ports#LCD Icon Control|LCD Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..32 1hvs&lt;/tt&gt;
| RW8
| Etc. 3 (3), Etc. 2 (2), Etc. 1 (1),
Horizontal (h), Vertical (v), Sleep (s)
|-
! $16
| [[Display/IO Ports#LCD Final Line|LCD Final Line]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $17
| [[Display/IO Ports#LCD Back Porch Line|LCD Back Porch Line]]&lt;sup&gt;(WSC)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| RW8
| Line (l)
|-
! $18
| [[Display/IO Ports#LCD Line Counter|LCD Line Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll&lt;/tt&gt;
| W8
| Line (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| R8
| Cartridge icon (c), Volume icons (v),
Headphone icon (h), Latch override (l)
|-
! $1A
| [[Display/IO Ports#LCD Status|LCD Latched Icon Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;..cv vvhs&lt;/tt&gt;
| W8
| Cartridge (c), Sound (s), Latch override (l)
|-
! $1C
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 0/1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;1111 0000&lt;/tt&gt;
| RW8
| Shade index
|-
! $1D
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 2/3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;3333 2222&lt;/tt&gt;
| RW8
| Shade index
|-
! $1E
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 4/5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;5555 4444&lt;/tt&gt;
| RW8
| Shade index
|-
! $1F
| [[Display/IO Ports#LCD Mono Shade LUT|LCD Mono Shade LUT 6/7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;7777 6666&lt;/tt&gt;
| RW8
| Shade index
|-
! $20
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 0]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $22
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 1]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $24
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $26
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $28
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 4]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 5]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 6]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $2E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 7]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $30
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 8]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $32
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 9]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $34
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 10]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $36
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 11]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 .000&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $38
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 12]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3A
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 13]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3C
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 14]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! $3E
| [[Display/IO Ports#LCD Mono Palette|LCD Mono Palette 15]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.333 .222 .111 ....&lt;/tt&gt;
| RW16
| Shade LUT index
|-
! rowspan="10" | [[DMA]]&lt;sup&gt;(color)&lt;/sup&gt;
! $40
| [[DMA#General DMA|GDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll lll.&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $42
| [[DMA#General DMA|GDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $44
| [[DMA#General DMA|GDMA Destination Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;aaaa aaaa aaaa aaa.&lt;/tt&gt;
| RW16
| IRAM address (a)
|-
! $46
| [[DMA#General DMA|GDMA Length]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;bbbb bbbb bbbb bbb.&lt;/tt&gt;
| RW16
| Bytes (b)
|-
! $48
| [[DMA#General DMA|GDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.. ....&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d)
|-
! $4A
| [[DMA#Sound DMA|SDMA Source Address Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Linear address, low 16 bits (l)
|-
! $4C
| [[DMA#Sound DMA|SDMA Source Address High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Linear address, high 4 bits (h)
|-
! $4E
| [[DMA#Sound DMA|SDMA Length Low]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll llll llll llll&lt;/tt&gt;
| RW16
| Length, low 16 bits (l)
|-
! $50
| [[DMA#Sound DMA|SDMA Length High]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... hhhh&lt;/tt&gt;
| RW8
| Length, high 4 bits (h)
|-
! $52
| [[DMA#Sound DMA|SDMA Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ed.t rhff&lt;/tt&gt;
| RW8
| Enable (e), Decrement (d), Target (t),
Repeat (r), Hold (h), Frequency (f)
|-
! rowspan="2" | [[SoC]]&lt;sup&gt;(color)&lt;/sup&gt;
! $60
| [[SoC#System Control 2|System Control 2]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;c4C. i.sl&lt;/tt&gt;
| RW8
| Color (c), 4BPP (4), Chunky (C),&lt;br/&gt;
Cart I/O wait state (i), SRAM wait state (s),&lt;br/&gt;
Cart clock speed (l).
|-
! $62
| [[SoC#System Control 3|System Control 3]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;S... ...p&lt;/tt&gt;
| RW8
| SwanCrystal (S), Power off (p)
|-
! rowspan="4" | [[Hyper Voice]]&lt;sup&gt;(color)&lt;/sup&gt;
! $64
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Left Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $66
| [[Hyper Voice#Hyper Voice Output|Hyper Voice Right Output]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss ssss ssss&lt;/tt&gt;
| W16
| Raw sample (s)
|-
! $69
| [[Hyper Voice#Hyper Voice Input|Hyper Voice Right Input]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| W8
| Sample (s)
|-
! $6A
| [[Hyper Voice#Hyper Voice Control|Hyper Voice Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.ttc ???? errr ssvv&lt;/tt&gt;
| RW16
| Target (t), Channel reset (c), Enable (e),
Rate (r), Sample (s), Shift (v)
|-
! rowspan="8" | [[Display]]&lt;sup&gt;(SC)&lt;/sup&gt;
! $70
| LCD Timing Configuration 1?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $71
| LCD Timing Configuration 2?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $72
| LCD Timing Configuration 3?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $73
| LCD Timing Configuration 4?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $74
| LCD Timing Configuration 5?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $75
| LCD Timing Configuration 6?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $76
| LCD Timing Configuration 7?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! $77
| LCD Timing Configuration 8?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;???? ????&lt;/tt&gt;
| RL8
|
|-
! rowspan="22" | [[Sound]]
! $80
| [[Sound#Sound Channel Frequency|Sound Channel 1 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $82
| [[Sound#Sound Channel Frequency|Sound Channel 2 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $84
| [[Sound#Sound Channel Frequency|Sound Channel 3 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $86
| [[Sound#Sound Channel Frequency|Sound Channel 4 Frequency]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .ddd dddd dddd&lt;/tt&gt;
| RW16
| Divider (d)
|-
! $88
| [[Sound#Sound Channel Volume|Sound Channel 1 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! rowspan="2" | $89
| [[Sound#Sound Channel Volume|Sound Channel 2 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
| [[Sound#Sound Channel 2 Voice Sample|Sound Channel 2 Voice Sample]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ssss ssss&lt;/tt&gt;
| RW8
| Sample (s)
|-
! $8A
| [[Sound#Sound Channel Volume|Sound Channel 3 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8B
| [[Sound#Sound Channel Volume|Sound Channel 4 Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;llll rrrr&lt;/tt&gt;
| RW8
| Left (l), Right (r)
|-
! $8C
| [[Sound#Sound Channel 3 Sweep Amount|Sound Channel 3 Sweep Amount]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| RW8
| Value (v)
|-
! $8D
| [[Sound#Sound Channel 3 Sweep Ticks|Sound Channel 3 Sweep Ticks]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...t tttt&lt;/tt&gt;
| RW8
| Ticks (t)
|-
! $8E
| [[Sound#Sound Channel 4 Noise Control|Sound Channel 4 Noise Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...e rttt&lt;/tt&gt;
| RW8
| Enable (e), Reset (r), Tap (t)
|-
! $8F
| [[Sound#Sound Wavetable Address|Sound Wavetable Address]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;wwww wwww&lt;/tt&gt;
| RW8
| Address &gt;&gt; 6 (w)
|-
! $90
| [[Sound#Sound Channel Control|Sound Channel Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;nsv. 4321&lt;/tt&gt;
| RW8
| Channel enable (1234)
Noise (n), Sweep (s), Voice (v)
|-
! $91
| [[Sound#Sound Output Control|Sound Output Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;H... hrrs&lt;/tt&gt;
| RW8
| Headphones connected (H)
Headphone output (h)
Speaker output (s), range (r)
|-
! $92
| [[Sound#Sound Channel 4 LFSR Register|Sound Channel 4 LFSR Register]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.rrr rrrr rrrr rrrr&lt;/tt&gt;
| R16
| PRNG state (r)
|-
! $94
| [[Sound#Sound Channel 2 Voice Volume|Sound Channel 2 Voice Volume]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... lLrR&lt;/tt&gt;
| RW8
| Left Half (l), Full (L)
Right Half (r), Full (R)
|-
! $95
| [[Sound#Sound Test|Sound Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;cc5? ??sh&lt;/tt&gt;
| RW8
| 
|-
! $96
| [[Sound#Sound Channel Output Right|Sound Channel Output Right]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $98
| [[Sound#Sound Channel Output Left|Sound Channel Output Left]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..ss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9A
| [[Sound#Sound Channel Output Sum|Sound Channel Output Sum]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .sss ssss ssss&lt;/tt&gt;
| R16
| Sample (s)
|-
! $9E
| [[Sound#Sound Speaker Main Volume|Sound Speaker Main Volume]]&lt;sup&gt;(color)&lt;/sup&gt;
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ..vv&lt;/tt&gt;
| RW8
| Main volume (v)
|-
! [[SoC]]
! $A0
| [[SoC#System Control|System Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;C??? swcl&lt;/tt&gt;
| RW8
| Cartridge OK (C), ROM wait state (s), ROM width (w),
Color system (c), Boot ROM lockout (l)
|-
! [[Timers]]
! $A2
| [[Timers#Timer Control|Timer Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... VvHh&lt;/tt&gt;
| RW8
| Horizontal enable (h), auto reload (H)
Vertical enable (v), auto reload (V)
|-
! [[SoC]]
! $A3
| [[SoC#System Test|System Test]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... u?vh&lt;/tt&gt;
| RW8
| UART test (u), VBlank Timer test (v), HBlank Timer test (h)
|-
! rowspan="4" | [[Timers]]
! $A4
| [[Timers#Timer Reload|Horizontal Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A6
| [[Timers#Timer Reload|Vertical Blank Timer Reload]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| RW16
| Ticks (t)
|-
! $A8
| [[Timers#Timer Counter|Horizontal Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! $AA
| [[Timers#Timer Counter|Vertical Blank Timer Counter]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;tttt tttt tttt tttt&lt;/tt&gt;
| R16
| Ticks (t)
|-
! [[SoC]]
! $AC
| ?
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... ...p&lt;/tt&gt;
| W8?
| Power off (p)
|-
! rowspan="2" | [[Interrupts]]
! rowspan="2" | $B0
| [[Interrupts#Interrupt Vector Offset|Interrupt Vector Offset]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;VVVV V...&lt;/tt&gt;
| W8
| Vector offset (V)
|-
| [[Interrupts#Interrupt Vector Request|Interrupt Vector Request]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;vvvv vvvv&lt;/tt&gt;
| R8
| Requested vector offset (v)
|-
! rowspan="2" | [[UART]]
! $B1
| [[UART#Serial Receive Data|Serial Receive Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| R8
| Receive buffer data (d)
|-
! $B1
| [[UART#Serial Transmit Data|Serial Transmit Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd&lt;/tt&gt;
| W8
| Transmit buffer data (d)
|-
! [[Interrupts]]
! $B2
| [[Interrupts#Interrupt Enable|Interrupt Enable]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| RW8
| Interrupt index (i)
|-
! rowspan="2" | [[UART]]
! $B3
| [[UART#Serial Status|Serial Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;eb.. .tor&lt;/tt&gt;
| R8
| Enable (e), Baud rate (b),
Transfer ready (t), Overrun (o), Receive ready (r)
|-
! $B3
| [[UART#Serial Control|Serial Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;ebO. ....&lt;/tt&gt;
| W8
| Enable (e), Baud rate (b), Reset Overrun (O)
|-
! [[Interrupts]]
! $B4
| [[Interrupts#Interrupt Status|Interrupt Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| R8
| Interrupt index (i)
|-
! [[Keypad]]
! $B5
| [[Keypad|Keypad Scan]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.iii oooo&lt;/tt&gt;
| RW8
| Input row (i), Output column (o)
|-
! rowspan="2" | [[Interrupts]]
! $B6
| [[Interrupts#Interrupt Acknowledge|Interrupt Acknowledge]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;iiii iiii&lt;/tt&gt;
| W8
| Interrupt index (i)
|-
! $B7
| [[Interrupts#Interrupt NMI Control|Interrupt NMI Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;...b ....&lt;/tt&gt;
| RW8
| Low battery (b)
|-
! rowspan="4" | [[EEPROM|Internal EEPROM]]
! $BA
| [[EEPROM#Internal EEPROM Data|Internal EEPROM Data]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;dddd dddd dddd dddd&lt;/tt&gt;
| RW16
| Data (d)
|-
! $BC
| [[EEPROM#Internal EEPROM Command|Internal EEPROM Command]]
|
| RW16
|
|-
! rowspan="2" | $BE
| [[EEPROM#Internal EEPROM Status|Internal EEPROM Status]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... p... ..RD&lt;/tt&gt;
| R16
| Protected (p), Ready (R), Done (D)
|-
| [[EEPROM#Internal EEPROM Control|Internal EEPROM Control]]
| style="text-align: right" | &lt;tt style="white-space: nowrap"&gt;.... .... pewr ....&lt;/tt&gt;
| W16
| Protect (p), Erase (e), Write (w), Read (r)
|-
! [[Mapper|Cartridge]]
! $C0&lt;br /&gt;...&lt;br /&gt;
$FF
| Cartridge I/O
|
| RW8
| Forwarded by the SoC
|}

== I/O port routing ==

The [[NEC V30MZ]] supports 16-bit I/O port addresses. The WonderSwan SoC routes them using the following algorithm:

* If an address is between &lt;code&gt;$00B8&lt;/code&gt; and &lt;code&gt;$00BF&lt;/code&gt; inclusive, it is routed to the internal EEPROM control block.
* If an address is between &lt;code&gt;$00C0&lt;/code&gt; and &lt;code&gt;$00FF&lt;/code&gt; inclusive, it is routed to the cartride bus.
* If an address's bits &lt;code&gt;0&lt;/code&gt; through &lt;code&gt;8&lt;/code&gt; inclusive are between &lt;code&gt;$000&lt;/code&gt; and &lt;code&gt;$0B7&lt;/code&gt; inclusive, they are routed to the SoC block.
* If none of these conditions are reached, open bus is read.

On the monochrome models, as well as color models in mono emulation, open bus is always &lt;code&gt;0x90&lt;/code&gt;.</text>
    <sha1>a23779a0257bca9e3dc3e6722358fbbf069ae7d8</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>Hyper Voice</title>
  <ns>0</ns>
  <id>30</id>
  <revision>
    <id>613</id>
    <parentid>272</parentid>
    <timestamp>2025-05-04T08:49:29Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* Hyper Voice Control ($6A, $6B) */</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="3262" xml:space="preserve">Hyper Voice is a headphone-only sample output channel introduced with the WonderSwan Color. It allows converting 8-bit signed and unsigned, mono and stereo samples into 16-bit signed PCM sent directly to the headphone output, after mixing with the traditional four channels.

== I/O Ports ==

{{Anchor|Hyper Voice Output}}
=== Hyper Voice Left Output ($64, $65 write) ===

=== Hyper Voice Right Output ($66, $67 write) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 ssss ssss  ssss ssss
 |||| ||||  |||| ||||
 ++++-++++--++++-++++- Signed 16-bit sample.
&lt;/pre&gt;

Unlike the [[Sound]] sample output registers, these can be written to - allowing for direct 16-bit sample output.

{{Anchor|Hyper Voice Input}}
=== Hyper Voice Input ($69 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ssss ssss
|||| ||||
++++-++++- Signed 8-bit sample.
&lt;/pre&gt;

Hyper Voice samples are typically written by [[DMA|Sound DMA]], but can also be written manually by the user. In the latter case, the "channel mode" setting is ignored - it always behaves as if it were in "stereo" mode, writing one channel after the other in sequence.

{{Anchor|Hyper Voice Control}}
=== Hyper Voice Control ($6A, $6B) ===

&lt;pre&gt;
15  bit  8  7  bit  0
 ---- ----  ---- ----
 .ttc ????  errr ssvv
  |||       |||| ||||
  |||       |||| ||++- Volume/Shift:
  |||       |||| ||      0 = 100%   1 = 50%
  |||       |||| ||      2 = 25%    3 = 12.5%
  |||       |||| ++--- Sample extension mode:
  |||       ||||         0 = Unsigned
  |||       ||||         1 = Unsigned, negated
  |||       ||||         2 = Signed
  |||       ||||         3 = Ignored
  |||       |+++------ Update sample rate/Divisor:
  |||       |            0 = 24000/1  = 24000 Hz
  |||       |            1 = 24000/2  = 12000 Hz
  |||       |            2 = 24000/3  =  8000 Hz
  |||       |            3 = 24000/4  =  6000 Hz
  |||       |            4 = 24000/5  =  4800 Hz
  |||       |            5 = 24000/6  =  4000 Hz
  |||       |            6 = 24000/8  =  3000 Hz
  |||       |            7 = 24000/12 =  2000 Hz
  |||       +--------- Enable: 0 = off, 1 = on
  ||+----------------- Reset: When 1 is written, the following DMA sample
  ||                          will be used for the left channel.
  ++------------------ Target channel layout:
                         0 = Stereo
                         1 = Mono, left channel only
                         2 = Mono, right channel only
                         3 = Mono, both channels
&lt;/pre&gt;

Internally, 8-bit values of the form &lt;tt style="white-space: nowrap"&gt;Vvvv vvvv&lt;/tt&gt; are transformed to signed 16-bit samples based on the scaling mode as follows, where &lt;code&gt;V&lt;/code&gt; represents the highest, 7th bit of the input value:

{| class="wikitable"
! Sample extension mode
! Bit representation
|-
| Unsigned
| &lt;tt style="white-space: nowrap"&gt;000 Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Unsigned, negated
| &lt;tt style="white-space: nowrap"&gt;111 Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Signed
| &lt;tt style="white-space: nowrap"&gt;VVV Vvvv vvvv 0000 0000&lt;/tt&gt;
|-
| Ignored
| &lt;tt style="white-space: nowrap"&gt;___ Vvvv vvvv 0000 0000&lt;/tt&gt;
|}

With the exception of the Ignored mode, the resulting value is shifted right by &lt;code&gt;Shift&lt;/code&gt; bits, and the result's bottom 16 bits are used as the sample.</text>
    <sha1>00e178c78daa9cbee53e5b32c94512cb48572ddb</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>MediaWiki:Sidebar</title>
  <ns>8</ns>
  <id>4</id>
  <revision>
    <id>615</id>
    <parentid>7</parentid>
    <timestamp>2025-05-07T01:43:36Z</timestamp>
    <contributor>
      <username>Fiskbit</username>
      <id>37</id>
    </contributor>
    <comment>Adds a link to the offline wiki snapshot on archive.org to the sidebar.</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="309" xml:space="preserve">* navigation
** mainpage|Wiki main page
** https://archive.org/details/WSDevWiki | Offline wiki snapshot
** https://forums.nesdev.org/ | NESdev Forums
** https://discord.gg/JSG4kuF8EK | NESdev Discord
** https://discord.gg/7rmX2QJ | WS Discord
** recentchanges-url|recentchanges
* SEARCH
* TOOLBOX
* LANGUAGES</text>
    <sha1>d7fc551bb290963aa84df289d5736570d6239e80</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>UART</title>
  <ns>0</ns>
  <id>23</id>
  <revision>
    <id>616</id>
    <parentid>554</parentid>
    <timestamp>2025-06-01T18:30:26Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <minor/>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="1767" xml:space="preserve">The WonderSwan's EXT port features an UART serial port operating with the following configuration:

* 9,600 or 38,400 bps (bauds per second),
* 8N1 (8 data bits followed by 1 stop bit, no parity).

This allows for effective maximum transfer speeds of 960 or 3840 bytes per second, respectively.

The hardware also features one-byte transmit and receive buffers, which allow for a slight delay in code when handling data to/from the console.

== Interrupts ==

The UART features two interrupts:

* UART Send Ready - constantly triggering (level interrupt) as long as the transmit buffer is empty (Serial Status bit 2),
* UART Receive Ready - constantly triggering (level interrupt) as long as the receive buffer contains a byte (Serial Status bit 0).

These interrupts are only triggering if the UART block is enabled.

== I/O ports ==

{{Anchor|Serial Receive Data}}
=== Serial Receive Data ($B1 read) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Receive buffer value
&lt;/pre&gt;

{{Anchor|Serial Transmit Data}}
=== Serial Transmit Data ($B1 write) ===

&lt;pre&gt;
7  bit  0
---- ----
dddd dddd
|||| ||||
++++-++++- Transmit buffer value
&lt;/pre&gt;

{{Anchor|Serial Status}}
=== Serial Status ($B3 read) ===

&lt;pre&gt;
7  bit  0
---- ----
eb.. .tor
||    |||
||    ||+- 1 if the receive buffer contains a byte
||    |+-- 1 on overrun (receive buffer overflow)
||    +--- 1 if the transmit buffer is empty (can transmit another byte)
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;

{{Anchor|Serial Control}}
=== Serial Control ($B3 write) ===

&lt;pre&gt;
7  bit  0
---- ----
ebO. ....
|||
||+------- Write 1 to reset overrun
|+-------- UART speed: 0 = 9600 bps, 1 = 38400 bps
+--------- UART enable: 0 = off, 1 = on
&lt;/pre&gt;</text>
    <sha1>189815041aa8761555885752dafa3c435b87c7af</sha1>
  </revision>
</page>
<page arvcontinue="20250423183822|601">
  <title>WonderWitch/FreyaBIOS/Sound</title>
  <ns>0</ns>
  <id>50</id>
  <revision>
    <id>617</id>
    <parentid>317</parentid>
    <timestamp>2025-06-14T10:49:25Z</timestamp>
    <contributor>
      <username>Asie</username>
      <id>351</id>
    </contributor>
    <comment>/* INT $15/AH=$00 - sound_init */ document</comment>
    <model>wikitext</model>
    <format>text/x-wiki</format>
    <text bytes="2306" xml:space="preserve">The Sound interrupt provides an abstraction layer for the WonderSwan's [[Sound|sound hardware]].

== Interrupts ==

=== INT $15/AH=$00 - sound_init ===

* AH = $00

Initializes the sound system, by:

* setting the sound wavetable address to 0x180,
* clearing the sound channel control (0x90) and output control (0x91) ports,
* clearing all other writable sound-related ports (0x80-0x8E, 0x94).

=== INT $15/AH=$01 - sound_set_channel ===

* AH = $01
* BL = [[Sound#Sound Channel Control|Channel Control]] value

=== INT $15/AH=$02 - sound_get_channel ===

* AH = $02

Return:

* AL = [[Sound#Sound Channel Control|Channel Control]] value

=== INT $15/AH=$03 - sound_set_output ===

* AH = $03
* BL = [[Sound#Sound Output Control|Output Control]] value

=== INT $15/AH=$04 - sound_get_output ===

* AH = $04

Return:

* AL = [[Sound#Sound Output Control|Output Control]] value

=== INT $15/AH=$05 - sound_set_wave ===

* AH = $05
* AL = Channel (0, 1, 2, 3)
* DS:DX = Pointer to waveform data (16 bytes)

=== INT $15/AH=$06 - sound_set_pitch ===

* AH = $06
* AL = Channel (0, 1, 2, 3)
* BX = Frequency divider (0 - 2047)

=== INT $15/AH=$07 - sound_get_pitch ===

* AH = $07
* AL = Channel (0, 1, 2, 3)

Return:

* AX = Frequency divider (0 - 2047)

=== INT $15/AH=$08 - sound_set_volume ===

* AH = $08
* AL = Channel (0, 1, 2, 3)
* BL = [[Sound#Sound Channel Volume|Channel Volume]] value

=== INT $15/AH=$09 - sound_get_volume ===

* AH = $09
* AL = Channel (0, 1, 2, 3)

Return:

* AL = [[Sound#Sound Channel Volume|Channel Volume]] value

=== INT $15/AH=$0A - sound_set_sweep ===

* AH = $0A
* BL = [[Sound#Sound Channel 3 Sweep Amount|Sweep Amount]]
* CL = [[Sound#Sound Channel 3 Sweep Ticks|Sweep Ticks]]

=== INT $15/AH=$0B - sound_get_sweep ===

* AH = $0B

Return:

* AL = [[Sound#Sound Channel 3 Sweep Amount|Sweep Amount]]
* AH = [[Sound#Sound Channel 3 Sweep Ticks|Sweep Ticks]]

=== INT $15/AH=$0C - sound_set_noise ===

* AH = $0C
* BL = [[Sound#Sound Channel 4 Noise Control|Channel 4 Noise Control]] value

=== INT $15/AH=$0D - sound_get_noise ===

* AH = $0D

Return:

* AL = [[Sound#Sound Channel 4 Noise Control|Channel 4 Noise Control]] value

=== INT $15/AH=$0E - sound_get_random ===

* AH = $0E

Return:

* AX = [[Sound#Sound Channel 4 LFSR Register|Channel 4 LFSR Register]] value</text>
    <sha1>97b78b4561b0581e8fa65801491de0edda9960b0</sha1>
  </revision>
</page>
</mediawiki>